SG3526

Pulse Width Modulation

Control Circuit
The SG3526 is a high performance pulse width modulator
integrated circuit intended for fixed frequency switching regulators
and other power control applications.
Functions included in this IC are a temperature compensated http://onsemi.com
voltage reference, sawtooth oscillator, error amplifier, pulse width
modulator, pulse metering and steering logic, and two high current MARKING
totem pole outputs ideally suited for driving the capacitance of power DIAGRAM
FETs at high speeds. 18
Additional protective features include soft start and undervoltage PDIP−18 SG3526N
lockout, digital current limiting, double pulse inhibit, adjustable dead N SUFFIX AWLYYWW
time and a data latch for single pulse metering. All digital control ports 18 CASE 707
are TTL and B−series CMOS compatible. Active low logic design 1
1
allows easy wired−OR connections for maximum flexibility. The
versatility of this device enables implementation in single−ended or A = Assembly Location
push−pull switching regulators that are transformerless or transformer WL = Wafer Lot
YY = Year
coupled. The SG3526 is specified over a junction temperature range of WW = Work Week
0° to +125°C.
• 8.0 V to 35 V Operation
• 5.0 V ±1% Trimmed Reference PIN CONNECTIONS
• 1.0 Hz to 400 kHz Oscillator Range
• Dual Source/Sink Current Outputs: ±100 mA +Error 1 18 Vref

• Digital Current Limiting −Error 2 17 VCC

• Programmable Dead Time Compensation 3 16 Output B
• Undervoltage Lockout
CSoft−Start 4 15 Ground
• Single Pulse Metering
Reset 5 14 VC
• Programmable Soft−Start
• Wide Current Limit Common Mode Range −CS 6 13 Output A
• Guaranteed 6 Unit Synchronization +CS 7 12 Sync

Shutdown 8 11 RDeadtime
Vref 18
Under− RT 9 10 CT
VCC 17 Reference Voltage
Regulator Lockout
15 (Top View)
Ground To Internal
12 Circuitry 14
Sync
11 VC
RDeadtime
9 Oscillator 13 ORDERING INFORMATION
RT
10
CT
Output Device Package Shipping
A
5 SG3526N PDIP−18 20 Units/Rail
Reset Soft
4 Start Toggle
CSoft−Start Memory F/F
3 F/F
Compensation Q
VCC S T
SQ Q
1 − RQ
+Error +
2 + R 16
−Error − Q
100 mV Amp
7 Output
+C.S. + Metering
6 B
− F/F
−C.S.
8
Shutdown

Figure 1. Representative Block Diagram

© Semiconductor Components Industries, LLC, 2006 1 Publication Order Number:

July, 2006 − Rev. 4 SG3526/D
 SG3526

MAXIMUM RATINGS (Note 1)

Rating Symbol Value Unit
Supply Voltage VCC +40 Vdc
Collector Supply Voltage VC +40 Vdc
Logic Inputs −0.3 to +5.5 V
Analog Inputs −0.3 to VCC V
Output Current, Source or Sink IO ±200 mA
Reference Load Current (VCC = 40 V, Note 2) Iref 50 mA
Logic Sink Current 15 mA
Power Dissipation PD mW
TA = +25°C (Note 3) 1000
TC = +25°C (Note 4) 3000
Thermal Resistance Junction−to−Air RθJA 100 °C/W
Thermal Resistance Junction−to−Case RθJC 42 °C/W
Operating Junction Temperature TJ +150 °C
Storage Temperature Range Tstg −65 to +150 °C
Lead Temperature (Soldering, 10 Seconds) TSolder ±300 °C

RECOMMENDED OPERATING CONDITIONS

Characteristics Symbol Min Max Unit
Supply Voltage VCC 8.0 35 Vdc
Collector Supply Voltage VC 4.5 35 Vdc
Output Sink/Source Current (Each Output) IO 0 ±100 mA
Reference Load Current Iref 0 20 mA
Oscillator Frequency Range fosc 0.001 400 kHz
Oscillator Timing Resistor RT 2.0 150 kΩ
Oscillator Timing Capacitor CT 0.001 20 μF
Available Deadtime Range (40 kHz) − 3.0 50 %
Operating Junction Temperature Range TJ 0 +125 °C
1. Values beyond which damage may occur.
2. Maximum junction temperature must be observed.
3. Derate at 10 mW/°C for ambient temperatures above +50°C.
4. Derate at 24 mW/°C for case temperatures above +25°C.

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 SG3526

ELECTRICAL CHARACTERISTICS (VCC = +15 Vdc, TJ = Tlow to Thigh [Note 6], unless otherwise noted.)
Characteristics Symbol Min Typ Max Unit
REFERENCE SECTION (Note 7)
Reference Output Voltage (TJ = +25°C) Vref 4.90 5.00 5.10 V
Line Regulation (+8.0 V ≤ VCC ≤ +35 V) Regline − 10 30 mV
Load Regulation (0 mA ≤ IL ≤ 20 mA) Regload − 10 50 mV
Temperature Stability ΔVref/ΔT − 10 − mV
Total Reference Output Voltage Variation ΔVref 4.85 5.00 5.15 V
(+8.0 V ≤ VCC ≤ +35 V, 0 mA ≤ IL ≤ 20 mA)

Short Circuit Current (Vref = 0 V) (Note 5) ISC 25 80 125 mA

UNDERVOLTAGE LOCKOUT
Reset Output Voltage (Vref = +3.8 V) − 0.2 0.4 V
Reset Output Voltage (Vref = +4.8 V) 2.4 4.8 − V
OSCILLATOR SECTION (Note 8)
Initial Accuracy (TJ = +25°C) − ±3.0 ±8.0 %
Frequency Stability over Power Supply Range Δfosc − 0.5 1.0 %
(+8.0 V ≤ VCC ≤ +35 V) Δ V
CC

Frequency Stability over Temperature Δfosc − 2.0 − %

(ΔTJ = Tlow to Thigh) Δ TJ
Minimum Frequency fmin − 0.5 − Hz
(RT = 150 kΩ, CT = 20 μF)

Maximum Frequency fmax 400 − − kHz

(RT = 2.0 kΩ, CT = 0.001 μF)

Sawtooth Peak Voltage (VCC = +35 V) Vosc(P) − 3.0 3.5 V

Sawtooth Valley Voltage (VCC = +8.0 V) Vosc(V) 0.45 0.8 − V
ERROR AMPLIFIER SECTION (Note 9)
Input Offset Voltage (RS ≤ 2.0 kΩ) VIO − 2.0 10 mV
Input Bias Current IIB − −350 −2000 nA
Input Offset Current IIO − 35 200 nA
DC Open Loop Gain (RL ≥ 10 MΩ) AVOL 60 72 − dB
High Output Voltage VOH 3.6 4.2 − V
(VPin 1−VPin 2 ≥ +150 mV, Isource = 100 μA)

Low Output Voltage VOL − 0.2 0.4 V

(VPin 2−VPin 1 ≥ +150 mV, Isink = 100 μA)

Common Mode Rejection Ratio (RS ≤ 2.0 kΩ) CMRR 70 94 − dB

Power Supply Rejection Ratio (+12 V ≤ VCC ≤ +18 V) PSRR 66 80 − dB
5. Maximum junction temperature must be observed.
6. Tlow = 0°C Thigh = +125°C
7. IL = 0 mA unless otherwise noted.
8. fosc = 40 kHz (RT = 4.12 kΩ ± 1%, CT = 0.01 μF ± 1%, RD = 0 Ω)
9. 0 V ≤ VCM ≤ +5.2 V.

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 SG3526

ELECTRICAL CHARACTERISTICS (continued)

Characteristics Symbol Min Typ Max Unit
PWM COMPARATOR SECTION (Note 10)
Minimum Duty Cycle DCmin − − 0 %
(VCompensation = +0.4 V)

Maximum Duty Cycle DCmax 45 49 − %

(VCompensation = +3.6 V)

DIGITAL PORTS (SYNC, SHUTDOWN, RESET)

Output Voltage V
(High Logic Level) (Isource = 40 μA) VOH 2.4 4.0 −
(Low Logic Level) (Isink = 3.6 mA) VOL − 0.2 0.4
Input Current ⎯ High Logic Level μA
(High Logic Level) (VIH = +2.4 V) IIH − −125 −200
(Low Logic Level) (VIL = +0.4 V) IIL − −225 −360

CURRENT LIMIT COMPARATOR SECTION (Note 12)

Sense Voltage (RS ≤ 50 Ω) Vsense 80 100 120 mV
Input Bias Current IIB − −3.0 −10 μA
SOFT−START SECTION
Error Clamp Voltage (Reset = +0.4 V) − 0.1 0.4 V
CSoft−Start Charging Current (Reset = +2.4 V) ICS 50 100 150 μA
OUTPUT DRIVERS (Each Output, VC = +15 Vdc, unless otherwise noted.)
Output High Level VOH V
Isource = 20 mA 12.5 13.5 −
Isource = 100 mA 12 13 −
Output Low Level VOL V
Isink = 20 mA − 0.2 0.3
Isink = 100 mA − 1.2 2.0
Collector Leakage, VC = +40 V IC(leak) − 50 150 μA
Rise Time (CL = 1000 pF) tr − 0.3 0.6 μs
Fall Time (CL = 1000 pF) tf − 0.1 0.2 μs
Supply Current ICC − 18 30 mA
(Shutdown = +0.4 V, VCC = +35 V, RT = 4.12 kΩ)
10. fosc = 40 kHz (RT = 4.12 kΩ ± 1%, CT = 0.01 μF ± 1%, RD = 0 Ω)
11. 0 V ≤ VCM ≤ +5.2 V
12. 0 V ≤ VCM ≤ +12 V

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 SG3526

V ref , REFERENCE VOLTAGE (V)

5.0

50 mV 4.0
Spec
Limit 3.0

2.0

1.0

−75 −50 −25 0 25 50 75 100 125 150 1.0 2.0 3.0 4.0 5.0 10 20 30 40
TJ, JUNCTION TEMPERATURE (°C) VCC, SUPPLY VOLTAGE (V)

Figure 2. Reference Stability over Temperature Figure 3. Reference Voltage as a

Function Supply Voltage

8.0

7.0
SHUTDOWN VOLTAGE (V)
A Vol , VOLTAGE GAIN (dB)

6.0
80
5.0
60
4.0
40
3.0
20 1 +
_ 3 2.0
2
100 CComp
0 pF 1.0

0
10 100 1.0 k 10 k 100 k 1.0 M 10 M 25 50 75 100 125 150 175 200
f, FREQUENCY (Hz) DIFFERENTIAL INPUT VOLTAGE (mV)

Figure 4. Error Amplifier Open Loop Figure 5. Current Limit Comparator Threshold
Frequency Response
V sat , OUTPUT DRIVER SATURATION VOLTAGE (V)

8.0 2.5

7.0
2.0
6.0
RESET VOLTAGE (V)

5.0
1.5
4.0

3.0 1.0

2.0
0.5
1.0

0 0
0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 2.0 5.0 10 20 50 100 200
Vref, REFERENCE VOLTAGE (V) OUTPUT DRIVER SINK CURRENT (mA)

Figure 6. Undervoltage Lockout Characteristic Figure 7. Output Driver Saturation Voltage as a

Function of Sink Current

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 SG3526

2.5 200
RD = 0 Ω
V SAT , SATURATION VOLTAGE (V)
100
2.0

R T, TIMING RESISTOR (k Ω )
50
1.5
20
1.0
10

0.5 5.0

0 2.0
2.0 5.0 10 20 50 100 200

10
0.1

1.0

100
0.01

1000
20
50
0.2
0.5

2.0
5.0

200
500
0.02
0.05
0.002
0.005
IC, SINK CURRENT (mA)
OSCILLATOR PERIOD (ms)

Figure 8. VC Saturation Voltage as a Figure 9. Oscillator Period

Function of Sink Current

VCC

Q6

Vref
Q5 Vref
125
μA
Q11
Q3 Q4
50μA 50μA
Q12 To Reset
100μA R1
To Driver A
14μA 100 14μA 3 Compensation
+ To Driver B
μA Q10 100μA
1.2V
Q7 Q8 Q9 Bandgap −
Q1 Q2 Reference
1.0k 500 1.0k 500 R2

1
− Error + Error

Figure 10. Error Amplifier Figure 11. Undervoltage Lockout

Memory
F/F The metering Flip−Flop is an asynchronous data latch
which suppresses high frequency oscillations by allowing
Sync S only one PWM pulse per oscillator cycle.
S Q R Q Clock
PWM D
Q PWM The memory Flip−Flop prevents double pulsing in a
push−pull configuration by remembering which output
Metering produced the last pulse.
F/F

Figure 12. Pulse Processing Logic

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 SG3526

APPLICATIONS INFORMATION

Negative
Output
R1 Voltage
R3 1 + R2 1 +
Vref Vref
C* 2 − 2 −
R2 R3
R1 Positive
27 17 Reference 18 Output
VCC Vref Gnd Voltage Gnd
Regulator
+
15 10μF R1 + R2 R1
Vout = Vref Vout = Vref
R2 R2
Gnd
R1R2
R3 =
R1 + R2
* May be required with some types of transistors

Figure 13. Extending Reference Figure 14. Error Amplifier Connections

Output Current Capability

Output to Load +
RS
11 12
SG3526 Sync − 6
8 Vout
R1
RD 9 10 + 7

R2
Gnd −
RT CT
Vout R1
0.1 V +
R1 + R2 0.1 V
I(max) = ISC =
RS RS

Figure 15. Oscillator Connections Figure 16. Foldback Current Limiting

+12V

Vref 14
VC
A 13
100
Ramp −
1 μA
+ Error + PWM SG3526
Error +
2 − Amp
− Error 16
B
Q2 Gnd
5 Q1
Reset

To
Q3 Undervoltage
Lockout CSoft−Start The totem pole output drivers of the SG3526 are ideally
suited for driving the input capacitance of power FETs at
high speeds.

Figure 17. Soft−Start Circuity Figure 18. Driving VMOS Power FETs

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 SG3526

+V
Supply
R1 C2 T1

14 R4
VC 13 D1
A
+V
Supply D2 Q1
5 16
R B
R1 SG3526
C1 8 7
S +CS
14 Q1
VC 13 R3
A 4 6
CS −CS
T2 Gnd
SG3526 15
Q2 C2 C1 R2
16
B
Gnd
15 T1

In the above circuit, current limiting is accomplished by using the

current limit comparator output to reset the soft−start capacitor.

Figure 19. Half−Bridge Configuration Figure 20. Flyback Converter with

Current Limiting

+V Supply Q1 To +V Supply
R1 Output
Filter R1
C1
R2 14
VC 13 R2 T1
A Q1
14
VC C2
13 SG3526
A
SG3526 16 R3
16 B Q2
B Gnd
Gnd
15
15

Figure 21. Single−Ended Configuration Figure 22. Push−Pull Configuration

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 SG3526

PACKAGE DIMENSIONS

PDIP−18
N SUFFIX
CASE 707−02
ISSUE D

J NOTES:
1. POSITIONAL TOLERANCE OF LEADS (D), SHALL
BE WITHIN 0.25 mm (0.010) AT MAXIMUM
MATERIAL CONDITION, IN RELATION TO SEATING
18 10 PLANE AND EACH OTHER.
B L 2. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
1 9
3. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
4. CONTROLLING DIMENSION: INCH.

A M INCHES MILLIMETERS
DIM MIN MAX MIN MAX
A 0.875 0.915 22.22 23.24
C B 0.240 0.260 6.10 6.60
C 0.140 0.180 3.56 4.57
D 0.014 0.022 0.36 0.56
F 0.050 0.070 1.27 1.78
N K G 0.100 BSC 2.54 BSC
H 0.040 0.060 1.02 1.52
F D SEATING J 0.008 0.012 0.20 0.30
PLANE K
H G L
0.115 0.135
0.300 BSC
2.92 3.43
7.62 BSC
M 0_ 15_ 0_ 15 _
N 0.020 0.040 0.51 1.02

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