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MOSFET Basics PDF
MOSFET Basics PDF
Introduction
More than 99 % of all ICs are MOSFETs used for random-access
memory, flash memory, processors, ASICs (application-specific
integrated circuits), and other applications.
In the year 2000, 106 MOSFETs per person per year were manufactured.
All MOSFETs are transistors that consist of metal (M) SiO2 (oxide or O)
and Si (semiconductor or S).
(1) VDS = 0,
(2) VDS > 0, and
(3) VDS >> 0.
VGS = 0
In this case, no DS current flows. Why? Because we have n+pn+
junctions, that is two back-to-back diodes, one of which will be in the
reverse direction and therefore block the current flow.
VGS > 0
We have a moderately positive gate voltage.
This mode is the depletion mode of operation. Holes in
semiconductor are repelled by positive charge on the gate. The
semiconductor is depleted of free holes and a depletion layer is
created.
VGS >> 0
We have a strongly positive gate voltage.
This mode is the inversion mode of operation. Electrons are induced
in the semiconductor near the oxide-semiconductor interface. An
electron current flows from S to D. The magnitude of the gate voltage
determines the magnitude of the SD current.
The electric field in the oxide field is highest at the source end of the
channel. Thus many electrons are induced near the source.
The electric field in the oxide field is lowest at the drain end of the
channel. Thus few electrons are induced near the drain.
• ID increases
• Fewer electrons at the drain end of the channel
Î ID-vs.-VDS begins to have negative curvature.
Electric field in the oxide is very low or zero at the drain end of the
channel. Thus there are no free electrons near drain. The channel is
pinched off.
Illustration:
Electrons traverse the space charge region of the reverse biased pn+
junction.
ΦM = ΦSemi
In this illustration you can consider the source to be above the page
and the drain to be below the page. The metal is the gate.
p ( x) = ni e(Ei − E F ) kT (1)
ΦS = 0 (4)
e Φ ( x) = Eibulk − Ei ( x) (5)
ΦS = Φ ( x = 0) (6)
p ( x) = ni e(Ei − EF ) kT
[ Eibulk − eΦ ( x ) − EF ] kT
= ni e
( Eibulk − EF )
= ni e kT
e − e Φ ( x ) kT
p ( x) = p0 e −e Φ ( x ) kT (7)
Band diagram:
2ε
WD = ΦS
e NA (8)
It is Φ(x) > 0 Î p < p0, that is, we have a depleted layer near the
surface.
where
p = ni e( Ei − EF ) kT (11)
NA
e ΦS = 2 e Φ F = 2 kT ln
ni (Onset of strong inversion) (12)
2ε 2ε kT N
WD, max = 2 ΦF = 2 ln A
eN A eN A e ni
NA ε kT
WD, max = 2 ln
2 ni (13)
e NA
Solution: It is
ni = 1010 cm −3 , εr = 9
NA ε kT
WD, max = 2 2 ln
e NA ni
3D −
QD = e NA for 0 ≤ x ≤ WD (14)
3D
QD = 0 for x > WD (15)
where “Q3D” is the “charge per unit volume”. Analogously, we will denote
a charge per unit area as “Q2D”.
2D
QM = − QS2D 2D
= − QD (
+ Qn2D ) (16)
2D
QD = − eN AWD (18)
V = VOX + Φ S (19)
where
VOX = − E d OX
= − (QS2D ε OX ) d OX
(20)
= − QS2D 2D
COX
QS2D
QS2D
VOX = − 2D =
COX ε OX d OX (21)
Qn2D ≈ 0 (23)
ΦS = 2Φ F (25)
Insertion of Eqs. (23) – (25) into Eqs. (19) and (21) yields
2D e N A WD, max
QD
Vth = − 2D + 2 Φ F = 2D
+ 2 ΦF
COX COX (26)
Thus the threshold voltage is the sum of a voltage drop in the oxide and
in the semiconductor at the onset of strong inversion. Eq. (26) applies to
the ideal MOS structure.
2D ε OX
COX =
d OX (27)
2D εS
CD =
WD (28)
The following illustration shows the CMOS2D - vs. - V curve. Note that WD
depends on V.
−1
⎛ d OX WD, max ⎞
2D
CMOS, min = ⎜⎜ + ⎟⎟
⎝ ε OX εS ⎠ (31)
VG > 0 Accumulation
Holes accumulate at the O-S interface
2D
CMOS = ε OX d OX
VG > 0 Depletion
Depletion layer thickness increases with V
Φ MS = Φ M − ΦS (32)
There are usually charges trapped in the oxide, for example Na+
(sodium) ions. The oxide charges produce a voltage:
2D 2D
V = QOX COX (33)
QOX
V FB = Φ MS −
COX (34)
Eq. (26) holds for the ideal MOS structure. In the case of a real MOS
structure, the effects of the work function difference and oxide charges
must be included. The threshold voltage for the real MOS structure is
given by:
2D 2D
QOX QD
V th = Φ MS − 2D
− 2D
+ 2 ΦF
COX COX (35)
2D
QM = QS2D = Qn2D + QD
2D
(36)
Qn2D = QS2D − QD
2D
(37)
1 x 1 2D
E = −
ε ∫ −∞ ρ( x ) d x = −
ε
Q
(38)
Vth
Qn2D = − ε OX E OX ( x) + ε OX
d OX
VGS − V ( x) Vth
= − ε OX + ε OX (39)
d OX d OX
ε OX
Qn2D = − [VGS − Vth − V ( x) ] (40)
d OX
ID = Qn2D ( x) v( x) Z (41)
= Qn2D ( x) [ − µ n E ( x) ] Z (42)
dV ( x )
= Qn2D ( x) µ n Z
dx (43)
ε OX
Z µ n [ VGS − Vth − V ( x) ]
dV ( x )
ID = −
d OX dx (44)
LG VDS
ε OX µ Z
ID ∫ dx = −
d OX ∫ (VGS − Vth − V ( x)) dV ( x) (45)
0 0
ε OX µ Z ⎡ 1 2 ⎤
( −) I D = ⎢ (VGS − Vth ) VDS − VDS ⎥ (46)
d OX LG ⎣ 2 ⎦
εOX µ Z 1 2 ε µZ
I D, sat = VDS, sat = OX (VGS − Vth )2 (48)
d OX LG 2 2 d OX LG
dI D, sat εOX µ Z
g m, sat = = ( VGS − Vth ) (49)
dVGS d OX LG
Questions:
What are the units of gm / Z?
How does gm depend on Z?
How does the input capacitance (CGS) depend on Z?
What is the relevance of gm / CGS?
How does gm / CGS depend on Z?