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Support for Layer 2 and Layer 3 While the cost difference between OC-192c POS
and 10 GbE WAN PHY has created the perception
SONET/SDH interfaces deployed in routers have
that POS interfaces actually have greater function-
been designed to support Packet over SONET/SDH
ality, this is a myth. By eliminating the need to
(POS) as defined in RFCs 1619, 1662 and 2615.
re-encapsulate Ethernet into PPP, 10 GbE WAN
Even though most IP packets originate from Ethernet
PHY supports IP as well as direct transmission and
networks as packet-only interfaces, support for
switching of Ethernet frames more efficiently and
transmission and switching of Ethernet frames on
cost effectively than OC-192 POS.
POS is explicitly excluded. POS interfaces actually
strip off the Ethernet header and add their own link
layer header, for example PPP or HDLC framing. This
Rich Diagnostic and Maintenance
design aspect of POS interfaces has led to multiple
Capabilities
efforts to carry Ethernet over SONET/SDH: ITU X.86
and T1X1 for OC-3 through OC-48, and 10 GbE The misperception exists that if you want rich
WAN PHY for OC-192. diagnostic and maintenance capabilities across
OC-192 links you need to buy OC-192 POS
interfaces. The truth is that 10 GbE WAN PHY
provides equivalent, and in some cases enhanced,
diagnostic and maintenance functionality. The
reason for the misperception lies in the methods
used for the various functions. SONET approaches
diagnostics from the perspective of managing a
TDM link where all management information is
carried outside of the TDM data. 10 GbE approaches
the problem from a data link perspective where
much of the diagnostic information is carried
within the data frames. The 802.3ae standards body
recognized this fact when designing the WAN
PHY specification and included only the SONET
diagnostic and maintenance functionality not
already present in Ethernet.
Link availibilty, proper cable Link detect, interface up/down Loss of signal, signal fail
Long links (collision), noisy link or faulty Tx/Rx Runts NA (fixed frame length)
Noisy link or faulty Tx/Rx CRC B1, B2, B3, FEBE/REI, signal degrade
As shown in Table 1, 10 GbE WAN PHY makes mechanisms for many features (Table 1). Much of the
use of the SONET overhead bits to provide: difference between SONET and Ethernet can be
boiled down to the fact that SONET is synchronous,
• Same diagnostics capability
it relies on counting a specific number of clock
- Loss of signal
cycles to identify the start of a frame, and Ethernet is
- Framing errors/loss of frame
asynchronous, frames may come at any time. The
- Coding violations
synchronization diagnostics in SONET, for the most
(Line and Path RDI and Line and Path AIS)
part, do not apply in the Ethernet world. If the SONET
- Errored seconds
link does lose synchronization, the Ethernet layer
- Severely errored seconds
detects that the link is down without having to look
- Delay triggers (currently not supported in FTOS)
at the SONET synchronization overhead bits.
- Loss of synchronization (not needed)
• Same error/performance monitoring
SONET APS and 10 GbE LAG
- B1, B2, B3
- J0, J1 ( J1 is currently not visible in the FTOS CLI) One area of concern is 10 GbE WAN PHY’s lack of
support for SONET automatic protection switching
• Same defect/alarms
(APS). In the POS world, support for APS was an
- FEBE
interesting feature because there is no equivalent in
- RDI
the IP world. Nevertheless, APS on POS interfaces is
- AIS
significantly different from the APS supported on
SONET add-drop multiplexers that must participate
Ethernet has built in mechanisms for detecting link
in a ring topology. POS interfaces only support Linear
state and frame errors so it does not need to rely on
APS, or the ability to switch from a failed primary
the SONET capabilities to provide this information
point-to-point connection to an idle backup.
even though it can use both Ethernet and SONET
SECTION
LOF = 0 LOS = 0 BIP(B1) = 0
LINE
AIS = 0 RDI = 0 FEBE = 0 BIP(B2) = 0
PATH
AIS = 0 RDI = 0 LOP = 0 FEBE = 0 BIP(B3) = 0
B1 Section BIP-8 Bit interleave parity for section error monitoring of previous frame
H1, 2 Pointer byte Location of SPE in each STS relative to the pointer (in bytes). Also used for frequency justification.
H3 Pointer action Used to adjust the fill of input buffers in case of negative Fixed: 0x00,
pointer justification. Also used for frequency justification. no pointer action required
B2 Line BIP-1536 Bit interleave parity for line error monitoring of previous frame
K1 Linear APS Request (bits 1-4): specifies automatic protection switching request type Fixed: 0x0, no request
or Ring APS
(not used by WAN PHY) Channel (bits 5-8): channel to switch from Fixed: 0x1, working channel
K2 Linear APS Channel (bits 1-4): channel to switch to Fixed: 0x0, working channel
or Ring APS
(not used by WAN PHY) Redundancy (bit 5): 1+1 or 1:n Fixed: 0 1+1
Status (bits 6-8): indicates line AIS (111), line RDI (110), bi-directional (101), Indicate line RDL, AIS
unidirectional (100), rest undefined or set to zero
J1 Path trace 16 J1 bytes in consecutive WIS frames make up a user programmable path message that
repeats. First byte is 0x00 for no message.
B3 Path BIP-8 Bit interleave parity for path error monitoring of previous frame
G1 Path status REI/FEBE (bits 1-4): reports detected block errors (B3) for far end
RDI (bit 5): remote defect indicator
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San Jose, CA 95134 USA their respective holders. Information in this document is subject to change without notice. Certain features may not yet be generally
available. Force10 Networks, Inc. assumes no responsibility for any errors that may appear in this document.
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