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CHAPTER 5
5.1 INTRODUCTION
The operating rules for PSC PWM when the number of level n = 5
are given below:
( K − 1) ∏
Pcr =
n (5.1)
L −1
N=
2 (5.2)
1
Voi = ∫ Voi (t)dt
Tcr (5.3)
Ton
Voi = .Vdc
Tcr (5.4)
Voi = V (5.5)
Where, Voi is the output voltage of cell i, and Ton is the time
interval, determined by the comparison between the reference and the carrier
signals.
5.2.1 Results
⎧ max(Va , Vb , Vc ) + min(Va , Vb , Vc ) ⎫
Voff = ⎨ ⎬
⎩ 2 ⎭ (5.6)
5.3.1 Results
The results of CSF, VSF and PSC PWM techniques using SH and
SFO methods are analyzed and THD as well as output voltage values are
compared as shown in Table 5.1, Figures 5.15 and 5.16.
The THD value and output voltage values are small in SH PWM
technique whereas the values are high in SFO PWM technique. It is observed
finally that with minimised THD, SH PWM method gives better results and
the SFO PWM technique is the most suitable in achieving the increased
output voltage.
117
Table 5.1 Output voltage and THD for CSF, VSF and PSC PWM
techniques
Figure 5.15 % of THD value for CSF, VSF and PSC PWM techniques
118
Figure 5.16 Output voltage for CSF, VSF and PSC PWM techniques
The Figure 5.17 shows the hardware setup for three phase cascaded
multilevel inverter. The hardware setup consists of six single phase inverter
sets using FSBB20CH60 Smart Power Module (SPM), six 100V DC power
supplies and Digital storage oscilloscope. The inverter topology is based on
the series connection of single phase inverters with separate DC sources. The
details of FSBB20CH60 SPM Data sheet is given in Appendix 1.
119
1) Design entry
2) Design synthesis
3) Design implementation
4) Design verification
The source code is written in the VHDL. After writing the code
syntax check has been performed on the code to verify whether code was
properly written using correct syntax [73-76].
• Map: Group logical symbols from the net list (gates) into
physical components (Slices and IOBs).
• Place and route: Place components onto the chip, connect the
components, and extract timing data into reports.
routing which places the logic blocks of the design into FPGA and route them
together. This operation produces NCD output file.
Xilinx device programming uses IMPACT to create a BIT file for debugging
and downloads it into the target device. Once the program is dumped to
FPGA kit, it acts as a PWM based FPGA controller and generates gate drive
switching pulses. These pulses are connected to optoisolator circuit for
preventing the ground sharing between the FPGA-processor and H-bridge
power module. The output of optoisolator is connected through driver to each
switching devices for controlling the PWM three phase cascaded multilevel
inverter.
The output LEDs are used to verify the conditions or to debug the
code. The I/O lines from FPGA-1 are used to interface external peripherals.
To interface external peripheral devices, 26 I/O lines from FPGA-1 is
terminated in 26 pin header.
129
The Figure 5.21 shows the hardware setup for three phase five level
cascaded inverter. The hardware setup consists of
5.6 SUMMARY