Ipad Air 2 Equemático PDF

L8106
J3910 U4750
U7503 L8152 L8111 L3210
L8110
U2120 Y0600
U8650 L8104
L2855
U0790 U4600
L8105
C8141 U3200
L2856
U4003
D4001
J4500
U3500
D8430
U7500
L2854 L2852
U6201 U4800
U5403
L6503
J2701
U6202
U6301
U6401
U1800
U4190
FL6501
U2180 D3591 U4770
L8429
L8100
L8101
C1454
C1451
C1452
L3260
U5601
L4612
L4622
L4632
L4602
U5401 D8458 D8428 U7900
C1455
C1456
C1453
L4642
U4100
J7900
L2853
U4150
FL6401
J4040
FL6502
C1420
C1412
C1405
C1430
C1410
FL6901
U6302 D8800
J4020
L8103
L8102
Q8823
U3250
DZ8820
U6501
U2150
C1406
C1411
U6001
FL6402
U0600
FL7002
FL6801
C1413
L7410
FL6601 U7412
U6103
FL6403 U5402
L8151
U8100
FL7401
C1431
C1421
U6601
C1414
FL6602 U8680
J7004
L5903
L3531 L3530
U6102 U2000
C1432
C1422
C1415
U7413
J3150
Q8804
L8109
DZ3590
FL7003
DZ3692
Q8900
U2260
DZ3691
DZ3503
DZ3502
DZ3500
DZ3501
L5102
C1433
C1423
L8812
U6101 U1600 U1700
C1424
C1434
FL6102
FL6101
U5000
U7800 Y5201 L8107 L8150 L8108

U5901
U6801 U7410
C1435
C1425
U5801
C8140
U8670
C1092
U5201
J7410 J8900
U5962 U7001
C1438 C1437 C1436 C1426 C1416
C1094
C8190 J3700
J7800 U3000
C1093 C1095 C1097 C1096
J7002 J7420
J7001
備註：" DZ3500,DZ3501,DZ3502,DZ3503,DZ3590"
VIETMOBILE.VN
以上位置使用 337S0104,377S0155 為有極性;使用377 S0184
C1451
SCHEMATIC DIAGRAM
C1454
C1455
C1456
則無極性！
C1452
C1453
C1410
C1405
C1412
C1430
C1420
C1406
IPAD AIR 2
C1411
U2140
C1413
C1431
C1421
L2811
C1414
L2810 L2812
C1415
C1432
C1422
J2700
C1433
C1423
C1435 C1434
C1424
C1425
C1438 C1437 C1436 C1426
J3100
C1416
C1097 C1096
D3100
D3101
RL EVT MLB B 820-3633-05 TOP 面極性圖20140503
8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
MLB B - PVT B 0003279770 PRODUCTION RELEASED 2014-09-29
LAST_MODIFIED=Mon Sep 29 18:09:18 2014

RADIO_MLB SYNC VER 0.109.0
WIFI_DEV SYNC VER 0.68.0
ROTTERDAM SYNC VER 0.11.0
D D
PDF CSA CONTENTS
TABLE_TABLEOFCONTENTS_HEAD
SYNC MASTER DATE PDF CSA CONTENTS
SYNC MASTER DATE PDF CSA CONTENTS
SYNC MASTER DATE
1
TABLE_TABLEOFCONTENTS_ITEM
1 TABLE OF CONTENTS N/A N/A 26
36 IO: FILTERS N/A N/A 51
66 CELL: HB SWITCH RADIO 09/29/2014
2
2 BLOCK DIAGRAM: SYSTEM N/A N/A 27
37 IO: HOTBAR PADS N/C N/A 52
67 CELL: RX DIV (1/2) RADIO 09/29/2014
3 4 BOM TABLES N/A N/A 28 39 IO: BUTTON FLEX CONN N/A N/A 53 68 CELL: RX DIV (2/2) RADIO 09/29/2014
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
4
5 SOC: MISC & ALIASES N/A N/A 29
40 GRAPE: STINGER & CONN N/A N/A 54
69 CELL: GPS RADIO 09/29/2014
5
6 SOC: MAIN N/A N/A 30
41 GRAPE: CUMULUS N/A N/A 55
70 CELL: ANT FEEDS & GPS (J82) RADIO 09/29/2014
6
7 SOC: I/OS N/A N/A 31
45 DISPLAY: CONNECTOR N/A N/A 56
74 WIFI/BT: J82 ANT INTERFACE WIFI 09/29/2014
7
8 SOC: NAND N/A N/A 32
46 DISPLAY: EDP SUPPORT N/A N/A 57
75 WIFI/BT: WIFI/BT MODULE WIFI 09/29/2014
8
9 SOC: MIPI, ISP N/A N/A 33
47 MESA: SUPPORT N/A N/A 58
78 SENSOR: HAMMERHEAD N/A N/A
9 10 SOC: EDP, PCIE N/A N/A 34 48 ROTTERDAM ROTTERDAM 05/13/2014 59 79 CELL: SIM AND ANT SW FILT N/A N/A
C
10 11 SOC: DDR N/A

35 50 CELL: PROBE PTS & DEBUG CONN RADIO

60 81 PMU: ARABELA (1/3) N/A

C
N/A 09/29/2014 N/A
11
12 SOC: IO POWER N/A N/A 36
51 CELL: BB PMU (1/2) RADIO 09/29/2014 61
82 PMU: ARABELA (2/3) N/A N/A
12 13 SOC: SOC POWER AND GND N/A N/A 37 52 CELL: BB PMU (2/2) RADIO 09/29/2014 62 83 PMU: ARABELA (3/3) N/A N/A
13
14 SOC: CPU, GPU, SRAM POWER N/A N/A 38
53 CELL: BASEBAND (1/2) RADIO 09/29/2014 63
84 POWER: J82 SPECIFIC N/A N/A
14
16 DDR: CHANNEL 0 AND 1 N/A N/A 39
54 CELL: BASEBAND (2/2) RADIO 09/29/2014 64
86 POWER: EXTERNAL SWITCHES N/A N/A
15 17 DDR: CHANNEL 2 AND 3 N/A N/A 40 55 CELL: BASEBAND (3/3) RADIO 09/29/2014 65 88 PMU: CHARGER BUCK N/A N/A
16
18 NAND N/A N/A 41
56 CELL: RF TXCVR (1/3) RADIO 09/29/2014 66
89 POWER: BATTERY CONN N/A N/A
17
20 SENSOR: OSCAR N/A N/A 42
90 SOC: DEBUG N/A N/A
18
21 SENSOR: CARBON, PHOS+, MAGN N/A N/A 43
91 ALIASES: BB/WLAN/BT N/A N/A
19
22 SENSOR: HALL EFFECT N/A N/A 44
59 CELL: QFE DCDC RADIO 09/29/2014 69
93 TEST: TPS/HOLES/FIDUCUALS N/A N/A
B 20
27 CAMERA: CAM CONNS N/A N/A 45
60 CELL: 2G PA RADIO 09/29/2014 70
95 TEST: EE TP/PP N/A N/A B
21
28 CAMERA: CAM SUPPORT N/A N/A 46
61 CELL: VLB PAD RADIO 09/29/2014 71
96 TEST: CELL EE TP/PP N/A N/A
22
30 AUDIO: L81 CODEC N/A N/A 47
62 CELL: LB PAD RADIO 09/29/2014 72
121 POWER: ALIASES N/A N/A
23
31 AUDIO: HP/DMIC FLEX CONNS N/A N/A 48
63 CELL: MB PAD RADIO 09/29/2014 73
155 BB/WLAN VOLTAGE ATTRIBUTES N/A N/A
24
32 AUDIO: SPEAKER AMPS N/A N/A 49
64 CELL: HB PAD RADIO 09/29/2014
25
35 IO: TRISTAR N/A N/A 50
65 CELL: ANTENNA SWITCH RADIO 09/29/2014
A A
DRAWING TITLE
SCHEM,MLB-B,X190
DRAWING NUMBER SIZE
Apple Inc. 051-0301 D

SCH AND BOARD P/N R
REVISION
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

TABLE_5_HEAD
B.0.0
TABLE_5_ITEM
NOTICE OF PROPRIETARY PROPERTY: BRANCH
DRAWING
051-0301 1 SCH,MLB-B,J82 SCH1 CRITICAL THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
TABLE_5_ITEM
THE POSESSOR AGREES TO THE FOLLOWING: PAGE

820-3633 1 PCBF,MLB-B,J82 PCB1 CRITICAL I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 155
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET
IV ALL RIGHTS RESERVED 1 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ISP0 REAR CAMERA

ISP0_I2C
CSA 27
SPI3 MIPI0C
COMPASS PHOSPHOROUS+ GRYO ACCEL

ISP1
CSA 21 SPI CSA 21 SPI CSA 21 SPI CSA 21 SPI ISP1_I2C FRONT CAMERA D
D MIPI1C CSA 27
PROX SENSOR
CSA 78 I2C
I2S4 BT MIMO
UART3 WIFI/BT WIFI/BT ANT
TEMP SENSOR
CSA 78
I2C PCIE1 WLAN
UART2 CSA WIFI/BT ANT
HELIUM COEX
CSA 78 I2C
CAPRI
OSCAR
NOT ON
SPI (M)
I2C
GRAPE CELLULAR/
CSA 41
GPS WIFI-ONLY CONFIG
OSCAR
CSA 20 COEX PRIMARY CELLULAR ANT
CUMULUS CUMULUS I2C UART
UART8 HSIC0 HSIC DIVERSITY CELLULAR ANT
UART
GPIO IPC
C UART
UART1 UART
GPS ANT C
STINGER BASEBAND
USB SIM CARD
CSA 40 I2C
TRISTAR
CSA 35
USB1
DISPLAY/ ALS (MIC)
UART2
TOUCH PANEL I2C
I2C0 I2C
I2C MESA ALS (AJ)
I2C2 USB2.0 USB0
SPI I2C UART0 UART1
UART6 UART0
SPI2 JTAG
I2C1 JTAG
B B
SPI1 SPI MBUS DIG
EDP LPDP
BACKLIGHT I2S0 ASP
I2S1 XSP
HP
L81 MIC1
AUDIO CODEC
CSA 30 MIC2
RIGHT
BMU AMP
PMU SPEAKER
CSA 33
ARABELA BATTERY IO FLEX
CSA 81-83
NC -- DWI1 I2S3
AMP LEFT
HDQ CSA 32
SPEAKER
IRQ UART5 (HDQ) IO FLEX
DWI DWI0
A I2C I2C0 SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
GPIO GPIO
DDR0 DDR1 DDR2 DDR3 FMI0 FMI1 BLOCK DIAGRAM: SYSTEM
DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
HALL EFF 1 HALL EFF 2 BUTTON FLEX NOTICE OF PROPRIETARY PROPERTY:
CSA 22 IO FLEX
CSA 39 LPDDR3 LPDDR3 NAND FLASH THE INFORMATION CONTAINED HEREIN IS THE
THE POSESSOR AGREES TO THE FOLLOWING: PAGE 2 OF 155
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
CSA 16 CSA 17 CSA 18 III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 2 OF 73
IV ALL RIGHTS RESERVED
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SOC TABLE_5_HEAD
Page Notes PART#
343S00016
QTY
1
DESCRIPTION
IC,CAPRI,A1,PROD,ASE
REFERENCE DESIGNATOR(S)
U0600
CRITICAL
CRITICAL
BOM OPTION
TABLE_5_ITEM
Power aliases required by this page:

(NONE) TABLE_ALT_HEAD
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

PART NUMBER
Signal aliases required by this page:
TABLE_ALT_ITEM
(NONE) 343S00021 343S00016 U0600 IC,CAPRI,A1,PROD,SCK
BOM options provided by this page:
D D
PMU TABLE_5_HEAD

TABLE_5_ITEM
343S0675 1 IC,PMU,ARABELA,D2207A0,TOP-AC,FCBGA380 U8100 CRITICAL
SDRAM TABLE_5_HEAD

TABLE_5_ITEM
333S0803 2 IC,CAPRI,DRAM,10X10MM,FBGA261 U1600,U1700 CRITICAL
TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
333S0804 333S0803 U1600,U1700 ELPIDA DRAM

TABLE_ALT_ITEM
333S00014 333S0803 U1600,U1700 SAMSUNG DRAM
NAND
C 16GB FLASH CONFIGURATIONS
C
TABLE_5_HEAD

TABLE_5_ITEM
335S0972 1 TOSHIBA 16GB MLC 1YNM PPN1.5 U1800 CRITICAL 16GB_PROD
TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
335S1035 335S0972 16GB_PROD U1800 HYNIX 16GB MLC 1YNM PPN1.5
64GB FLASH CONFIGURATIONS TABLE_5_HEAD

TABLE_5_ITEM
335S00011 1 SANDISK 64GB TLC 1YNM PPN1.5 U1800 CRITICAL 64GB_PROD
TABLE_ALT_HEAD
MECHANICAL PARTS PART NUMBER ALTERNATE FOR

PART NUMBER
BOM OPTION REF DES COMMENTS:
TABLE_5_HEAD
TABLE_ALT_ITEM
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 335S00017 335S00011 64GB_PROD U1800 TOSHIBA 64GB TLC 1YNM PPN
TABLE_5_ITEM
806-7118 1 RADIO FENCE X190 PD_FENCE_RADIO CRITICAL MLB_B

TABLE_5_ITEM
806-00001 1 AP FENCE X190 PD_FENCE_AP CRITICAL

TABLE_5_ITEM 128GB FLASH CONFIGURATIONS
806-6353 1 GRAPE FENCE X190 PD_FENCE_GRAPE CRITICAL TABLE_5_HEAD

TABLE_5_ITEM
335S00012 1 SANDISK 128GB TLC 1YNM PPN1.5 U1800 CRITICAL 128GB_PROD

B TABLE_ALT_HEAD
B
PART NUMBER
BARCODE LABEL/EEEE CODES

TABLE_ALT_ITEM
335S00018 335S00012 128GB_PROD U1800 TOSHIBA 128GB TLC 1YNM PPN

TABLE_5_HEAD

TABLE_5_ITEM
825-00067 1 EEEE FOR 639-5813 (MLB A 16GB) EEEE_FQJ3 CRITICAL EEEE_MLB_A_16GB

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM
825-00067 1 EEEE FOR 639-4747 (MLB B 16GB) EEEE_FH54 CRITICAL EEEE_MLB_B_16GB

TABLE_5_ITEM
825-00067 1 EEEE FOR 639-5809 (MLB B 32GB) EEEE_FQHY CRITICAL EEEE_MLB_B_32GB

TABLE_5_ITEM
825-00067 1 EEEE FOR 639-5810 (MLB B 64GB) EEEE_FQHW CRITICAL EEEE_MLB_B_64GB

TABLE_5_ITEM
825-00067 1 EEEE FOR 639-5811 (MLB B 128GB) EEEE_FQHV CRITICAL EEEE_MLB_B_128GB
A CKPLUS WAIVE TABLE SYNC_MASTER=N/A SYNC_DATE=N/A A

TABLE_DASHBOARD_INFO PAGE TITLE
CKPLUS RULE EXCEPTIONS REQUIRED
BOM TABLES
SCHEMATIC DEFINED CONSTRAINTS (YES/NO) NO DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
NOTICE OF PROPRIETARY PROPERTY:
THE INFORMATION CONTAINED HEREIN IS THE
THE POSESSOR AGREES TO THE FOLLOWING:
PAGE 4 OF 155
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART SHEET 3 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
BOOT CONFIG ID R0510 MASTER: SOC

=PP1V8_SOC 1
240 2 JTAG_SOC_SEL 70 6 IN I2C0_SCL_1V8 MAKE_BASE=TRUE =I2C_SOC2PMU_SCL_1V8 OUT 62
72 62 6 5 4 OUT 5 69
1% =I2C_SOC2TRISTAR_SCL_1V8 OUT 25
TO:
1NOSTUFF 1NOSTUFF 1 1 NOSTUFF
1/32W ARABELA ADDR: 0B0111100X
R0500 R0501 R0502 R0503 MF 70 6 BI I2C0_SDA_1V8 MAKE_BASE=TRUE =I2C_SOC2PMU_SDA_1V8 BI 62 TRISTAR ADDR: 0B0011010X
01005
1.00K 1.00K 1.00K 1.00K
5%
=I2C_SOC2TRISTAR_SDA_1V8 BI 25
5% 5% 5%
1/32W 1/32W
MF MF
01005 01005 01005
2 01005 2 2 2 NOSTUFF 70 6 I2C1_SCL_1V8 MAKE_BASE=TRUE =I2C_SOC2MESA_SCL_1V8 33
MF MF IN OUT
6 OUT GPIO_BOOT_CFG3 1/32W 1/32W R0550 =I2C_SOC2SPKRAMP_SCL_1V8 OUT 24 TO:
240 MESA EEPROM (MEM) ADDR: 0B1010000X
6 GPIO_BOOT_CFG2 1 2 TP_JTAG_SOC_TRST_L 5 69 I2C1_SDA_1V8 MAKE_BASE=TRUE =I2C_SOC2MESA_SDA_1V8
D 6
OUT
OUT GPIO_BOOT_CFG1 1%
1/32W
MF
OUT 70 6 BI
=I2C_SOC2SPKRAMP_SDA_1V8
BI
BI
33
24
MESA EEPROM (ID) ADDR: 0B1011000X
SPEAKER AMP LEFT ADDR: 0B0110001X
SPEAKER AMP RIGHT ADDR: 0B0110100X D
6 OUT GPIO_BOOT_CFG0
01005
70 6 IN I2C2_SCL_1V8 MAKE_BASE=TRUE =I2C_HP_ALS_SCL_1V8 OUT 23
R0560 =I2C_MIC_ALS_SCL_1V8 OUT 23

TO:
240 ALS(MIC) ADDR: 0B0101001X
BOOT_CFG[3:0] MODE 1 2 SOC_TESTMODE 5 69
ALS(HP) ADDR: 0B1001001X
S/W READ FLOW OUT
1% 70 6 BI I2C2_SDA_1V8 MAKE_BASE=TRUE =I2C_HP_ALS_SDA_1V8 BI 23
0000 SPI 1/32W
1. SET GPIO AS INPUT MF =I2C_MIC_ALS_SDA_1V8 BI 23
0001 SPI W/TEST 01005
2. DISABLE PU AND ENABLE PD
CURRENT SETTING ---> 0010 NAND 3. READ SOC_FAST_SCAN_CLK 5
OUT
MAKE_BASE=TRUE
0011 NAND W/TEST
SOC_HOLD_RESET OUT 5
6 IN I2C3_SCL_1V8 MAKE_BASE=TRUE =I2C3_SCL_1V8 OUT 70
TO:
PROBE POINTS
SEG: CAN CONNECT TO GROUND. DO NOT FLOAT.
6 BI I2C3_SDA_1V8 MAKE_BASE=TRUE =I2C3_SDA_1V8 BI 70
PPVDD12_UH1_HSIC1 OUT 5
EFUSE SHOULD BE TIED TO GROUND PER SEG

PPVDD18_EFUSE1 OUT 11
BOARD ID
72 62 6 5 4 =PP1V8_SOC
1NOSTUFF 1 MLB_A 1 1DEV

R0504 R0505 R0506 R0507
1.00K 1.00K 1.00K 1.00K
5% 5% 5% 5%
1/32W 1/32W 1/32W 1/32W
MF MF MF 70 69 68 62 25 10 5 IN RESET_SOC_L MAKE_BASE=TRUE CFSB_SOC OUT 5
2 01005 2 01005 2 01005 2 01005
MF
GPIO_BRD_ID3 CFSB1_SOC 5
C 6
6
OUT
OUT GPIO_BRD_ID2
OUT
C
6 OUT GPIO_BRD_ID1
6 OUT GPIO_BRD_ID0
BRD_ID[3-0] S/W READ FLOW R0530

0.00 2
0000 RESERVED 1. SET GPIO AS INPUT 5 IN WDOG_SOC 1 WDOG_SOC2PMU_RESET_IN OUT 62
0001 RESERVED 2. DISABLE PU AND ENABLE PD 0%

1/32W
0010 MLB_B AP 3. READ MF
01005
RDAR://PROBLEM/15529479
0011 MLB_B DEV
0100 RESERVED
0101 RESERVED
0110 MLB_A AP
0111 MLB_A DEV
1000 UNUSED
1001 UNUSED
1010 UNUSED
1011 UNUSED
1100 RESERVED
1101 RESERVED
B BOARD REVISION B
9 OUT GPIO_BRD_REV0
9 OUT GPIO_BRD_REV1
9 OUT GPIO_BRD_REV2
9 OUT GPIO_BRD_REV3
NOSTUFF NOSTUFF NOSTUFF
1
R0523 1R0522
1.00K
1
R0521 1R0520
1.00K 5% 1.00K 1.00K
5% 5% 5%
1/32W MF 1/32W 1/32W
01005 MF MF
01005
2 2 2 01005 2
1/32W
MF
01005
BRD_REV[3-0]
0000 RESERVED
0001 RESERVED
S/W READ FLOW
0010 PROTO 1 (BRING UP)
0011 PROTO 1 (LOCAL/CHINA) 1. SET GPIO AS INPUT
0100 PROTO 2 2. ENABLE PU AND DISABLE PD
0101 PRE-EVT 3. READ
0110 EVT
CURRENT SETTING ---> 0111 DVT & PVT
1000 UNUSED
A SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
SOC: MISC & ALIASES

DRAWING NUMBER SIZE

REVISION
R
BRANCH
B.0.0
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 5 OF 155
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
4 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ON IN HIBERNATE
VDD1, VDD2, VDDIOD_DDRXCA (VDDCA), VDD12_CKE_DDR0, VDD12_CKE_DDR1
D D
=PP0V95_USB_SOC 72
1 C0630 1 C0631 1 C0632
0.01UF 0.22UF 100PF
10% 20% 5%
PPVDD12_UH1_HSIC1 6.3V 6.3V 16V
4 2 X5R 2 X5R 2 NP0-C0G
01005 01005-1 01005
72 =PP1V2_HSIC_SOC
1 C0610 1 C0611 1 C0612 =PP3V3_USB_SOC 72
1 C0615 1 C0620
0.22UF 0.22UF 0.22UF 0.01UF 100PF
20%
6.3V
20%
6.3V
20%
6.3V 10% 5%
1 C0640 1 C0645 1 C0641
2 X5R 2 X5R 2 X5R 6.3V
2 X5R
16V
2 NP0-C0G 0.01UF 0.22UF 100PF
01005-1 01005-1 01005-1 10% 20% 5%
01005 01005 2 6.3V 2 6.3V 2 16V
X5R X5R NP0-C0G
01005 01005-1 01005
VDD12_UH1_HSIC1 AM33
SEG: CAN CONNECT TO GROUND. DO NOT FLOAT.
VDD12_UH0_HSIC0 H24
VDDH_USB F23
VDD095_USB J25
VDD33_USB H25
CKPLUS_WAIVE=PWRTERM2GND
20MA
U0600
5MA
TMKP88A0-N
FCBGA
13MA
EACH SYM 4 OF 15
OMIT_TABLE
C 71 68
71 68
BI
BI
HSIC_BB_DATA
HSIC_BB_STB
D25
E25
UH1_HSIC0_DATA
UH1_HSIC0_STB
C
NC_HSIC1_DATA NO_TEST=TRUE AV38 UH2_HSIC1_DATA
72 62 6 5 4 =PP1V8_SOC ANALOGMUXOUT G35 TP_ANALOGMUXOUT
NC_HSIC1_STB NO_TEST=TRUE AU38 70
UH2_HSIC1_STB
1 1 1 USB_DP B26 USB_SOC_P BI 25 69
R0610 R0611 R0612 U37
100K 100K 100K 69 4 IN JTAG_SOC_SEL JTAG_SEL USB_DM C26 USB_SOC_N BI 25 69
5% 5% 5% NC_JTAG_SOC_TRTCK NO_TEST=TRUE R36 JTAG_TRTCK
1/32W 1/32W 1/32W
72 62 6 5 4 =PP1V8_SOC MF MF MF 69 4 TP_JTAG_SOC_TRST_L U40 JTAG_TRST*
2 01005 2 01005 2 01005 U36 R0630
1 69 TP_JTAG_SOC_TDO JTAG_TDO
R0634 T41 68.1K2
69 IN JTAG_SOC_TDI JTAG_TDI USB_VBUS F22 USB_VBUS_DETECT_R 1 USB_VBUS_DETECT IN 65
10K U38 USB_VBUS HAS 70K INPUT IMPEDANCE
5% 69 25 OUT JTAG_SOC_TMS JTAG_TMS VIN 5.0V MAX 1%
1/32W 1/32W
MF 69 25 OUT JTAG_SOC_TCK U41 JTAG_TCK USB_ID F25 NC_USB_ID NO_TEST=TRUE MF
01005
2 01005
70 69 68 62 25 10 4 IN RESET_SOC_L AR41 RESET*
USB_REXT F24 USB_REXT0
1 C0660 POWER-ON RESET 4 IN CFSB_SOC AR39 CFSB
0.01UF FAIL SAFE I/O 4 CFSB1_SOC AN26 CFSB1
IN
10% WDOG AN39 WDOG_SOC OUT 4
10V
2 X5R-CERM 4 IN SOC_HOLD_RESET AN38
0201 HOLD_RESET XI0 H41 XTAL_SOC_24M_I
TP0600 AM40
TP 1
SOC_TST_CLKOUT TST_CLKOUT XO0 H40 XTAL_SOC_24M_O
ALWAYS-ON 1.8V
TP-P55
4 OUT SOC_FAST_SCAN_CLK AR40 FAST_SCAN_CLK (REQUEST_DFU1_L) HOLD_KEY* AP27 GPIO_BTN_ONOFF_L IN 6 23 62 69
69 4 IN SOC_TESTMODE AT39 TESTMODE (REQUEST_DFU2_L) MENU_KEY* AM26 GPIO_BTN_HOME_L IN

6 33 62 R0640 1 PLACE_NEAR=U0600.F24:5MM
1
1.00M2 R0660
200
1% 1%
1/32W 1/32W
MF MF
01005 2 01005
B R06411 B
1.33K
1% CRITICAL
1/32W
MF Y0600
01005 2 1.60X1.20MM-SM
24.000MHZ-30PPM-9.5PF-60OHM
SOC_24M_O 1 3
NO_TEST=TRUE
CRITICAL
CRITICAL 2 4
1 C0650
1 C0651
12PF 12PF
5% 5%
16V 16V
2 CERM 2 CERM
01005 01005
PAGE TITLE
SOC: MAIN
DRAWING NUMBER SIZE

REVISION
R
BRANCH
B.0.0
SHEET
5 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPIOS
R_RPU AND R_RPD 45 K OHM
V_NOM 1.8V
V_MAX 1.95V
R0700
33 I2S0 LOW JITTER
22 OUT I2S_SOC2CODEC_ASP_MCK 1 2 I2S_SOC2CODEC_ASP_MCK_R H38 I2S0_MCK I2C0_SCL AP36 I2C0_SCL_1V8 OUT 4 6 70
70
PLACE_NEAR=U0600.H38:10MM 5% I2S_SOC2CODEC_ASP_BCLK AR35 I2S0_BCLK
U0600 I2C0_SDA AP34 I2C0_SDA_1V8 NC_SOC_GPIO00 NO_TEST=TRUE AF37 GPIO[0]
1/32W
70 22 OUT TMKP88A0-N BI 4 6 70
U0600
MF I2S_SOC2CODEC_ASP_LRCK AT36 I2S0_LRCK FCBGA NC_SOC_GPIO01 NO_TEST=TRUE AF36 GPIO[1]
01005
70 22 OUT TMKP88A0-N
70 22 I2S_CODEC2SOC_ASP_DOUT AN37 I2S0_DIN SYM 6 OF 15 I2C1_SCL AM41 I2C1_SCL_1V8 4 6 70 70 30 G PIO_SOC2GRAP
TS2SOC2 PE_RESET_L AJ41 GPIO[2] FCBGA
IN OUT OUT
70 22 I2S_SOC2CODEC_ASP_DOUT AN36 I2S0_DOUT OMIT_TABLE I2C1_SDA AK36 I2C1_SDA_1V8 4 6 70 62 25 MU_IRQ (USE INTERNAL PU) AG38 GPIO[3] OMIT_TABLE
SYM 5 OF 15
OUT BI IN
D 69 GPIO_DISPLAY_ID1
I2S_SOC2CODEC_XSP_BCLK AM36 I2S1_MCK I2C2_SCL T39 I2C2_SCL_1V8 4 6 70
70 30 IN GPIO_GRAPE2SOC_IRQ_L (USE INTERNAL PU)
NC_SOC_GPIO05 NO_TEST=TRUE
AH41
AF38
GPIO[4]
GPIO[5] TMR32_PWM0 AL38 OSCAR_BIDIR_TIME_SYNC_HOST_IRQ 17
D
OUT OUT BI
70 22
AT38 I2S1_BCLK I2C2_SDA R38 I2C2_SDA_1V8 4 6 70 62 GPIO_PMU2SOC_IRQ_L (USE INTERNAL PU) AG39 GPIO[6] TMR32_PWM1 AM38 NC_TMR32_PWM1 NO_TEST=TRUE
OUT BI IN
70 22 OUT C_SO
I2S DE
OC2
2CSODEC DOUT
C_XSP_LRCK AR38 I2S1_LRCK 62 6 OUT GPIO_SOC2PMU_KEEPACT AG40 GPIO[7] TMR32_PWM2 AL36 NC_TMR32_PWM2 NO_TEST=TRUE
I2C3_SCL T38
I2C3_SDA I2C3_SCL_1V8 OUT 4 6
AG41
70 22 IN I2S_SOC2CODEC_XSP_DOUT AT40 I2S1_DIN R37
NC_SOC_GPIO08 NO_TEST=TRUE GPIO[8]
I2C3_SDA_1V8 BI 4 6
AE36
70 22 OUT
AR37 I2S1_DOUT 69 IN GPIO_ALS2SOC_DEVBRD_IRQ_L GPIO[9] UART0_RXD V37 UART_DEBUG2SOC_TX IN 25 69
DWI_SOC2PMU_CLK
DWI0_CLK AN35 OUT 62 70 NC_SOC_GPIO10 NO_TEST=TRUE AD36 GPIO[10] UART0_TXD V38 UART_SOC2DEBUG_TX OUT 25 69
I2S2 LOW JITTER GPIO[11]
NC_I2S2_MCLK NO_TEST=TRUE H39 I2S2_MCK DWI1_CLK L36 NC_DWI1_CLK NO_TEST=TRUE
68 BI GPIO_BB_IPC AE38
P37
DWI_SOC2PMU_DO AF39 N41
NC_I2S2_BCLK NO_TEST=TRUE
I2S2_BCLK 28 IN GPIO_BTN_VOL_DOWN_L (USE INTERNAL PU)
GPIO[13] UART1_CTSN UART_BB2SOC_RTS_L IN 68 71
AT35 AF40
NC_I2S2_LRCK NO_TEST=TRUE M40 I2S2_LRCK DWI0_DO J39 OUT 62 70 28 IN GPIO_BTN_VOL_UP_L (USE INTERNAL PU)
GPIO[12] UART1_RTSN N39 UART_SOC2BB_RTS_L OUT 68 71
M39 AD37
NC_I2S2_DIN NO_TEST=TRUE
I2S2_DIN DWI1_DO NC_DWI1_DO NO_TEST=TRUE NC_SOC_GPIO14 NO_TEST=TRUE GPIO[14] UART1_RXD P39 UART_BB2SOC_TX IN 25 68 71
N36 AF41
NC_I2S2_DOUT NO_TEST=TRUE
I2S2_DOUT 30 OUT GPIO_SOC2GRAPE_EXT_SW_ON
GPIO_BRD_ID3 GPIO[15] UART1_TXD P40 UART_SOC2BB_TX OUT 25 68 71
R0701 4 IN GPIO_SOC2BB_COREDUMP AD39 GPIO[16] BOARD_ID<3>
33 AJ40 AE39
24 OUT I2S_SOC2SPKRAMP_MCK 1 2 I2S_SOC2SPKRAMP_MCK_R I2S3_MCK 71 68 OUT GPIO_BOOT_CFG0 GPIO[17] UART2_CTSN R41 UART_WLAN2SOC_RTS_L IN 68 70
70 PLACE_NEAR=U0600.AJ40:10MM
5% 70 24 I2S_SOC2SPKRAMP_BCLK AH36 I2S3_BCLK 4 NO_TEST=TRUE NC_SOC_GPIO19 AD38 GPIO[18] BOOT_CFG<0> UART2_RTSN T36 UART_SOC2WLAN_RTS_L 57 68 70
1/32W OUT IN OUT
MF
70 24 I2S_SOC2SPKRAMP_LRCK AK40 I2S3_LRCK GPIO_SOC2BB_WAKE_MODEM AE41 GPIO[19] UART2_RXD R39 UART_WLAN2SOC_TX 68 70
01005 OUT IN
70 24 IN I2S_SPKRAMP2SOC_DOUT AJ38 I2S3_DIN 71 68 OUT GPIO_SOC2SPKRAMP_KEEPALIVE AD40 GPIO[20] UART2_TXD R40 UART_SOC2WLAN_TX OUT 57 68 70
70 24 OUT I2S_SOC2SPKRAMP_DOUT AK41 I2S3_DOUT 24 OUT

GPIO_BB2SOC_GPS_SYNC AC37 GPIO[21]
71 68 IN
GPIO_HP_ALS2SOC_IRQ_L AC38 GPIO[22] UART3_CTSN AP35 UART_BT2SOC_RTS_L IN 68 70
69 OUT GPIO_DISPLAY_ID0 P38 I2S4_MCK 23 IN

GPIO_SOC2BB_RADIO_ON_L(USE INTERNAL PU) AB36 GPIO[23] UART3_RTSN AT33 UART_SOC2BT_RTS_L OUT 57 68 70
70 68 57 OUT I2S_SOC2BT_BCLK P34 I2S4_BCLK 71 69 68 6 OUT

AC36 GPIO[24] UART3_RXD AR34 UART_BT2SOC_TX IN 68 70
4
70 68 57 OUT I2S_SOC2BT_LRCK P36 I2S4_LRCK SEP’S I2C INTERNAL PULL UPS ARE TOO WEAK (28-55K)
IN GPIO_BOOT_CFG1 AD41 GPIO[25] BOOT_CFG<1> UART3_TXD AT34 UART_SOC2BT_TX OUT 57 68 70
M41 W36 AC40
70 68 IN I2S_BT2SOC_DOUT I2S4_DIN SEP_I2C_SCL SEP_I2C0_SCL_1V8 6 69 67 6 IN GPIO_FORCE_DFU GPIO[26] FORCE_DFU
N38 W39 AC39 AG36
70 68 57 OUT I2S_SOC2BT_DOUT I2S4_DOUT SEP_I2C_SDA SEP_I2C0_SDA_1V8 6 70 OUT TP_GPIO_DFU_STATUS GPIO[27] DFU_STATUS UART4_CTSN UART_ROTTERDAM2SOC_RTS_L IN 34
SEP_SPI_SCLK V40 NC_SEP_SPI_SCLK NO_TEST=TRUE

4 GPIO_BOOT_CFG2 AC41 GPIO[28] BOOT_CFG<2> UART4_RTSN AG37 UART_SOC2ROTTERDAM_RTS_L 34
IN OUT
SEP_SPI_SSIN V41 NC_SEP_SPI_SSIN NO_TEST=TRUE NC_BOARD_ID4 NO_TEST=TRUE AB38
GPIO[29] BOARD_ID<4> UART4_RXD AH38 UART_ROTTERDAM2SOC_TX 34
V36 IN
SEP_SPI_MISO NC_SEP_SPI_MISO NO_TEST=TRUE GPIO_MIC_ALS2SOC_IRQ_L(USE INTERNAL PU) AB41 GPIO[30] UART4_TXD AH39 UART_SOC2ROTTERDAM_TX
C 4 IN GPIO_BRD_ID2 AL41 SPI0_MISO BOARD_ID<2> SEP_SPI_MOSI
W38
NC_SEP_SPI_MOSI NO_TEST=TRUE
23
4
IN
IN GPIO_BOOT_CFG3 AB39 GPIO[31] BOOT_CFG<3>
AN34
OUT 34
C
4 IN GPIO_BRD_ID1 AJ39 SPI0_MOSI BOARD_ID<1> SEP_GPIO0 W41 NC_SEP_GPIO0 NO_TEST=TRUE
62 17 IN GPIO_OSCAR2PMU_HOST_WAKE AA36 GPIO[32] UART5_RTXD UART_BATT_HDQ OUT 62 66
NO_TEST=TRUE
4 IN GPIO_BRD_ID0 AM39 SPI0_SCLK BOARD_ID<0> 69 68 IN HSIC_BB2SOC_DEVICE_RDY AA38 GPIO[33]
ISP_UART0_RXD AJ36 NC_ISP_UART0_RXD AA39
NC_SPI0_SSIN NO_TEST=TRUE AK39 SPI0_SSIN AJ37 69 68 OUT HSIC_SOC2BB_HOST_RDY GPIO[34]
NO_TEST=TRUE
69 68 IN GPIO_BB2SOC_RESET_DET_L AA37 GPIO[35]
ISP_UART0_TXD NC_ISP_UART0_TXD (USE INTERNAL PU) Y36
22 IN SPI_CODEC_MISO L40 SPI1_MISO 70 22 IN GPIO_CODEC2SOC_IRQ_L GPIO[36]
R0702 22 OUT SPI_CODEC_MOSI N34 SPI1_MOSI OUT GPIO_SOC2BB_RESET_L AA40 GPIO[37] UART6_RXD V39 UART_ACC2SOC_TX IN 25 70
33
22 OUT SPI_CODEC_SCLK 1 2 22 SPI_CODEC_SCLK_R L41 SPI1_SCLK 69 68 UART6_TXD U39 UART_SOC2ACC_TX
N C_UART7_T OUT 25 70
PLACE_NEAR=U0600.L41:10MM
5% OUT SPI_CODEC_CS_L M38 SPI1_SSIN (OPENDRAIN) SOCHOT0 AN41 SOCHOT0_L IN 6 62 69 X
MF (OPENDRAIN) SOCHOT1 AK37 SOCHOT1_L OUT 6 62 UART7_RXD AK38 R NO_TEST=TRUE
01005
1/32W
33 IN SPI_MESA_MISO Y37 SPI2_MISO UART7_TXD AL39 D NO_TEST=TRUE
R0703 AP41 DISPLAY_SYNC OUT 30 70

33 OUT SPI_MESA_MOSI Y38 SPI2_MOSI DISP_VSYNC
UART8_RXD Y39 UART_OSCAR2SOC_TX IN 17 70
SPI_MESA_SCLK 33 SPI_MESA_SCLK_R UART_SOC2OSCAR_TX

33 OUT
1 2 33 AA41 SPI2_SCLK UART8_TXD Y40 OUT 17 70
PLACE_NEAR=U0600.AA41:10MM 5% IN GPIO_MESA2SOC_IRQ Y41 SPI2_SSIN
1/32W
MF
01005 70 30
70 30 IN SPI_GRAPE_MISO AT37 SPI3_MISO
R0704 OUT SPI_GRAPE_MOSI
SPI_GRAPE_SCLK_R AM37 SPI3_MOSI
33 AP39
70 30 OUT SPI_GRAPE_SCLK 1 2 SPI3_SCLK
PLACE_NEAR=U0600.AP39:10MM
5% SPI_GRAPE_CS_L AP38 SPI3_SSIN
1/32W OUT
MF
01005
72 62 6 5 4 =PP1V8_SOC
I2C PULL-UPS
BUTTON PULLUPS
1
B 72 62 11 =PP1V8_ALWAYS R0750 1R0751 1
R0752 1
R0753 1R0754 1
R0755 1
R0756 1
R0757 1
R0740 1
R0741 B
2.2K 2.2K 2.2K 2.2K 2.2K 2.2K 2.2K 2.2K 2.2K 2.2K
=PP1V8_S2R_MISC 6 9 66 67 72 5% 5% 5% 5% 5% 5% 5% 5% 5% 5%
72 67 66 9 6 =PP1V8_S2R_MISC 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W
MF MF
01005 MF MF MF MF
01005 MF MF MF MF
=PP1V8_SOC 4 5 6 62 72
2 01005 2 2 01005 2 01005 2 01005 2 2 01005 2 01005 2 01005 2 01005
1
R0720 1
R0721 1 1 70 6 4 I2C0_SDA_1V8
100K 100K R0760 R0761 70 6 4 I2C0_SCL_1V8
5% 5% 100K 100K
1/32W 1/32W 5% 5% 70 6 4 I2C1_SDA_1V8
MF MF 1/32W 1/32W
2 01005 2 01005 MF
01005 MF 70 6 4 I2C1_SCL_1V8
2 2 01005
70 6 4 I2C2_SDA_1V8
70 6 4
I2C2_SCL_1V8
GPIO_BTN_HOME_L 62 6 SOCHOT1_L
62 33 5 I2C3_SDA_1V8
69 62 23 5 GPIO_BTN_ONOFF_L 69 62 6 SOCHOT0_L
SEP EEPROM
UNPROGRAMMED P/N: 335S0894
6 4
6 4 I2C3_SCL_1V8
SEP_I2C0_SDA_1V8
6 SEP_I2C0_SCL_1V8
6
=PP1V8_EEPROM 72
1 C0790
GPIO_SOC2PMU_KEEPACT 6 62
0.22UF
A1
20%
GPIO_FORCE_DFU 6 67 69
2 6.3V
GPIO_SOC2BB_RADIO_ON_L X5R
6 68 69 71 01005-1
VCC
CRITICAL
NOSTUFF U0790
1 1 1 CAT24C08C4A
R0730 R0731 R0733
A 100K
5%
100K
5%
100K
5% 6 SEP_I2C0_SCL_1V8 B1 SCL
WLCSP
SDA B2 SEP_I2C0_SDA_1V8 6 SYNC_MASTER=N/A SYNC_DATE=N/A A
1/32W 1/20W 1/32W PAGE TITLE
MF MF MF
2 01005 2 201 2 01005 SOC: I/OS
DRAWING NUMBER SIZE
VSS
A2
REVISION
R
BRANCH B.0.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
72 7 =PP1V8_NAND_SOC
R0800 1 1
R0801
100K 100K
5% 5%
1/32W 1/32W
MF
01005 MF
2 2 01005
U0600
TMKP88A0-N
FCBGA
SYM 7 OF 15
OMIT_TABLE
70 69 16 OUT ANC0_CE0_L D40 PPN0_CEN[0] PPN1_CEN[0] G36 ANC1_CE0_L OUT 16 69 70
C NC_ANC0_CE1_L NO_TEST=TRUE D35 PPN0_CEN[1] PPN1_CEN[1] G41 NC_ANC1_CE1_L NO_TEST=TRUE

C
70 16 BI ANC0_AD<0> A37 PPN0_IO[0] PPN1_IO[0] G38 ANC1_AD<0> BI 16 70
70 16 BI ANC0_AD<1> B38 PPN0_IO[1] PPN1_IO[1] G39 ANC1_AD<1> BI 16
70 16 ANC0_AD<2> C38 PPN0_IO[2] PPN1_IO[2] E37 ANC1_AD<2> 16

BI BI
70 16 BI ANC0_AD<3> B37 PPN0_IO[3] PPN1_IO[3] E36 ANC1_AD<3> BI 16
70 16 ANC0_AD<4> C37 PPN0_IO[4] PPN1_IO[4] F37 ANC1_AD<4> 16

BI BI
70 16 ANC0_AD<5> C39 PPN0_IO[5] PPN1_IO[5] E40 ANC1_AD<5> 16
BI BI
70 16 BI ANC0_AD<6> D39 PPN0_IO[6] PPN1_IO[6] E41 ANC1_AD<6> BI 16
70 16 BI ANC0_AD<7> D36 PPN0_IO[7] PPN1_IO[7] F36 ANC1_AD<7> BI 16
70 16 ANC0_ALE A35 PPN0_ALE PPN1_ALE G40 ANC1_ALE 16 70

OUT OUT
70 16 OUT ANC0_CLE B35 PPN0_CLE PPN1_CLE F41 ANC1_CLE OUT 16 70
70 16 ANC0_WE_L A36 PPN0_WEN PPN1_WEN G37 ANC1_WE_L 16 70

OUT OUT
70 16 OUT A RE_L C35 PPN0_REN PPN1_REN F39 ANC1_RE_L OUT 16 70
70 16 C36 E38
BI N PPN0_DQS PPN1_DQS ANC1_DQS BI 16 70
D38 E39
ANC0_ZQ
C PPN0_ZQ PPN1_ZQ ANC1_ZQ
0
PLACE_NEAR=U0600.D38:5MM 1 PLACE_NEAR=U0600.E39:5MM
R08401 _ R0841
240 DQS 240
1% 1%
1/32W 1/32W
MF E35 PPN0_VREF PPN1_VREF F35 MF
01005 2 2 01005
240 OHM IS CORRECT PER CAPRI DATASHEET
240 OHM IS CORRECT PER CAPRI DATASHEET
B =PP1V8_NAND_SOC 7 72
B
1 1
R0830 C0830
51.1K 0.01UF
1% 10%
1/32W
MF 2 6.3V
01005
2 01005 X5R
VOLTAGE=0.9V
70 PPVREF_ANC_SOC
1 1 C0831
R0831
51.1K 0.01UF
1% 10%
1/32W 2 6.3V
X5R
MF 01005
2 01005
PAGE TITLE
SOC: NAND
DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
72 =PP1V0_MIPI_SOC =PP1V8_MIPI_SOC 72
1 C0906 1 C0910 1 C0915

0.22UF 100PF 1.0UF
20% 5% 20%
2 6.3V
X5R 2 16V
NP0-C0G 2 6.3V
X5R
01005-1 01005 0201-1
VDD10_MIPIC AM31
VDD10_MIPIC AN30
VDD10_MIPIC AN32
VDD18_MIPIC AN28
VDD18_MIPIC AM29
26MA 13MA
U0600
TMKP88A0-N
FCBGA
SYM 3 OF 15
OMIT_TABLE
70 21 IN MIPI_CAM_REAR_DATA_P<0> AV33 MIPI0C_DPDATA0 ISP0_SCL AT29 ISP_CAM_REAR_SCL OUT 21
70 21 IN MIPI_CAM_REAR_DATA_N<0> AW33 MIPI0C_DNDATA0 ISP0_SDA AT31 ISP_CAM_REAR_SDA BI 21
AV32
70 21 IN MIPI_CAM_REAR_DATA_P<1> AW32 MIPI0C_DPDATA1
70 21 IN MIPI_CAM_REAR_DATA_N<1> MIPI0C_DNDATA1
AV30 ISP1_SCL AT32 ISP_CAM_FRONT_SCL OUT 21
C 21
21
IN
IN
MIPI_CAM_REAR_DATA_P<2>
MIPI_CAM_REAR_DATA_N<2>
AW30 MIPI0C_DPDATA2
MIPI0C_DNDATA2
ISP1_SDA AR28 ISP_CAM_FRONT_SDA BI 21
C
AV29 SENSOR0_CLK AR31 ISP_CAM_REAR_CLK_R
SHUTDOWN_L R0910 1 33 2 ISP_CAM_REAR_CLK OUT 21
AW29 1/32W 5% 01005 MF
21 IN MIPI_CAM_REAR_DATA_P<3> MIPI0C_DPDATA3 SENSOR0_RST AT30 OUT 21 PLACE_NEAR=U0600.AR31:5MM
21 IN MIPI_CAM_REAR_DATA_N<3> AV31 MIPI0C_DNDATA3

SENSOR1_CLK AP32 ISP_CAM_FRONT_CLK_R
SHUTDOWN_L R0911 15% 33 2 ISP_CAM_FRONT_CLK OUT 21
1/32W 01005 MF
70 21 IN MIPI_CAM_REAR_CLK_P MIPI0C_DPCLK SENSOR1_RST AR30 OUT 21
70 21 MIPI_CAM_REAR_CLK_N AW31 MIPI0C_DNCLK

IN
MIPI0C_REXT AP30 MIPI0C_REXT

SENSOR0_ISTRB AR32 GPIO_SPKRAMP2SOC_RIGHT_IRQ_L (USE INTERNAL PU)
IN 24
SEG: 4.02K IS CORRECT VALUE
1 SENSOR0_XSHUTDOWN AR29 GPIO_SPKRAMP2SOC_LEFT_IRQ_L (USE INTERNAL PU)
IN 24
R0920
4.02K SENSOR1_ISTRB AP33 GPIO_SOC2ROTTERDAM_DWLD_REQ (USE INTERNAL PD) OUT 34
1%
1/32W SENSOR1_XSHUTDOWN AN33 GPIO_SOC2ROTTERDAM_EN (USE INTERNAL PU) OUT 34
01005
MF
2
MIPI1C_REXT AP31 MIPI1C_REXT

MIPI1C_DPDATA0 AV37 MIPI_CAM_FRONT_DATA_P<0> IN 21 70
MIPI1C_DNDATA0 AW37 MIPI_CAM_FRONT_DATA_N<0> IN 21 70 SEG: 4.02K IS CORRECT VALUE

1
AV35
MIPI_CAM_FRONT_DATA_P<1>
R0921
MIPI1C_DPDATA1 AW35 IN 21 4.02K
MIPI1C_DNDATA1 MIPI_CAM_FRONT_DATA_N<1> IN 21
1%
1/32W
AV36 MF
2 01005
MIPI1C_DPCLK M P IN 21 70
MIPI1C_DNCLK AW36 I IN 21 70
P
I
B _ B
C
A
M
_
F
R
O
N
T
_
C
L
K
_
N
PAGE TITLE
SOC: MIPI, ISP

DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
72 =PP0V95_PCIE_SOC =PP1V8_PCIE_SOC 72
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
C1096 C1097 C1092 C1093 C1094 C1095 1 C1041 1 C1046 1 C1040 1 C1049 1 C1050
1UF 1UF 1UF 1UF 1UF 1UF 0.22UF 0.01UF 56PF 56PF 0.22UF
CERM 4V CERM 4V CERM 4V CERM 4V CERM 4V CERM 4V 20% 10% 5% 5% 20%
0402 20% 0402 20% 0402 20% 0402 20% 0402 20% 0402 20% 6.3V
2 X5R 6.3V
2 X5R 6.3V
2 NP0-C0G 6.3V
2 NP0-C0G 6.3V
2 X5R
1 3 1 3 1 3 1 3 1 3 1 3 01005-1 01005 01005 01005 01005-1
2 4 2 4 2 4 2 4 2 4 2 4
R1090
VOLTAGE=1.2V
0.00 2
D 72 =PP1V0_LPDP_SOC
PP1V2_PCIE_PLL_SOC_FILT 1
0%
=PP1V2_PLL_SOC 11 72 D
1 C1090 1 C1091 1/32W
56PF 0.22UF MF
1 01005
C1055 1 C1045 5% 20%
1.0UF 56PF 6.3V
2 NP0-C0G 2 6.3V
X5R
20% 5% 01005 01005-1
2 6.3V
X5R
6.3V
2 NP0-C0G
0201-1 01005
H22
H23
J21
J23
G26
J26
H29
K30
VDD095_VP01_PCIE J27
VDD095_VP23_PCIE K29
8MA VDDA10_REFCLK_PCIE L28
VDD18_VPH01_PCIE K27
VDD18_VPH23_PCIE J28
VDDA12_PLL_PCIE L27
LPDP_VDDA10
LPDP_VDDA10
LPDP_VDDA10
LPDP_VDDA10
VDD095_VPTX0_PCIE
VDD095_VPTX1_PCIE
VDD095_VPTX2_PCIE
VDD095_VPTX3_PCIE
ULPI_DATA[0] L35 SWD_OSCAR_CLK_1V8
32 EDP_AUX_P D23 LPDP_AUX_P OUT 17 70
BI L37 SWD_OSCAR_IO_1V8
E23 ULPI_DATA[1] BI 17 70
32 BI EDP_AUX_N LPDP_AUX_N K38
ULPI_DATA[2] GPIO_BRD_REV2 IN 4
70 32 EDP_DATA_P<0> C22 LPDP_TX0P ULPI_DATA[3] J34 GPIO_SOC2DEVBRD_S3E_RESET2_L 69

OUT EDP_DATA_N<0> OUT
70 32
B22 LPDP_TX0N ULPI_DATA[4] M37 PIO_SOC2WLAN_WAKE
G PIO 68 70
OUT IN
8.5MA
24MA 21MA 45MA 26MA ULPI_DATA[5] M36 PIO_SOC2BT_WAKE
_
70 32 EDP_DATA_P<1> B23 LPDP_TX1P EACH EACH EACH IN 57 68 70
OUT OMIT_TABLE L38 BRD_REV3
A23 ULPI_DATA[6] IN 4
70 32 OUT EDP_DATA_N<1> LPDP_TX1N U0600 L34
ULPI_DATA[7] SOC2AJ_HS3_SHUNT_EN OUT 23
EDP_DATA_P<2> C24 TMKP88A0-N

70 32 OUT LPDP_TX2P FCBGA K34
GPIO_SOC2AJ_HS4_SHUNT_EN
EDP_DATA_N<2> B24 M34 OUT 23
70 32 OUT LPDP_TX2N SYM 8 OF 15
ULPI_CLK K41 GPIO_BRD_REV1 IN 4
70 32 EDP_DATA_P<3> B25 LPDP_TX3P ULPI_NXT L39 GPIO_BRD_REV0 4

OUT ULPI_DIR IN
EDP_DATA_N<3> A25 GPIO_SOC2DEVBRD_S3E_WAKE
PLACE_NEAR=U0600.F21:10MM
70 32 OUT LPDP_TX3N ULPI_STP OUT 69
R10231 1 C1060 LPDP_CAL_DRV_OUT F21 LPDP_CAL_DRV_OUT TOUCH CLK +/-100PPM -->

CLK32K_OUT K39 CLK_SOC2GRAPE_32K OUT 30 69 70
240 100PF G23 (+/-30PPM FREQUENCY ACCURACY, +/-70PPM FOR JITTER)
RDAR://PROBLEM//16438437 1% 5% LPDP_CAL_VSS_EXT LPDP_CAL_VSS_EXT
1/32W 6.3V
2 CERM CPU_SLEEP_STATUS AN40 NC_CPU_SLEEP_STATUS NO_TEST=TRUE
MF PCIE_RX0_P
C 01005 2 01005 NC_PCIE_RX0_P
NC_PCIE_RX0_N
NO_TEST=TRUE
NO_TEST=TRUE
E29
F29 PCIE_RX0_M EDP_HPD P41 EDP_HPD IN 32 C
B29 (12MHZ TO EXT NVME CTL) NAND_SYS_CLK J35 CLK_SOC2DEVBRD_PCIE_24MHZ OUT 69
NC_PCIE_TX0_P NO_TEST=TRUE
PCIE_TX0_P
NC_PCIE_TX0_N NO_TEST=TRUE C29
PCIE_TX0_M
PERST# FOR LANE 0 IS GPIO[39]
NC_PCIE_CLK0_P NO_TEST=TRUE A32 PCIE_REF_CLK0_P
70 68 IN PCIE_WLAN2SOC_TX_P B32
NC_PCIE_CLK0_N NO_TEST=TRUE
PCIE_REF_CLK0_M
70 68 IN PCIE_WLAN2SOC_TX_N NC_PCIE_CLKREQ0 NO_TEST=TRUE J41 PCIE_CLKREQ0*
PLACE_NEAR=U0600.A28:11MM
(PCIE_WLAN2SOC_TX_P) D28 PCIE_RX1_P
70 68 57 OUT PCIE_SOC2WLAN_TX_P 0.1UF1 2 C1022 (PCIE_WLAN2SOC_TX_N) E28 PCIE_RX1_M
20% 4V 01005 X5R
0.1UF1 C1023 PCIE_SOC2WLAN_TX_C_P A28 PCIE_TX1_P
70 68 57 OUT PCIE_SOC2WLAN_TX_N 2 70
20% 4V 01005 X5R 70 PCIE_SOC2WLAN_TX_C_N B28 PCIE_TX1_M
PLACE_NEAR=U0600.B28:11MM
WIFI
PCIE_SOC2WLAN_CLK_C_P B33 PCIE_REF_CLK1_P PERST# FOR LANE 1 IS GPIO[43]
PLACE_NEAR=U0600.B33:8MM C33
C1024 PCIE_SOC2WLAN_CLK_C_N PCIE_REF_CLK1_M
70 68 57 OUT PCIE_SOC2WLAN_CLK_P 0.1UF1 2
72 67 66 6 =PP1V8_S2R_MISC 20% 4V 01005 X5R (PCIE_WLAN2SOC_CLKREQ_L) J40 PCIE_CLKREQ1* (1.8V)
1 70 68 57 OUT PCIE_SOC2WLAN_CLK_N 0.1UF1 2 C1025
R1020 20% 4V 01005 X5R NC_PCIE_RX2_P NO_TEST=TRUE D30 PCIE_RX2_P
1.00K PLACE_NEAR=U0600.C33:8MM
NO_TEST=TRUE E30
5% NC_PCIE_RX2_N PCIE_RX2_M
1/32W
MF A30
2 01005
NC_PCIE_TX2_P NO_TEST=TRUE
PCIE_TX2_P
70 68 PCIE_WLAN2SOC_CLKREQ_L NC_PCIE_TX2_N NO_TEST=TRUE B30 PCIE_TX2_M
IN
NC_PCIE_CLK2_P NO_TEST=TRUE D32 PCIE_REF_CLK2_P

NC_PCIE_CLK2_N NO_TEST=TRUE E32 PCIE_REF_CLK2_M
69 PCIE_DEVBRD2SOC_CLKREQ_L J38 PCIE_CLKREQ2*

IN
B NC_PCIE_RX3_P NO_TEST=TRUE E31 PCIE_RX3_P B
NC_PCIE_RX3_N NO_TEST=TRUE F31
PCIE_RX3_M
NC_PCIE_TX3_P NO_TEST=TRUE B31 PCIE_TX3_P

NC_PCIE_TX3_N NO_TEST=TRUE C31 PCIE_TX3_M
NC_PCIE_CLK3_P NO_TEST=TRUE E33 PCIE_REF_CLK3_P

PCIE_REF_CLK3_M
NC_PCIE_CLK3_N NO_TEST=TRUE F33
NC_PCIE_CLKREQ3 NO_TEST=TRUE K36 PCIE_CLKREQ3*
NC_PCIE_REF_CK01_P NO_TEST=TRUE G27 PCIE_REF_PAD_CLK01_P

NC_PCIE_REF_CK01_N NO_TEST=TRUE G28
PCIE_REF_PAD_CLK01_M
INTERNAL REF IS USED
SEG: OK TO FLOAT REF_PAD_CLK NC_PCIE_REF_CK23_P NO_TEST=TRUE G30 PCIE_REF_PAD_CLK23_P
G29 PCIE_PERST0* J36 NC_PCIE_PERST0 NO_TEST=TRUE
NC_PCIE_REF_CK23_N NO_TEST=TRUE
PCIE_REF_PAD_CLK23_M J37
J31 PCIE_PERST1* PCIE_SOC2WLAN_RESET_L OUT 68 70
PCIE_RESREF01 H36
H31 PCIE_RESREF01 PCIE_PERST2* PCIE_SOC2DEVBRD_RESET_L OUT 69
1
NC_PCIE_RESREF23 H37 R1022
NO_TEST=TRUE
PCIE_RESREF23 PCIE_PERST3* NC_PCIE_PERST3 NO_TEST=TRUE
100K
5%
SEG: UNUSED RESREFS CAN FLOAT 1/32W
MF
CORRECT VALUE FOR CAPRI CAPRI DATASHEET 0. 2 01005
PLACE_NEAR=U0600.J31:10MM
FOR UNUSED PCIE LINKS, THE PCIE_TX_P/M PINS MAY BE LEFT FLOATING
R10211 BUT THE RESPECTIVE VPTX SUPPLY SHALL BE CONNECTED
200
1%
1/32W
MF
01005 2
PAGE TITLE
SOC: EDP, PCIE

DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
THE POSESSOR AGREES TO THE FOLLOWING: PAGE10 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
DDR0_CA<0> A15 DDR0_CA[0] DDR1_CA[0] E21 DDR1_CA<0> AW22 AW15

70 14 OUT
U0600 OUT 14 70
70 15 OUT DDR2_CA<0> DDR2_CA[0] DDR3_CA[0] DDR3_CA<0> OUT 15 70
70 14 OUT DDR0_CA<1> B15 DDR0_CA[1] TMKP88A0-N DDR1_CA[1] D20 DDR1_CA<1> OUT 14 70 DDR2_CA<1> AV22 DDR2_CA[1]
U0600 DDR3_CA[1] AW16 DDR3_CA<1>
C15 E20
70 15 OUT TMKP88A0-N OUT 15 70
70 14 OUT DDR0_CA<2> DDR0_CA[2] FCBGA DDR1_CA[2] DDR1_CA<2> OUT 14 70
70 15 DDR2_CA<2> AU22 DDR2_CA[2] FCBGA DDR3_CA[2] AV16 DDR3_CA<2> 15 70
OUT OUT
DDR0_CA<3> D16 DDR0_CA[3] SYM 1 OF 15 DDR1_CA[3] B20 DDR1_CA<3>
70 14 OUT OUT 14 70
14 70
70 15 OUT DDR2_CA<3> AT23 DDR2_CA[3] SYM 2 OF 15 DDR3_CA[3] AU16 DDR3_CA<3> OUT 15 70
DDR0_CA<4> A14 DDR0_CA[4] OMIT_TABLE DDR1_CA[4] A20 DDR1_CA<4> OMIT_TABLE
70 14 OUT OUT 70 15 OUT DDR2_CA<4> AW23 DDR2_CA[4] DDR3_CA[4] AW17 DDR3_CA<4> OUT 15 70
DDR0_CA<5> A11 DDR0_CA[5] DDR1_CA[5] A17 DDR1_CA<5>
70 14 OUT OUT 14 70
70 15 OUT DDR2_CA<5> AW26 DDR2_CA[5] DDR3_CA[5] AW20 DDR3_CA<5> OUT 15 70
DDR0_CA<6> C11 DDR0_CA[6] DDR1_CA[6] C17 DDR1_CA<6>
70 14 OUT OUT 14 70
70 15 OUT DDR2_CA<6> AU26 DDR2_CA[6] DDR3_CA[6] AU20 DDR3_CA<6> OUT 15 70
DDR0_CA<7> D12 DDR0_CA[7] D17 DDR1_CA<7>
70 14 OUT DDR1_CA[7] OUT 14 70
70 15 DDR2_CA<7> AT27 DDR2_CA[7] DDR3_CA[7] AT21 DDR3_CA<7> 15 70 72 11 =PP1V2_VDDIOD_SOC
A10 A16 OUT OUT
70 14 OUT DDR0_CA<8> DDR0_CA[8] DDR1_CA[8] DDR1_CA<8> OUT 14 70
70 15 DDR2_CA<8> AW27 DDR2_CA[8] DDR3_CA[8] AW21 DDR3_CA<8> 15 70
B10 B16 14 70 OUT OUT
DDR0_CA<9> DDR1_CA<9> 1 1
D
70 14 OUT
B12
DDR0_CA[9] DDR1_CA[9]
B18
OUT 70 15 OUT DDR2_CA<9> AV27 DDR2_CA[9] DDR3_CA[9] AV21 DDR3_CA<9> OUT 15 70
1 C1194
0.1UF
R1194
4.7K
1%
1 C1196
0.1UF
R1196
4.7K
1%
D
DDR0_CK_P DDR0_CK[0] DDR1_CK[0] DDR1_CK_P AV25 20%
70 14 OUT OUT 14 70
70 15 OUT DDR2_CK_P DDR2_CK[0] DDR3_CK[0] AV19 DDR3_CK_P OUT 15 70
20%
6.3V
1/32W
MF 6.3V
2 X5R-CERM
1/32W
MF
DDR0_CK_N A12 DDR0_CKB[0] DDR1_CKB[0] A18 DDR1_CK_N 2 X5R-CERM 01005
70 14 OUT D13 D18 OUT 14 70
70 15 OUT DDR2_CK_N AW25 DDR2_CKB[0] DDR3_CKB[0] AW19 DDR3_CK_N OUT 15 70
01005 2 01005 2 01005
NC_DDR0_CK<1> NO_TEST=TRUE DDR0_CK[1] DDR1_CK[1] NC_DDR1_CK<1> NO_TEST=TRUE
NC_DDR2_CK<1> NO_TEST=TRUE AU25 DDR2_CK[1] DDR3_CK[1]
AU19 NC_DDR3_CK<1> NO_TEST=TRUE
PPVREF_DDR0_DQ_SOC 10 PPVREF_DDR1_DQ_SOC 10
NC_DDR0_CKB<1> NO_TEST=TRUE C12 DDR0_CKB[1] DDR1_CKB[1] C18 NC_DDR1_CKB<1> NO_TEST=TRUE
NC_DDR2_CKB<1> NO_TEST=TRUE AT26 DDR2_CKB[1] DDR3_CKB[1] AT20 NC_DDR3_CKB<1> NO_TEST=TRUE VOLTAGE=0.6V
VOLTAGE=0.6V
70 14 OUT DDR0_CKE<0> B14 DDR0_CKE[0] DDR1_CKE[0] D19 DDR1_CKE<0> OUT 14 70

70 15 DDR2_CKE<0> AV23 DDR2_CKE[0] DDR3_CKE[0] AV17 DDR3_CKE<0> 15 70
NO_TEST=TRUE OUT OUT 1 1
E13 DDR0_CKE[1] DDR1_CKE[1] E18 NC_DDR1_CKE<1> NO_TEST=TRUE NO_TEST=TRUE
AR24 DDR2_CKE[1] DDR3_CKE[1] AR20
NO_TEST=TRUE
1 C1195 R1195 1 C1197 R1197
NC_DDR0_CKE<1>
RESET_SOC_L D14 DDR0_CKEIN DDR1_CKEIN C19 RESET_SOC_L 10 25 62 68 69 70 NC_DDR2_CKE<1> NC_DDR3_CKE<1> 4.7K 4.7K
70 69 68 62 25 10 5 4 IN IN 4
5 69 68 62 25 10 5 4 IN RESET_SOC_L AT25 DDR2_CKEIN DDR3_CKEIN AT19 RESET_SOC_L IN 4 5 10 25 62 68 69 70
0.1UF 0.1UF
70 20% 20%
6.3V 6.3V
2 X5R-CERM 01005 2 X5R-CERM 01005
DDR0_CSN<0> D15 DDR0_CSN[0] DDR1_CSN[0] F20 DDR1_CSN<0> 01005 01005
70 14 OUT OUT 14 70
70 15 OUT DDR2_CSN<0> AT24 DDR2_CSN[0] DDR3_CSN[0] AT18 DDR3_CSN<0> OUT 15 70
2 MF 2 MF
E14 DDR0_CSN[1] DDR1_CSN[1] E19 NC_DDR1_CSN<1> NO_TEST=TRUE 1/32W 1/32W
NO_TEST=TRUE
NO_TEST=TRUE AR23 DDR2_CSN[1] DDR3_CSN[1] AR19 NO_TEST=TRUE
1% 1%
NC_DDR0_CSN<1> NC_DDR2_CSN<1> NC_DDR3_CSN<1>
DDR0_DM<0> E6 DDR0_DM[0] DDR1_DM[0] U2 DDR1_DM<0>
70 14 OUT OUT 14 70
70 15 OUT DDR2_DM<0> AL2 DDR2_DM[0] DDR3_DM[0] AR11 DDR3_DM<0> OUT 15 70
DDR0_DM<1> E5 DDR0_DM[1] DDR1_DM[1] U5 DDR1_DM<1> DDR3_DM[1] AV10
70 14 OUT OUT 14 70
70 15 OUT DDR2_DM<1> AJ5 DDR2_DM[1] DDR3_DM<1> OUT 15 70
DDR0_DM<2> B5 DDR0_DM[2] DDR1_DM[2] W5 DDR1_DM<2> 1 1
70 14 OUT OUT 14 70 70 15 OUT DDR2_DM<2> AL5 DDR2_DM[2] DDR3_DM[2] AV8 DDR3_DM<2> OUT 15 70 1 C1184 R1184 1 C1186 R1186
DDR0_DM<3> H5 DDR0_DM[3] DDR1_DM[3] R2 DDR1_DM<3> 14 70 4.7K 4.7K
70 14 OUT OUT 70 15 OUT DDR2_DM<3> AJ2 DDR2_DM[3] DDR3_DM[3] AR13 DDR3_DM<3> OUT 15 70 0.1UF 1% 0.1UF 1%
20% 1/32W 20% 1/32W
F10 2 6.3V
X5R-CERM MF
01005 2 6.3V
X5R-CERM MF
70 14 BI DDR0_DQ<0> DDR0_DQ[0] DDR1_DQ[0] AA3 DDR1_DQ<0> BI 14 70 70 15 DDR2_DQ<0> AR3 DDR2_DQ[0] DDR3_DQ[0] AP7 DDR3_DQ<0> 15 70
01005
2 01005 2 01005
BI BI
DDR0_DQ<1> E10 DDR0_DQ[1] DDR1_DQ[1] AA2 DDR1_DQ<1>
BI BI 14 70
70 15 BI DDR2_DQ<1> AR2 DDR2_DQ[1] DDR3_DQ[1] AR7 DDR3_DQ<1> BI 15 70 PPVREF_DDR2_DQ_SOC 10 PPVREF_DDR3_DQ_SOC 10
70 14 DDR0_DQ<2> D10 DDR0_DQ[2] DDR1_DQ[2] AA1 DDR1_DQ<2> DDR2_DQ<2> AR1
BI BI 14 70
70 15 BI DDR2_DQ[2] DDR3_DQ[2] AT7 DDR3_DQ<2> BI 15 70
VOLTAGE=0.6V VOLTAGE=0.6V
DDR0_DQ<3> F9 DDR0_DQ[3] DDR1_DQ[3] Y3 DDR1_DQ<3> AP3

70 14 BI BI 14 70
70 15 BI DDR2_DQ<3> DDR2_DQ[3] DDR3_DQ[3] AP8 DDR3_DQ<3> BI 15 70
1 1
BI DDR0_DQ<4> D9 DDR0_DQ[4] DDR1_DQ[4] Y1 DDR1_DQ<4> BI 14 70
70 15 BI DDR2_DQ<4> AP1 DDR2_DQ[4] DDR3_DQ[4] AT8 DDR3_DQ<4> BI 15 70
1 C1185 R1185 1 C1187 R1187
70 14 DDR0_DQ<5> E8 DDR0_DQ[5] DDR1_DQ[5] W2 DDR1_DQ<5> AN2 DDR3_DQ<5> 0.1UF 4.7K 0.1UF 4.7K
BI BI 14 70
70 15 BI DDR2_DQ<5> DDR2_DQ[5] DDR3_DQ[5] AR9 BI 15 70
20% 20% 1%
DDR0_DQ<6> D8 DDR0_DQ[6] DDR1_DQ[6] W1 DDR1_DQ<6> 6.3V 6.3V 1/32W
BI BI 14 70
70 15 BI DDR2_DQ<6> AN1 DDR2_DQ[6] DDR3_DQ[6] AT9 DDR3_DQ<6> BI 15 70 2 X5R-CERM 2
14 70 01005 01005
DDR0_DQ<7> F7 DDR0_DQ[7] DDR1_DQ[7] V3 DDR1_DQ<7> AM3 DDR3_DQ<7> 01005 2 MF
01005
2 MF
BI BI 70 15 BI DDR2_DQ[7] DDR3_DQ[7] AP10 BI 15 70 X5R-CERM
DDR0_DQ<8> F4 DDR0_DQ[8] DDR1_DQ[8] T6 DDR1_DQ<8> DDR2_DQ<7> AH6 1/32W
BI BI 14 70
70 15 BI DDR2_DQ<8> DDR2_DQ[8] DDR3_DQ[8] AU11 DDR3_DQ<8> BI 15 70
C BI DDR0_DQ<9> E3 DDR0_DQ[9] DDR1_DQ[9] R5 DDR1_DQ<9> BI 14 70

70 15 BI DDR2_DQ<9>
DDR2_DQ<10>
AG5 DDR2_DQ[9] DDR3_DQ[9] AV12 DDR3_DQ<9>
DDR3_DQ<10> BI 15 70
1%
C
DDR0
DDR1
DDR0_DQ<10> C3 DDR0_DQ[10] DDR1_DQ[10] R4 DDR1_DQ<10>
DDR2
DDR3
BI BI 14 70 70 15 BI
AG4 DDR2_DQ[10] DDR3_DQ[10] AW12 BI 15 70
DDR0_DQ<11> F2 DDR0_DQ[11] DDR1_DQ[11] P6 DDR1_DQ<11> AF6
BI BI 14 70 70 15 BI DDR2_DQ<11> DDR2_DQ[11] DDR3_DQ[11] AU13 DDR3_DQ<11> BI 15 70
ONCE ROUTED SEG NEEDS TO CHECK PI OF *_VREF_DQ0
DDR0_DQ<12> D3 DDR0_DQ[12] DDR1_DQ[12] P4 DDR1_DQ<12> AF4 DDR3_DQ<12>
BI BI 14 70 70 15 BI DDR2_DQ<12> DDR2_DQ[12] DDR3_DQ[12] AW13 BI 15 70
AND *_VREF_DQ1 BEING TIED TOGETHER
DDR0_DQ<13> F1 DDR0_DQ[13] DDR1_DQ[13] N6 DDR1_DQ<13> AE6
BI BI 14 70 70 15 BI DDR2_DQ<13> DDR2_DQ[13] DDR3_DQ[13] AU14 DDR3_DQ<13> BI 15 70
DDR0_DQ<14> E1 DDR0_DQ[14] DDR1_DQ[14] N5 DDR1_DQ<14> AE5
BI BI 14 70
14 70
70 15 BI DDR2_DQ<14> DDR2_DQ[14] DDR3_DQ[14] AV14 DDR3_DQ<14> BI 15 70
DDR0_DQ<15> D2 DDR0_DQ[15] DDR1_DQ[15] N4 DDR1_DQ<15> DDR2_DQ<15> AE4 DDR3_DQ<15>
BI BI 70 15 BI DDR2_DQ[15] DDR3_DQ[15] AW14 BI 15 70
DDR0_DQ<16> C9 DDR0_DQ[16] DDR1_DQ[16] AC6 DDR1_DQ<16> AR6
BI BI 14 70
70 15 BI DDR2_DQ<16> DDR2_DQ[16] DDR3_DQ[16] AT4 DDR3_DQ<16> BI 15 70
DDR0_DQ<17> B9 DDR0_DQ[17] DDR1_DQ[17] AC5 DDR1_DQ<17> AR5
DDR3_DQ<17> =PP1V2_S2R_DDR_SOC
BI BI 14 70
70 15 BI DDR2_DQ<17> DDR2_DQ[17] DDR3_DQ[17] AU4 BI 15 70
72 10
DDR0_DQ<18> A9 DDR0_DQ[18] DDR1_DQ[18] AC4 DDR1_DQ<18>

BI BI 14 70
70 15 BI DDR2_DQ<18> AR4 DDR2_DQ[18] DDR3_DQ[18] AV4 DDR3_DQ<18> BI 15 70 1 C1190 1
R1190 1
BI DDR0_DQ<19> C8 DDR0_DQ[19] DDR1_DQ[19] AB6 DDR1_DQ<19> BI 14 70
70 15 BI DDR2_DQ<19> AP6 DDR2_DQ[19] DDR3_DQ[19] AU5 DDR3_DQ<19> BI 15 70 0.1UF 10K 1 C1192 R1192
DDR0_DQ<20> A8 DDR0_DQ[20] DDR1_DQ[20] AB4 DDR1_DQ<20> 14 70
AP4 20% 1% 0.1UF 10K
BI BI 70 15 BI DDR2_DQ<20> DDR2_DQ[20] DDR3_DQ[20] AW5 DDR3_DQ<20> BI 15 70 6.3V 1/32W 20% 1%
B7 DDR0_DQ[21] AA5 2 X5R-CERM 6.3V
BI DDR0_DQ<21> DDR1_DQ[21] DDR1_DQ<21> BI 14 70
70 15 DDR2_DQ<21> AN5 DDR2_DQ[21] DDR3_DQ[21] AV6 DDR3_DQ<21> 15 70 01005
MF
01005 2 X5R-CERM 1/32W
MF
BI DDR3_DQ<22> BI 2
DDR1_DQ[22] 01005
BI DDR0_DQ<22> A7 DDR0_DQ[22] AA4 DDR1_DQ<22> BI 14 70
70 15 DDR2_DQ<22> AN4 DDR2_DQ[22] DDR3_DQ[22] AW6 15 70
2 01005
BI BI
BI DDR0_DQ<23> C6 DDR0_DQ[23] DDR1_DQ[23] Y6 DDR1_DQ<23> BI 14 70
DDR2_DQ<23> AM6 DDR2_DQ[23] DDR3_DQ[23] AU7 DDR3_DQ<23> PPVREF_DDR0_CA_SOC 10
J4 DDR0_DQ[24] P3
70 15 BI BI 15 70 PPVREF_DDR1_CA_SOC 10
BI DDR0_DQ<24> DDR1_DQ[24] DDR1_DQ<24> BI 14 70
70 15 DDR2_DQ<24> AH3 DDR2_DQ[24] DDR3_DQ[24] AP14 DDR3_DQ<24> 15 70
VOLTAGE=0.6V
VOLTAGE=0.6V
BI BI
70 14 BI DDR0_DQ<25> H3 DDR0_DQ[25] DDR1_DQ[25] N2 DDR1_DQ<25> BI
14 70
DDR2_DQ<25> AG2 DDR2_DQ[25] DDR3_DQ[25] AR15 DDR3_DQ<25>
1 C1191 1
R1191 1
DDR0_DQ<26> G3 DDR0_DQ[26] N1 DDR1_DQ<26>
70 15 BI BI 15 70
0.1UF 10K
1 C1193 R1193
70 14 BI DDR1_DQ[26] BI 14 70
70 15 DDR2_DQ<26> AG1 DDR2_DQ[26] DDR3_DQ[26] AT15 DDR3_DQ<26> 15 70
20% 1% 0.1UF 10K
BI BI 6.3V
DDR0_DQ<27> J2 DDR0_DQ[27] DDR1_DQ[27] M3 DDR1_DQ<27> AF3 2 X5R-CERM 1/32W 20% 1%
70 14 BI BI 14 70
70 15 BI DDR2_DQ<27> DDR2_DQ[27] DDR3_DQ[27] AP16 DDR3_DQ<27> BI 15 70 01005 MF 2 6.3V 1/32W
DDR0_DQ<28> G2 DDR0_DQ[28] DDR1_DQ[28] M1 DDR1_DQ<28> DDR2_DQ<28> AF1 DDR3_DQ<28> 2 01005 X5R-CERM MF
70 14 BI BI 14 70
70 15 BI DDR2_DQ[28] DDR3_DQ[28] AT16 BI 15 70 01005
2 01005
DDR0_DQ<29> J1 DDR0_DQ[29] DDR1_DQ[29] L3 DDR1_DQ<29> DDR2_DQ<29>
70 14 BI BI 14 70
70 15 BI
AE3 DDR2_DQ[29] DDR3_DQ[29] AP17 DDR3_DQ<29> BI 15 70
DDR0_DQ<30> H1 DDR0_DQ[30] DDR1_DQ[30] L2 DDR1_DQ<30> DDR2_DQ<30> AE2 DDR3_DQ<30>
DDR3_DQ[30] AR17
70 14 14 70
BI BI 70 15 BI DDR2_DQ[30] BI 15 70
DDR0_DQ<31> G1 DDR0_DQ[31] DDR1_DQ[31] L1 DDR1_DQ<31> 14 70 AE1
70 14 BI BI 70 15 BI DDR2_DQ<31> DDR2_DQ[31] DDR3_DQ[31] AT17 DDR3_DQ<31> BI 15 70
DDR2_DQS_P<0>
DDR0_DQS_P<0> D7 DDR0_PDQS[0] DDR1_PDQS[0] V1 DDR1_DQS_P<0> AM1 DDR3_DQS_P<0>
DDR3_PDQS[0] AT10
70 14 14 70
BI BI 70 15 BI DDR2_PDQS[0] BI
15 70
DDR0_DQS_N<0> D6 DDR0_NDQS[0] DDR1_NDQS[0] U1 DDR1_DQS_N<0> 14 70 DDR2_DQS_N<0> AL1
DDR3_DQS_N<0> 1 1
BI BI 70 15 BI DDR2_NDQS[0] DDR3_NDQS[0] AT11 BI 15 70 1 C1180 R1180 1 C1182 R1182
B 70 14
BI DDR0_DQS_P<1> D4 DDR0_PDQS[1] DDR1_PDQS[1] T4 DDR1_DQS_P<1> BI 14 70
70 15 BI
DDR2_DQS_P<1> AH4
DDR2_PDQS[1] DDR3_PDQS[1]
AW11 DDR3_DQS_P<1>
BI 15 70
0.1UF
20%
6.3V
10K
1%
1/32W
0.1UF
20%
6.3V
10K
1%
1/32W
B
DDR0_DQS_N<1> D5 DDR0_NDQS[1] DDR1_NDQS[1] U4 DDR1_DQS_N<1> DDR2_DQS_N<1> AJ4 DDR3_DQS_N<1> 2 MF 2 X5R-CERM MF
DDR3_NDQS[1] AW10 01005 01005
70 14 14 70
BI BI 70 15 BI DDR2_NDQS[1] BI 15 70 01005 01005
X5R-CERM 2 2
A6 Y4 DDR2_DQS_P<2> AM4 AW7
70 14 BI DDR0_DQS_P<2> DDR0_PDQS[2] DDR1_PDQS[2] DDR1_DQS_P<2> BI
14 70
70 15 DDR2_PDQS[2] DDR3_PDQS[2] DDR3_DQS_P<2> 15 70
PPVREF_DDR2_CA_SOC 10 PPVREF_DDR3_CA_SOC 10
A5 DDR0_NDQS[2] BI BI
DDR0_DQS_N<2> DDR1_NDQS[2] W4 DDR1_DQS_N<2> 14 70
DDR2_DQS_N<2> AL4 AW8 VOLTAGE=0.6V VOLTAGE=0.6V
70 14 BI BI 70 15 BI DDR2_NDQS[2] DDR3_NDQS[2] DDR3_DQS_N<2> BI 15 70
1 1
G4 P1
1 C1181 R1181 1 C1183 R1183
DDR2_DQS_P<3> AH1 AT14 0.1UF 10K 0.1UF 10K
70 14
BI DDR0_DQS_P<3> G5 DDR0_PDQS[3] DDR1_PDQS[3] R1 DDR1_DQS_P<3> BI 14 70
70 15 DDR2_PDQS[3] DDR3_PDQS[3] AT13 DDR3_DQS_P<3> 15 70 20% 1% 20% 1%
BI DDR2_DQS_N<3> AJ1 BI
BI DDR0_DQS_N<3> DDR0_NDQS[3] DDR1_NDQS[3] DDR1_DQS_N<3> BI 14 70 DDR3_DQS_N<3> 6.3V
2 X5R-CERM 1/32W 6.3V
2 X5R-CERM 1/32W
70 15 BI DDR2_NDQS[3] DDR3_NDQS[3] BI 15 70 01005 MF MF
01005
01005
A13 A19 2 01005 2
AW24 AW18
10 PPVREF_DDR0_CA_SOC DDR0_VREF_CA DDR1_VREF_CA PPVREF_DDR1_CA_SOC 10
10 PPVREF_DDR2_CA_SOC DDR2_VREF_CA DDR3_VREF_CA PPVREF_DDR3_CA_SOC 10
DDR0_ZQ_CA_SOC C13 DDR0_ZQ_CA DDR1_ZQ_CA F18 DDR1_ZQ_CA_SOC AU24
10 10
10 DDR2_ZQ_CA_SOC DDR2_ZQ_CA DDR3_ZQ_CA AU18 DDR3_ZQ_CA_SOC 10
H10 AA7
PPVREF_DDR0_DQ_SOC PPVREF_DDR2_DQ_SOC AL7 AN9
L6 DDR0_VREF_DQ0
10
10 DDR1_VREF_DQ0 R7 PPVREF_DDR1_DQ_SOC DDR2_VREF_DQ0 DDR3_VREF_DQ0 AN15 PPVREF_DDR3_DQ_SOC
10 AG7 10
DDR0_VREF_DQ1 DDR1_VREF_DQ1 DDR2_VREF_DQ1 DDR3_VREF_DQ1
DDR0_ZQ_DQ0_SOC G9 DDR0_ZQ_DQ0 DDR1_ZQ_DQ0 AA6 DDR1_ZQ_DQ0_SOC DDR2_ZQ_DQ0_SOC AL6 DDR2_ZQ_DQ0 DDR3_ZQ_DQ0_SOC

10
DDR1_ZQ_DQ1_SOC
10
10 DDR3_ZQ_DQ0 AP9 10
DDR0_ZQ_DQ1_SOC M6 DDR0_ZQ_DQ1 DDR1_ZQ_DQ1 R6 AG6 DDR2_ZQ_DQ1
10 10
10 DDR2_ZQ_DQ1_SOC DDR3_ZQ_DQ1 AP15 DDR3_ZQ_DQ1_SOC 10
10
F13 VDD12_CKE_DDR0
=PP1V2_S2R_DDR_SOC =PP1V2_S2R_DDR_SOC
=PP1V2_S2R_DDR_SOC VDD12_CKE_DDR1 F17 AP24
72 10 72
72 10 VDD12_CKE_DDR2 VDD12_CKE_DDR3 AP19 =PP1V2_S2R_DDR_SOC 10 72
C1101 1 1 C1100 C1102 1 1 C1103

0.22UF 0.22UF 0.22UF 0.22UF
20% 20% 20% 20%
6.3V 2 SEG: OK TO FLOAT CK, CKB, CKE AND CSN PINS 2 6.3V 6.3V 6.3V
X5R X5R
01005-1 X5R 2 SEG: OK TO FLOAT CK, CKB, CKE AND CSN PINS 2 X5R
01005-1 01005-1 01005-1
A DDR0_ZQ_CA_SOC 10 DDR1_ZQ_CA_SOC 10 DDR2_ZQ_CA_SOC 10 DDR3_ZQ_CA_SOC 10 SYNC_MASTER=N/A SYNC_DATE=N/A A

DDR0_ZQ_DQ0_SOC 10 DDR1_ZQ_DQ0_SOC 10 PAGE TITLE
DDR2_ZQ_DQ0_SOC 10 DDR3_ZQ_DQ0_SOC 10
DDR0_ZQ_DQ1_SOC 10 DDR1_ZQ_DQ1_SOC 10 DDR2_ZQ_DQ1_SOC 10 DDR3_ZQ_DQ1_SOC 10 SOC: DDR
DRAWING NUMBER SIZE
1
R1100 1R1102 1R1104 1
R1101 1R1103 1R1105 1 Apple Inc. 051-0301 D
240 240 240 240 240 240
R1106 1R1107 1R1108 1
R1109 1R1110 1R1111 REVISION
240 240 240 240 240 240 R
1%
1/32W
1%
1/32W
1%
1/32W
1%
1/32W
1%
1/32W 1%
1/32W
1%
1/32W
1%
1/32W
1%
1/32W
1%
1/32W
1%
1/32W BRANCH
B.0.0
MF MF 01005 MF MF MF
01005 MF MF MF MF MF MF NOTICE OF PROPRIETARY PROPERTY:
01005 01005 01005
2 01005 2 01005 2 MF 2 01005 2 01005 2 2 01005 2 2 01005 2 2 01005 2 THE INFORMATION CONTAINED HEREIN IS THE
1/32W PROPRIETARY PROPERTY OF APPLE INC.
1%
SHEET
10 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
PLACE_NEAR=U0600.H21:13MM
XW12A0 R1290
SHORT-10L-0.5MM-SM VOLTAGE=1.2V
G12 3.5MA EACH AF16
VOLTAGE=1.2V 0.00 2
72 11 10 =PP1V2_VDDIOD_SOC 1 2 PP1V2_VDDIOD_DDR01CA VDDIOD_DDR01CA VDDA12_PLL_CPU PP1V2_PLL_SOC_FILT 1 =PP1V2_PLL_SOC 9 11 72
G14 U0600 H21 0%
D 1 C1260
1.0UF
1 C1261
1.0UF
1 C1262
1.0UF
1 C1265
0.47UF
1 C1266
0.47UF
1 C1267
0.47UF
1 C1268
0.22UF
1 C1269
0.22UF
G16
VDDIOD_DDR01CA TMKP88A0-N LPDP_VDDA12_PLL
VDDIOD_DDR01CA FCBGA VDDA12_PLL_MIPIT
AP29
1 C1290
0.01UF
10%
1 C1291
0.22UF
20%
1/32W
MF
01005
D
20% 20% 20% G18 VDDIOD_DDR01CA SYM 11 OF 15
2 X5R 2 X5R 2 X5R
VOLTAGE=4V
2 CERM-X5R-1
VOLTAGE=4V
2 CERM-X5R-1
VOLTAGE=4V
2 CERM-X5R-1 2 X5R 2 VOLTAGE=6.3V
X5R 2 VOLTAGE=6.3V
X5R
2 X5R G20 VDDIOD_DDR01CA OMIT_TABLE 01005 01005-1
0201-1
VOLTAGE=6.3V 0201-1
VOLTAGE=6.3V 0201-1
VOLTAGE=6.3V 201 201 201 01005-1
VOLTAGE=6.3V
01005-1
VOLTAGE=6.3V VDDIOD_DDR01CA VDDA18__SOC1_TSADC M32
20% 20% 20% 20% H13
20%
VDDA18_SOC0_TSADC W18
H15 VDDIOD_DDR01CA
H17 VDDIOD_DDR01CA AF18
1MA VDDA18_CPU_TSADC0
XW12C0 H19 VDDIOD_DDR01CA AH12
SHORT-10L-0.5MM-SM VOLTAGE=1.2V VDDA18_CPU_TSADC1
=PP1V2_VDDIOD_SOC 1 2 PP1V2_VDDIOD_DDR23CA AM17 VDDIOD_DDR23CA AE12
72 11 10 VDDA18_CPU_TSADC2
AM19 VDDIOD_DDR23CA AG18 =PP1V8_VDDIO18_SOC
VDDA18_CPU_TSADC3 11 72
1 C1270 1 C1271 1 C1272 1 C1275 1 C1276 1 C1277 1 C1278 1 C1279 AM21 VDDIOD_DDR23CA
1.0UF 1.0UF 1.0UF 0.47UF 0.47UF 0.47UF 0.22UF 0.22UF
20%
VOLTAGE=4V
20%
VOLTAGE=4V
AM25 VDDIOD_DDR23CA 1 C1235 1 C1236 1 C1237 1 C1238
2 X5R 2 X5R 2 X5R 2 CERM-X5R-1 2 CERM-X5R-1 2 CERM-X5R-1 2 X5R 2 X5R AN18 VDDIOD_DDR23CA AB35 0.22UF 0.22UF 0.22UF 0.22UF
0201-1
VOLTAGE=6.3V 0201-1
VOLTAGE=6.3V 0201-1
VOLTAGE=6.3V 201 201 201
VOLTAGE=4V VDDIO18_GRP1
01005-1
VOLTAGE=6.3V 01005-1
VOLTAGE=6.3V
AN20 VDDIOD_DDR23CA AD35 2 X5R
20% 20% 20% 20% 20% 20% VDDIO18_GRP1 2 X5R 2 X5R 2 X5R
AN22 VDDIOD_DDR23CA AF35 01005-1
VOLTAGE=6.3V
01005-1
VOLTAGE=6.3V
VDDIO18_GRP1 20%
AN24 VDDIOD_DDR23CA GPIO, UART, DWI, AH35 20% 20% 20%
VDDIO18_GRP1
AM23 VDDIOD_DDR23CA I2C,
FAIL
I2S, SPI,
SAFE, TIMER, VDDIO18_GRP1 AK35
MISC, ISP_UART0,
72 11 10 =PP1V2_VDDIOD_SOC AM11 VDDIOD_DDRDQ SEP, JTAG, VDDIO18_GRP1 AL34
CLK32K_OUT, =PP1V8_VDDIO18_SOC 11 72
AM13 VDDIOD_DDRDQ ULPI, PCIE GPIO VDDIO18_GRP1 AM35
C1200 1
AM15 VDDIOD_DDRDQ VDDIO18_GRP1 K35 CRITICAL
15UF 30MA C1240 1 C1242 1 C1243 1 C1244 1 C1245 1 C1246 1 C1247 1 C1248 1 C1249 1
20% AM9 VDDIOD_DDRDQ VDDIO18_GRP1 M35
VOLTAGE=4V 4.3UF 1.0UF 1.0UF 1.0UF 0.47UF 0.47UF 0.22UF 0.22UF 8.2PF
CERM 2 AA8 VDDIOD_DDRDQ VDDIO18_GRP1 P35 20% 20% 20% 20% 20% 20% 20% 20% +/-0.5PF
0402 VOLTAGE=4V VOLTAGE=6.3V VOLTAGE=6.3V VOLTAGE=6.3V VOLTAGE=4V VOLTAGE=4V 50V
AB5 VDDIOD_DDRDQ VDDIO18_GRP1 T35 X5R-CERM 2 X5R 2 X5R 2 X5R 2 CERM-X5R-1 2 CERM-X5R-1 2 X5R 2 X5R 2 C0G-CERM 2
0610 0201-1 0201-1 0201-1 201 201 01005-1
VOLTAGE=6.3V 201
AM7 VDDIOD_DDRDQ VDDIO18_GRP1 V35
AN10 VDDIOD_DDRDQ VDDIO18_GRP1 Y35
AN12 VDDIOD_DDRDQ
3MA VDDIO18_GRP0 AM28
CRITICAL CRITICAL AN14 ISP[0|1]_I2C,
C1203 1 C1204 1 VDDIOD_DDRDQ SENSOR[0|1] L1290
C 4.3UF
20%
VOLTAGE=4V
4.3UF
20%
VOLTAGE=4V
AN16
AB7
VDDIOD_DDRDQ
VDDIOD_DDRDQ H32
120-OHM-25%-250MA-0.5DCR
1 2 =PP1V8_XTAL_SOC
C
X5R-CERM 2 X5R-CERM 2 AN8 VDDIO18_PPN H33
72
0610 0610 VDDIOD_DDRDQ 75MA VDDIO18_PPN 01005 PLACE_NEAR=U0600.H35:5MM

AP2 VDDIOD_DDRDQ H34 C1280 1
VDDIO18_PPN 0.22UF
AP5 VDDIOD_DDRDQ VOLTAGE=1.8V
20%
1MA VDDIO18_XTAL H35 69 PP1V8_XTAL VOLTAGE=6.3V
AR16 VDDIOD_DDRDQ X5R 2
AR8 AM27 01005-1
VDDIOD_DDRDQ 1MA VDDIO18_AON
C1205 1 C1206 1 C1207 1 C1208 1 C1209 1 AV13 VDDIOD_DDRDQ
VDD18_EFUSE1 AL35 PPVDD18_EFUSE1
1.0UF 1.0UF 1.0UF 1.0UF 1.0UF AV5 VDDIOD_DDRDQ CKPLUS_WAIVE=PWRTERM2GND
4
20% 20% 20% 20% 20% EFUSE SHOULD BE TIED TO GROUND PER SEG
VOLTAGE=6.3V VOLTAGE=6.3V VOLTAGE=6.3V VOLTAGE=6.3V B8 VDDIOD_DDRDQ VDD_ANA_PLL0 V19 =PP1V8_ALWAYS 6 62 72
X5R 2 X5R 2 X5R 2 X5R 2 X5R 2
0201-1 0201-1 0201-1 0201-1 0201-1
VOLTAGE=6.3V E2 VDDIOD_DDRDQ VDD_ANA_PLL1 AA18
E9 VDDIOD_DDRDQ 21MA VDD_ANA_PLL2 U19 C1281 1
AD7 V18
0.22UF
VDDIOD_DDRDQ VDD_ANA_PLL4 20%
VOLTAGE=6.3V
G10 VDDIOD_DDRDQ VDD_ANA_PLL5 Y18 X5R 2
01005-1
G8 VDDIOD_DDRDQ
C1210 1 C1211 1 C1212 1
H11 VDDIOD_DDRDQ
1.0UF 1.0UF 1.0UF PLACE_NEAR=U0600.V19:11MM
20% 20% 20% AF2 VDDIOD_DDRDQ R1291
VOLTAGE=6.3V VOLTAGE=6.3V VOLTAGE=6.3V
X5R 2 X5R 2 X5R 2 H2 VDDIOD_DDRDQ
VOLTAGE=1.2V 0.00 2
0201-1 0201-1 0201-1 PP1V2_ANA_PLL_SOC_FILT 1 =PP1V2_PLL_SOC 9 11 72
H7
VDDIOD_DDRDQ 0%
H9 1 C1296 1 C1297 1 C1298 1/32W
VDDIOD_DDRDQ 1 C1299 MF
J8 0.22UF 0.01UF 0.01UF 8.2PF 01005
VDDIOD_DDRDQ 20% 10% 10% +/-0.5PF
K7
VDDIOD_DDRDQ 2 VOLTAGE=6.3V
X5R 2 VOLTAGE=6.3V
X5R
VOLTAGE=6.3V
2 X5R 50V
2 C0G-CERM
L8 01005-1 01005 01005 201
C1220 1 C1221 1 C1222 1 C1223 1 C1224 1 VDDIOD_DDRDQ
0.47UF 0.47UF 0.47UF 0.47UF 0.47UF M2
VDDIOD_DDRDQ
20% 20% 20% 20% 20% M7
VOLTAGE=4V VOLTAGE=4V VOLTAGE=4V VOLTAGE=4V VOLTAGE=4V VDDIOD_DDRDQ
CERM-X5R-1 2 CERM-X5R-1 2 CERM-X5R-1 2 CERM-X5R-1 2 CERM-X5R-1 2 AF5 V7
201 201 201 201 201 VDDIOD_DDRDQ VDDIOD_DDRDQ
N8 W8
B P5
VDDIOD_DDRDQ
VDDIOD_DDRDQ
VDDIOD_DDRDQ
VDDIOD_DDRDQ Y2 B
P7 VDDIOD_DDRDQ Y7
VDDIOD_DDRDQ
R8 VDDIOD_DDRDQ AF7
VDDIOD_DDRDQ
C1225 1 C1226 1 C1227 1 T7
VDDIOD_DDRDQ VDDIOD_DDRDQ AH7
0.47UF 0.47UF 0.47UF U8 AK7
20% 20% 20% VDDIOD_DDRDQ VDDIOD_DDRDQ
VOLTAGE=4V VOLTAGE=4V VOLTAGE=4V
CERM-X5R-1 2 CERM-X5R-1 2 CERM-X5R-1 2
201 201 201
C1230 1 C1231 1 C1232 1

0.22UF 0.22UF 100PF
20% 20% 5%
25V 2
X5R 2 X5R 2 C0G
01005-1
VOLTAGE=6.3V 0201
PAGE TITLE
SOC: IO POWER
DRAWING NUMBER SIZE
TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: REVISION
PART NUMBER R
TABLE_ALT_ITEM
REFDES FOR ALTERATIVE TABLE
BRANCH
B.0.0
138S0702 138S0657 QTY 22 RDAR://PROBLEM/8837828 C1203,C1204,C1240, C1305-C1308, C1404-C1409,C1464-C1469,C1445,C1446 NOTICE OF PROPRIETARY PROPERTY:
TABLE_ALT_ITEM

138S0702 138S0657 QTY 22 RDAR://PROBLEM/8837828 C1602,C1603,C1642,C1643, C1702,C1703,C1742,C1743 PROPRIETARY PROPERTY OF APPLE INC.
SHEET
11 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
A1 VSS VSS AD8 AK3 VSS VSS AT6 D31 VSS VSS K2 R27 VSS VSS W9
A21 VSS
U0600 VSS AE11 AK30 VSS
U0600 VSS AU1 D33 VSS
U0600 VSS K20 R29 VSS
U0600 VSS Y10
TMKP88A0-N TMKP88A0-N TMKP88A0-N TMKP88A0-N
A22 VSS FCBGA VSS AE13 AK32 VSS FCBGA VSS AU10 D34 VSS FCBGA VSS K22 R3 VSS FCBGA VSS Y12
A24 VSS SYM 12 OF 15 VSS AE17 AK34 VSS SYM 13 OF 15 VSS AU12 D37 VSS SYM 14 OF 15 VSS K24 R31 VSS SYM 15 OF 15 VSS Y14
A26 VSS OMIT_TABLE VSS AE19 AK4 VSS OMIT_TABLE VSS AU15 E11 VSS OMIT_TABLE VSS K26 R33 VSS OMIT_TABLE VSS Y16
72 =PP0V95_SOC A27 AE21 AK5 AU17 E12 K28 R35
VSS VSS VSS VSS VSS VSS VSS VSS Y20
CRITICAL CRITICAL CRITICAL CRITICAL A29 AE23 AK6 AU21 E15 K3 R9
1 1 1 1 VSS VSS VSS VSS VSS VSS VSS VSS Y22
C1305 C1306 C1307 C1308
4.3UF 4.3UF 4.3UF 4.3UF A3 VSS VSS AE25 AK8 VSS VSS AU23 E16 VSS VSS K32 T1 VSS VSS Y24
20% 20% 20% 20% AL10 VDD_SOC VDD_SOC J32
4V 4V 4V 4V U0600 A31 VSS VSS AE27 AL11 VSS VSS AU27 E17 VSS VSS K37 T10 VSS VSS Y26
2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM AL14 VDD_SOC K11
TMKP88A0-N VDD_SOC
D 0610 0610 0610 0610
AL18
AA10
VDD_SOC FCBGA VDD_SOC AA20
A33
A34
VSS
VSS
VSS
VSS
AE29
AE31
AL13
AL17
VSS
VSS
VSS
VSS
AU28
AU29
E22
E24
VSS
VSS
VSS
VSS
K4
K40
T12
T14
VSS
VSS
VSS
VSS
Y28
Y30
D
VDD_SOC SYM 10 OF 15 VDD_SOC K13 A39 AE33 AL19 AU3 E26 K5 T16 VSS
AA12 VSS VSS VSS VSS VSS VSS VSS Y32
VDD_SOC OMIT_TABLE VDD_SOC K15 A41 AE35 AL21 AU30 E27 K6 T18 VSS
AC18 VDD_SOC K17 VSS VSS VSS VSS VSS VSS
VDD_SOC AA11 AE37 AL23 AU31 E34 K8 T2 VSS_SENSE M26 TP_SOC_VSS_SENSE 70
CRITICAL CRITICAL CRITICAL T19 VDD_SOC K19 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC
1 C1320 1 C1321 1 C1322 T21
AA13 VSS VSS AE40 AL25 VSS VSS AU32 E4 VSS VSS L11 T20 VSS VSS_CPU_SENSE AC13 TP_SOC_VSS_CPU_SENSE 70
1.0UF 1.0UF 1.0UF VDD_SOC VDD_SOC K21 AA15 AE7 AL27 AU33 E7 VSS L13 T22
20% 20% 20% T23 VDD_SOC K23 VSS VSS VSS VSS VSS VSS
6.3V 6.3V 6.3V VDD_SOC AA17 AE9 AL29 AU34 F11 L15 T24
2 X5R 2 X5R 2 X5R T34 VSS VSS VSS VSS VSS VSS VSS
0201-1 0201-1 0201-1 VDD_SOC VDD_SOC K25 AA19 AF10 AL3 AU35 F12 L17 T26
T9 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC K31 AA21 AF12 AL31 AU36 F14 L19 T28
U10 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC AA22 AA27 AF22 AL40 AU41 F19 L25 T32
CRITICAL CRITICAL CRITICAL U16 VSS VSS VSS VSS VSS VSS VSS
1 C1323 1 C1324 1 C1325 VDD_SOC VDD_SOC L10 AA29 AF24 AL9 AU6 F26 L31 T37
1.0UF 1.0UF 1.0UF VDD_SOC VDD_SOC L12
20% 20% 20% AA31 VSS VSS AF26 AM10 VSS VSS AU8 F27 VSS VSS L33 T40 VSS
6.3V 6.3V 6.3V AC20 VDD_SOC VDD_SOC L14
2 X5R 2 X5R 2 X5R AA33 VSS VSS AF28 AM12 VSS VSS AU9 F28 VSS VSS L4 T5 VSS
0201-1 0201-1 0201-1 U20 VDD_SOC VDD_SOC L16 AA35 VSS VSS AF30 AM14 VSS VSS AV11 F3 VSS VSS L5 T8 VSS
U22 VDD_SOC VDD_SOC L18
AA9 VSS VSS AF32 AM16 VSS VSS AV15 F30 VSS VSS L7 U11 VSS
V11 VDD_SOC VDD_SOC L20 AB1 VSS VSS AF34 AM18 VSS VSS AV18 F32 VSS VSS L9 U13 VSS
V13 VDD_SOC VDD_SOC L22
SOC PD PARTITIONS)
AB10 VSS VSS AF8 AM2 VSS VSS AV2 F34 VSS VSS M10 U15 VSS
V15 VDD_SOC VDD_SOC L24 AB12 VSS VSS AG21 AM20 VSS VSS AV20 F38 VSS VSS M12 U17 VSS
CRITICAL CRITICAL V17 VDD_SOC VDD_SOC L26
1 C1330 1 C1331 AB14 VSS VSS AG23 AM22 VSS VSS AV24 F40 VSS VSS M14 U21 VSS
V21 VDD_SOC VDD_SOC L30
0.47UF 0.47UF AB16 VSS AG25 AM24 VSS VSS AV26 F5 VSS VSS M16 U23 VSS
V23 VSS
VDD_SOC VDD_SOC AB17 AB18 AG27 AM30 AV28 F6 M18 U25
2 2
V9 VSS VSS VSS VSS VSS VSS VSS
201 CERM- 201 CERM- VDD_SOC VDD_SOC L32 AB2 AG29 AM32 AV34 F8 M20 U27
X5R-1 4V X5R-1 4V W10 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC M11
20% 20% AB20 VSS VSS AG3 AM34 VSS VSS AV40 G11 VSS VSS M22 U29 VSS
AC22 VDD_SOC VDD_SOC M13 AB22 VSS VSS AG31 AM5 VSS VSS AV7 G13 VSS VSS M24 U3 VSS
W12 VDD_SOC M15
C W14
VDD_SOC
VDD_SOC VDD_SOC M17
AB24
AB26
VSS
VSS
VSS
VSS
AG33
AG35
AM8
AN11
VSS
VSS
VSS
VSS
AV9
AW1
G15
G17
VSS
VSS
VSS
VSS
Y8
M30
U31
U33
VSS C
W16 VSS
VDD_SOC M19
4.0A MAX,
VDD_SOC AB28 AG9 AN13 AW28 G19 M4 U35
1 C1340 1 C1341 1 C1345 W20 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC M21 AB3 AH10 AN17 AW3 G21 M5 U6
0.22UF 0.22UF 100PF W22 VSS VSS VSS VSS VSS VSS VSS
20% 20% 5% VDD_SOC VDD_SOC M23 AB30 AH14 AN19 AW34 G22 M8 U7
2 6.3V 2 6.3V 2 16V
NP0-C0G Y11 VSS VSS VSS VSS VSS VSS VSS
X5R X5R 01005 VDD_SOC VDD_SOC M27 AB32 AH16 AN21 AW39 G24 N11 U9
01005-1 01005-1 VSS VSS VSS VSS VSS VSS VSS
Y13 VDD_SOC VDD_SOC AB19 AB34 VSS VSS AH18 AN23 VSS VSS AW41 G25 VSS VSS N13 V10 VSS
Y15 VDD_SOC VDD_SOC M29
0.904V - 0.996V, AB37 VSS VSS AH2 AN25 VSS VSS AW9 G31 VSS VSS N15 V12 VSS
Y17 VDD_SOC VDD_SOC M31 AB40 VSS VSS AH20 AN27 VSS VSS B11 G32 VSS VSS N17 V14 VSS
Y19 VDD_SOC VDD_SOC M33 AB8 VSS VSS AH22 AN29 VSS VSS B13 G33 VSS VSS N19 V16 VSS
AD17 VDD_SOC VDD_SOC M9 AC1 VSS VSS AH24 AN3 VSS VSS B17 G34 VSS VSS N21 V2 VSS
Y21 VDD_SOC VDD_SOC N10 AC11 VSS VSS AH26 AN31 VSS VSS B19 G6 VSS VSS N23 V20 VSS
Y23 VDD_SOC VDD_SOC N12 Y5 VSS VSS AH28 AN6 VSS VSS B2 G7 VSS VSS N27 V22 VSS
Y34 VDD_SOC VDD_SOC N14 AC17 VSS VSS AH30 AN7 VSS VSS B21 H12 VSS VSS N29 V24 VSS
Y9 VDD_SOC VDD_SOC N16 AC19 VSS VSS AH32 AP11 VSS VSS B27 H14 VSS VSS N3 V26 VSS
AD19 VDD_SOC VDD_SOC N18 AC2 VSS VSS AH37 AP12 VSS VSS B34 H16 VSS VSS N31 V28 VSS
AD21 VDD_SOC VDD_SOC N20
(VDD_SOC,
AC21 VSS VSS AH40 AP13 VSS VSS B36 H18 VSS VSS N33 V30 VSS
AD23 VDD_SOC VDD_SOC AB21 AC23 VSS VSS AH5 AP18 VSS VSS B4 H20 VSS VSS N35 V32 VSS
AD34 VDD_SOC VDD_SOC N22 AC25 VSS AH8 AP20 VSS VSS B40 H26 VSS VSS N37 V34 VSS
AE18 VDD_SOC VDD_SOC P11 VSS
AC27 VSS AJ11 AP21 VSS VSS B6 H27 VSS VSS N40 V4 VSS
AC29 VSS AJ13 AP22 VSS VSS C1 H28 VSS VSS N7 V5 VSS
AA14 VDD_SOC VDD_SOC P15 VSS
AC3 VSS AJ17 AP23 VSS VSS C10 H30 VSS VSS N9 V6 VSS
AC31 VSS AJ19 AP25 VSS VSS C14 H4 VSS VSS P10 V8 VSS
AF23 VDD_SOC VDD_SOC P19 VSS
AC33 VSS AJ21 AP26 VSS VSS C16 H6 VSS VSS P12 W11 VSS
AH23 VDD_SOC VDD_SOC P21 VSS
AC35 VSS AJ23 AP28 VSS VSS C20 H8 VSS VSS P14 W13 VSS
AH34 VDD_SOC VDD_SOC P23 VSS
AC7 VSS AJ25 AP37 VSS VSS C21 J11 VSS VSS P16 W15 VSS
AK23 VDD_SOC VDD_SOC P9 VSS
B AL24
AL26
VDD_SOC VDD_SOC R10
AC9
AD1
VSS
VSS
VSS
VSS
AJ27
AJ29
AP40
AR10
VSS
VSS
VSS
VSS
C23
C25
J13
J15
VSS
VSS
VSS
VSS
P18
P2
W17
W19
VSS
VSS
B
VDD_SOC VDD_SOC AB23 AD10 AJ3 AR12 C27 J17 P20 W21
AL28 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC R12 AD12 AJ31 AR14 C28 J19 P22 W23
AL30 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC R14 AD16 AJ33 AR18 C30 J29 P24 W25
AL32 VSS VSS VSS VSS VSS VSS
VDD_SOC VDD_SOC R16 AD18
VSS
AJ35 AR21 C32 J3 P26 W27
AA16 VSS VSS VSS VSS VSS VSS
VSS
AJ6 AR22 C34 J30 P28 W29
J10 VDD_SOC R20 VSS VSS VSS VSS VSS VSS VSS
VDD_SOC AD20 AJ7 AR25 C4 J33 P30 W3
J12 VSS VSS VSS VSS VSS VSS
VSS
AJ9 AR26 C41 J5 P32 W31
VDD_SOC VDD_SOC T11 AD24
VSS
AK1 AR27 C5 J6 P8 W33
VSS
AK12 AR33 C7 J7 R11 W35
VSS
AK16 AR36 D11 J9 R13 W37
VSS
AK18 AT12 D21 K1 R15 W40
VDD_SOC VDD_SOC L29 AD30
VSS
AK2 AT2 D22 K10 R17 W6
VDD_SOC VDD_SOC M28 AD32
VSS
AK22 AT22 D24 K12 R19 W7
VSS VSS VSS VSS VSS VSS
VSS
VDD_SOC_SENSE M25 AD4 VSS AK24 AT28 VSS VSS D26 K14 VSS VSS R21
VSS
AD5 VSS AK26 AT3 VSS VSS D27 K16 VSS VSS R23
AD6 VSS AK28 AT5 D29 K18 R25
VSS VSS VSS VSS VSS
VSS
70 62 PPVDD_SOC_SOC_SENSE
VOLTAGE=0.95V
PAGE TITLE
SOC: SOC POWER AND GND

DRAWING NUMBER SIZE

REVISION
R
BRANCH
B.0.0
SHEET
12 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
72 =PPVDD_CPU
CRITICAL CRITICAL =PPVDD_GPU 72
1 C1400 1 C1401 C1405 C1406 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
15UF 15UF 7.5UF 7.5UF AB11 VDD_CPU VDD_GPU AA26 1 C1460 1 C1461 1 C1464 1 C1465 1 C1466 1 C1467 1 C1468 1 C1469
20% 20% 20% 20% U0600
4V 4V AD15 VDD_CPU AA28 15UF 15UF 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF
2 4V
CERM 2 4V
CERM CERM CERM TMKP88A0-N VDD_GPU 20% 20%
0402 0402 0402 0402 AD9 VDD_CPU FCBGA VDD_GPU AC34 2 4V 2 4V 2 2 2 2 2 2
1 3 1 3 CERM CERM
AE10 VDD_CPU AD25 0402 0402 0610 0610 0610 0610 0610 0610
SYM 9 OF 15 VDD_GPU
X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM
AE14 VDD_CPU OMIT_TABLE VDD_GPU AD29
2 4 2 4 4V 4V 4V 4V 4V 4V
D AE16 VDD_CPU
AE8 VDD_CPU
VDD_GPU
VDD_GPU
AD31
AE26
20% 20% 20% 20% 20% 20% D
AF13 VDD_CPU AE28 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
VDD_GPU 1 C1470 1 C1471 1 C1472 1 C1473 1 C1474 1 C1475
AF15 VDD_CPU VDD_GPU AE32 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL AF17 VDD_CPU AE34 20% 20% 20% 20% 20% 20%
C1410 C1411 C1412 C1413 C1414 C1415 C1416 VDD_GPU 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
4.3UF 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF 4.3UF AF19 VDD_CPU VDD_GPU AF25 0201-1 0201-1 0201-1 0201-1 0201-1 0201-1
20% 20% 20% 20% 20% 20% 20% AB15 VDD_CPU AF29 X5R X5R X5R X5R X5R X5R
4V 4V 4V 4V 4V 4V 4V VDD_GPU
CERM CERM CERM CERM CERM CERM CERM AF21 VDD_CPU AA32
0402 0402 0402 0402 0402 0402 0402 VDD_GPU
1 3 1 3 1 3 1 3 1 3 1 3 1 3 AF9 VDD_CPU VDD_GPU AF31
AG10 VDD_CPU VDD_GPU AG26 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
2 4 2 4 2 4 2 4 2 4 2 4 2 4 AG12 VDD_CPU AG28 1 C1480 1 C1481 1 C1482 1 C1483 1 C1484 1 C1485
VDD_GPU
AG14 VDD_CPU AG32 0.47UF 0.47UF 0.47UF 0.47UF 0.47UF 0.47UF
VDD_GPU 20% 20% 20% 20% 20% 20%
AG17 VDD_CPU VDD_GPU AG34 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
0204 0204 0204 0204 0204 0204
AG20 VDD_CPU AH25
CPU0-2 AND CPUB)

VDD_GPU X5R X5R X5R X5R X5R X5R
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL AG22 VDD_CPU AH29
C1420 C1421 C1422 C1423 C1424 C1425 C1426 VDD_GPU
VDD_CPU
1UF 1UF 1UF 1UF 1UF 1UF 1UF AG8 VDD_GPU AH31
20% 20% 20% 20% 20% 20% 20% AH11 VDD_CPU AJ26
4V 4V 4V 4V 4V 4V 4V VDD_CPU VDD_GPU
CERM CERM CERM CERM CERM CERM CERM
GPU LOGIC)
0402 0402 0402 0402 0402 0402 0402 AB9 VDD_GPU AJ28 1 C1490 1 C1491 1 C1492 1 C1493 1 C1495 1 C1496
1 3 1 3 1 3 1 3 1 3 1 3 1 3 AH13 VDD_CPU
VDD_CPU VDD_GPU AA34 0.22UF 0.22UF 0.22UF 0.22UF 100PF 56PF
20% 20% 20% 20% 5% 5%
AH15 VDD_GPU AJ32 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2
16V 6.3V
2 NP0-C0G
2 4 2 4 2 4 2 4 2 4 2 4 2 4 AH17 VDD_CPU AJ34 01005-1 01005-1 01005-1 01005-1 01005 01005
VDD_GPU NP0-C0G
X5R X5R X5R X5R
AH19 VDD_CPU VDD_GPU AK25
AH21 VDD_CPU AK29
13.4A MAX,
VDD_GPU
8.0A MAX,
AH9 VDD_CPU VDD_GPU AK31
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL AJ10 VDD_CPU N28
C1430 C1431 C1432 C1433 C1434 C1435 C1436 VDD_GPU
1UF 1UF 1UF 1UF 1UF 1UF 1UF AJ12 VDD_CPU VDD_GPU N32
20% 20% 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V 4V 4V AJ14 VDD_CPU VDD_GPU P25
C CERM
0402
1 3
CERM
0402
1 3
CERM
0402
1 3
CERM
0402
1 3
CERM
0402
1 3
CERM
0402
1 3
CERM
0402
1 3
AJ16 VDD_CPU VDD_GPU
VDD_GPU
P29 C
AC12 VDD_CPU AB25
0.775V - 1.05V,
0.80V - 1.05V,
AJ18 VDD_CPU VDD_GPU P31
2 4 2 4 2 4 2 4 2 4 2 4 2 4 AJ20 VDD_CPU VDD_GPU R26
AJ22 VDD_CPU VDD_GPU R28
VDD_GPU
AJ8 VDD_CPU R32
AK11 VDD_CPU VDD_GPU R34
CRITICAL CRITICAL VDD_GPU
AK13 VDD_CPU T25
C1437 C1438 C1439 1
1UF 1UF AK15 VDD_CPU VDD_GPU T29
20% 20% 220PF
4V 4V 10% AK17 VDD_CPU VDD_GPU T31
(VDD_GPU
(VDD_CPU
CERM CERM 10V
X7R-CERM 2 AK19 VDD_CPU U26
0402 0402 01005 VDD_GPU
1 3 1 3 AK21 VDD_CPU VDD_GPU U28
AC14 VDD_CPU VDD_GPU AB29
2 4 2 4 AK9 VDD_CPU U32
VDD_GPU
AL12 VDD_CPU VDD_GPU U34
AL16 VDD_CPU VDD_GPU V25
AL8 VDD_CPU VDD_GPU W26
AC16 VDD_CPU VDD_GPU W28
AC8 VDD_CPU VDD_GPU W32
AD11 VDD_CPU VDD_GPU W34
AD13 VDD_CPU VDD_GPU Y25
VOLTAGE=1.1V
70 62 PPVDD_CPU_SOC_SENSE AB13 VDD_CPU_SENSE VDD_GPU AB31
VDD_GPU Y29
VDD_GPU Y31
B VDD_GPU
VDD_GPU
AC26
AC28
B
VDD_GPU AC32
VOLTAGE=1.1V
VDD_GPU_SENSE N26 PPVDD_GPU_SOC_SENSE 62 70
CPU AND GPU SRAM)

VDD_SRAM AG30
VDD_SRAM AH27
VDD_SRAM AH33
VOLTAGE=3.3V
70 62 PPVDD_SRAM_SOC_SENSE N25 VDD_SRAM_SENSE VDD_SRAM AJ15
72 =PPVDD_SRAM AA24 VDD_SRAM VDD_SRAM AJ24
CRITICAL CRITICAL CRITICAL CRITICAL AA30 VDD_SRAM VDD_SRAM AJ30
C1451 C1452 C1453 C1454 AB27 AK10
7.5UF 7.5UF 4.3UF 4.3UF VDD_SRAM VDD_SRAM
20% 20% 20% 20% AB33 VDD_SRAM VDD_SRAM AK14
4V 4V 4V 4V
CERM CERM CERM CERM AC10 VDD_SRAM VDD_SRAM AK20
0402 0402 0402 0402
3.4A MAX,
1 3 1 3 1 3 1 3 AC15 VDD_SRAM VDD_SRAM AK27
AC24 VDD_SRAM VDD_SRAM AK33
2 4 2 4 2 4 2 4 AC30 VDD_SRAM VDD_SRAM AL15
AD14 VDD_SRAM VDD_SRAM N24
AD27 VDD_SRAM VDD_SRAM N30
CRITICAL CRITICAL AD33 VDD_SRAM VDD_SRAM P27
0.95V - 1.05V,
C1455 C1456 AE15 P33
1UF 1UF VDD_SRAM VDD_SRAM
20% 20% AE24 VDD_SRAM VDD_SRAM R24
4V 4V
CERM CERM AE30 VDD_SRAM VDD_SRAM R30
0402 0402
1 3 1 3 AF11 VDD_SRAM VDD_SRAM T27
AF27 VDD_SRAM VDD_SRAM T33
2 4 2 4 AF33 VDD_SRAM VDD_SRAM U24
A AG11
AG13
VDD_SRAM
VDD_SRAM
VDD_SRAM U30
V27 SYNC_MASTER=N/A SYNC_DATE=N/A A
(VDD_SRAM
VDD_SRAM
VDD_SRAM PAGE TITLE
AG15 VDD_SRAM V33
CRITICAL AG16 VDD_SRAM VDD_SRAM W24 SOC: CPU, GPU, SRAM POWER
1 C1457 1 C1459 AG19 VDD_SRAM VDD_SRAM W30 DRAWING NUMBER SIZE
1.0UF
20% 5%
100PF AG24 VDD_SRAM VDD_SRAM Y27
VDD_SRAM REVISION
2 6.3V 2 16V Y33
R
0201-1 01005
NP0-C0G BRANCH
B.0.0
X5R
TABLE_ALT_HEAD NOTICE OF PROPRIETARY PROPERTY:
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: THE INFORMATION CONTAINED HEREIN IS THE
PART NUMBER PROPRIETARY PROPERTY OF APPLE INC.
TABLE_ALT_ITEM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
138S00006 138S0835 ? C1410, ECT RDAR://PROBLEM/16040051 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
14 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
70 10 IN DDR1_CA<0> H18 DDR0_CA[0] OMIT_TABLE DDR1_CA[0] V17 DDR0_CA<0> IN 10 70
H19 W17 72 15 14 =PP1V2_DDR_VDDQ
70 10 IN DDR1_CA<1> DDR0_CA[1] U1600 DDR1_CA[1] DDR0_CA<1> IN 10 70
70 10 DDR1_CA<2> J18 DDR0_CA[2] BGA-1 DDR1_CA[2] V16 DDR0_CA<2> 10 70

IN IN
DRAM CRITICAL CRITICAL CRITICAL CRITICAL
70 10 IN DDR1_CA<3> J19 DDR0_CA[3] DDR1_CA[3] W16 DDR0_CA<3> IN 10 70
DDR1_CA<4> K19 (1 OF 3) W15 DDR0_CA<4> C1600 1 C1601 1 C1602 1 C1603 1 C1605 1 C1606 1 C1607 1 C1608 1
DDR0_CA[4] DDR1_CA[4] 15UF 15UF 4.3UF 4.3UF 1.0UF 1.0UF 1.0UF 1.0UF
CAPRI-DRAM
70 10 IN IN 10 70
70 10 IN DDR1_CA<5> R18 DDR0_CA[5] DDR1_CA[5] V10 DDR0_CA<5> IN 10 70

10 70
20%
4V
20%
4V
20%
4V 2
20%
4V 2
20%
6.3V 2
20%
6.3V 2
20%
6.3V 2
20%
6.3V 2
CERM 2 CERM 2 X5R-CERM X5R-CERM X5R X5R X5R X5R
70 10 IN DDR1_CA<6> R19 DDR0_CA[6] DDR1_CA[6] W10 DDR0_CA<6> IN
0402 0402 0610 0610 0201-1 0201-1 0201-1 0201-1
70 10 IN DDR1_CA<7> T19 DDR0_CA[7] DDR1_CA[7] W9 DDR0_CA<7> IN
10 70
70 10 IN DDR1_CA<8> T20 DDR0_CA[8] DDR1_CA[8] Y9 DDR0_CA<8> IN 10 70
70 10 IN DDR1_CA<9> U18 DDR0_CA[9] DDR1_CA[9] V8 DDR0_CA<9> IN 10 70
D 70 10 IN DDR1_CK_P M19 DDR0_CK DDR1_CK W13 DDR0_CK_P IN 10 70

D
70 10 IN DDR1_CK_N N19 DDR0_CKB DDR1_CKB W12 DDR0_CK_N IN 10 70
C1609 1 C1610 1 C1611 1 C1615 1 C1616 1 C1619 1
70 10 IN DDR1_CKE<0> L19 DDR0_CKE[0] DDR1_CKE[0] W14 DDR0_CKE<0> IN 10 70 100PF 0.47UF 0.47UF 0.1UF 0.1UF 100PF
5% 20% 20% 20% 20% 5%
NC_DRAM_DDR1_CKE<1> L18 DDR0_CKE[1] DDR1_CKE[1] V14 NC_DRAM_DDR0_CKE<1> 25V 4V
CERM-X5R-1 4V
CERM-X5R-1 6.3V
X5R-CERM 6.3V
X5R-CERM 16V
NO_TEST=TRUE NO_TEST=TRUE C0G 2 201
2
201
2
01005
2
01005
2
01005
2
0201
SEG: OK TO FLOAT CKE AND CS PINS SEG: OK TO FLOAT CKE AND CS PINS NP0-C0G
70 10 IN DDR1_CSN<0> DDR0_CS[0] DDR1_CS[0] DDR0_CSN<0> IN 10 70
NC_DDR1_CS<1> NO_TEST=TRUE L20 DDR0_CS[1] DDR1_CS[1]

Y14 NC_DDR0_CS<1> NO_TEST=TRUE
K20 Y15
70 10 IN DDR1_DM<0> DDR0_DM[0] DDR1_DM[0] DDR0_DM<0> IN 10 70
DDR1_DM<1> L3 C14 DDR0_DM<1>

70 10 IN DDR0_DM[1] DDR1_DM[1] IN 10 70 POR CAPS 6/11/2013
DDR1_DM<2> N2 B12 DDR0_DM<2>
70 10 IN DDR0_DM[2] DDR1_DM[2] IN 10 70
DDR1_DM<3> G2 B18 DDR0_DM<3>

70 10 IN DDR0_DM[3] DDR1_DM[3] IN 10 70
T4 D9 72 15 =PP1V8_S2R_DDR AA19 OMIT_TABLE A10
70 A1 OMIT_TABLE F20
0
1 DDR1_DQ<0> DDR0_DQ<0> B13 U1600 A12
BI DDR0_DQ[0] DDR1_DQ[0] BI 10 70
CRITICAL A18 U1600 F21
H3 C17 1 1 1 1 1 C2 CAPRI-DRAM A15
BI DDR1_DQ<1> DDR0_DQ[1] DDR1_DQ[1]
D17
DDR0_DQ<1> BI 10 70 C1620 C1625 C1626 C1628 C1629 BGA-1
A2 CAPRI-DRAM G1
DDR1_DQ<2> H4
J2 B16 DDR0_DQ<2> 15UF 1UF 1UF 1.0UF 1.0UF C3 A16
20% 10% 10% 20% 20% DRAM A20 BGA-1 G18
J3 C16 4V 6.3V 6.3V 6.3V 6.3V G19 A19 DRAM
BI DDR1_DQ<3> DDR0_DQ[3] DDR1_DQ[3] DDR0_DQ<3> BI 10 70
CERM
0402
2
402
2 CERM
402
2 X5R 2
0201-1 X5R 2 (2 OF 3) A21 G20
J4 D16 0201-1 M2 B14 (3 OF 3)
BI DDR1_DQ<4> DDR0_DQ[4] DDR1_DQ[4] DDR0_DQ<4> BI
10 70
CERM A3 G21
J5 E16 P18 VDD1 C19
BI DDR1_DQ<5> DDR0_DQ[5] DDR1_DQ[5] DDR0_DQ<5> BI 10 70 A4 H2
DDR1_DQ<6> K2 B15 DDR0_DQ<6> V11 C21
BI DDR0_DQ[6] DDR1_DQ[6] BI 10 70 A5 J20
70 10 DDR1_DQ<7> K3 C15 DDR0_DQ<7> W20 D4
BI DDR0_DQ[7] DDR1_DQ[7] BI 10 70 A6 K5
DDR1_DQ<8> P3 C11 DDR0_DQ<8> W21 D6
70 10 BI DDR0_DQ[8] DDR1_DQ[8] BI 10 70 A8 L5
DDR1_DQ<9> P4 D11 DDR0_DQ<9> 10 70 C1634 1 C1635 1 C1636 1 C1639 1
Y19 E12
BI DDR0_DQ[9] DDR1_DQ[9] BI 100PF 0.1UF 0.1UF 100PF VDDQ AA1 M20
DDR1_DQ<10> R2 B10 DDR0_DQ<10> 5% 20% 20% 5% Y5 E17
DDR0_DQ[10] DDR1_DQ[10] AA2 M3
DDR0
DDR1
BI BI 10 70
25V 6.3V 6.3V
X5R-CERM 16V
DDR1_DQ<11> R3 C10 DDR0_DQ<11> C0G 2
0201 01005
2 2 NP0-C0G 2 Y6 F1
BI DDR0_DQ[11] DDR1_DQ[11] BI 10 70 01005 01005 AA3 N20
C BI DDR1_DQ<12>
DDR1_DQ<13>
R4
R5
DDR0_DQ[12]
DDR0_DQ[13]
DDR1_DQ[12]
DDR1_DQ[13]
D10
E10
DDR0_DQ<12>
DDR0_DQ<13>
BI 10 70
X5R-CERM
AA18
F3
H5
AA6 P2 C
BI BI 10 70 AA7 R20
T2 B9 AA20 J1
BI DDR1_DQ<14> DDR0_DQ[14] DDR1_DQ[14] DDR0_DQ<14> BI 10 70 B1 T5
72 15 14 =PP1V2_S2R_DDR AA21 K1
BI DDR1_DQ<15> T3 DDR0_DQ[15] DDR1_DQ[15] C9 DDR0_DQ<15> BI
10 70 B11 U1
DDR1_DQ<16> E2 B20 DDR0_DQ<16> CRITICAL CRITICAL CRITICAL AA4 L2
C1646 1 B17 VSS VSS U20
DDR1_DQ<17> E3 C20 DDR0_DQ<17> 10 70 C1640 1 C1642 1 C1643 1 C1645 1
AA5 N1
BI DDR0_DQ[17] DDR1_DQ[17] BI 15UF 4.3UF 4.3UF 1UF 1UF B2 V18
DDR1_DQ<18> E4 D20 DDR0_DQ<18> 20% 20% 20% 10% 10% B3 N5
4V 4V 4V 6.3V 6.3V
2 B21 V19
CERM 2 X5R-CERM 2 2 CERM 2 CERM
402 B4 R1
DDR1_DQ<19> E5 DDR0_DQ[19] DDR1_DQ[19] E20 DDR0_DQ<19> 10 70 0402 0610 0610 402 C1 V5
BI BI
F2 B19 X5R-CERM E13 W4
BI DDR1_DQ<20> DDR0_DQ[20] DDR1_DQ[20] DDR0_DQ<20> BI 10 70 C13 V6
E21
BI DDR1_DQ<21> F4 DDR0_DQ[21] DDR1_DQ[21] D19 DDR0_DQ<21> BI 10 70
10 70 C4 V7
F5 E19 M5
BI DDR1_DQ<22> DDR0_DQ[22] DDR1_DQ[22] DDR0_DQ<22> BI VDD2 D1 W1
DDR1_DQ<23> G5 E18 DDR0_DQ<23> P20
BI DDR0_DQ[23] DDR1_DQ[23] BI 10 70 D2 W18
DDR1_DQ<24> U2 B8 DDR0_DQ<24> V20
BI DDR0_DQ[24] DDR1_DQ[24] BI 10 70 C1648 1 C1649 1 C1655 1 C1656 1 C1659 1 D21 W5
DDR1_DQ<25> V2 B7 DDR0_DQ<25> V21
BI DDR0_DQ[25] DDR1_DQ[25] BI 10 70 1.0UF 1.0UF 0.1UF 0.1UF 100PF D3 W6
20% 20% 20% 20% 5% W19
DDR1_DQ<26> V3 DDR0_DQ[26] DDR1_DQ[26] C7 DDR0_DQ<26> 10 70 6.3V 6.3V 6.3V
X5R-CERM 6.3V
X5R-CERM 16V D5 W7
BI BI 10 70 X5R 2 X5R 2 2 2 NP0-C0G 2
V4 D7 0201-1 0201-1 01005 01005 01005 Y11
BI DDR1_DQ<27> DDR0_DQ[27] DDR1_DQ[27] DDR0_DQ<27> BI E1 Y1
W2 B6 Y18
BI DDR1_DQ<28> DDR0_DQ[28] DDR1_DQ[28] DDR0_DQ<28> BI 10 70 E14 Y10
Y20
BI DDR1_DQ<29> W3 DDR0_DQ[29] DDR1_DQ[29] C6 DDR0_DQ<29> BI 10 70 E15 Y12
DDR1_DQ<30> Y3 B5 DDR0_DQ<30> Y21
BI DDR0_DQ[30] DDR1_DQ[30] BI 10 70 E6 Y13
BI DDR1_DQ<31> Y4 DDR0_DQ[31] DDR1_DQ[31] C5 DDR0_DQ<31> BI 10 70 E7 Y16
72 15 14 =PP1V2_S2R_DDR H20
E9 Y2
K4 DDR0_PDQS[0] K18
BI DDR1_DQS_P<0> DDR1_PDQS[0] D15 DDR0_DQS_P<0> BI 10 70 CRITICAL F18 Y7
70 10 BI DDR1_DQS_N<0> L4 DDR0_NDQS[0] DDR1_NDQS[0] D14 DDR0_DQS_N<0> BI 10 70
C1660 1 C1665 1 C1666 1 C1668 1 C1669 1 M18
F19 Y8
15UF 1UF 1UF 1.0UF 1.0UF N18
20% 10% 10% 20% 20%
N4 D12 4V 6.3V 6.3V 6.3V 6.3V T18
70 10 BI DDR1_DQS_P<1> DDR0_PDQS[1] DDR1_PDQS[1] DDR0_DQS_P<1> BI 10 70 CERM 2
0402 402
2
402
2 X5R 2
0201-1 X5R 2
0201-1
N3 C12 V12 VDDCA
70 10 BI DDR1_DQS_N<1> DDR0_NDQS[1] DDR1_NDQS[1] DDR0_DQS_N<1> BI 10 70 CERM CERM
V13
B 70 10 BI DDR1_DQS_P<2>
G3
G4 DDR0_PDQS[2]
C18
DDR1_PDQS[2] D18 DDR0_DQS_P<2> BI 10 70
V15 B
DDR1_DQS_N<2> DDR0_DQS_N<2> V9
70 10 BI DDR0_NDQS[2] DDR1_NDQS[2] BI 10 70
Y17
U4 D8
70 10 BI DDR1_DQS_P<3> U3 DDR0_PDQS[3] DDR1_PDQS[3] C8 DDR0_DQS_P<3> BI 10 70 C1674 1 C1675 1 C1676 1 C1679 1
DDR1_DQS_N<3> DDR0_DQS_N<3> 100PF 0.1UF 0.1UF 100PF

5% 20% 20% 5%
P19 25V 6.3V 6.3V 16V
W11 X5R-CERM X5R-CERM NP0-C0G 2
C0G 2
0201 01005
2
01005
2 01005
14 PPVREF_DDR1_CA_DRAM M4 DDR0_VREF_CA DDR1_VREF_CA D13 PPVREF_DDR0_CA_DRAM 14
14 PPVREF_DDR1_DQ_DRAM DDR0_VREF_DQ DDR1_VREF_DQ PPVREF_DDR0_DQ_DRAM 14

U19 W8
DDR1_ZQ_DRAM DDR0_ZQ DDR1_ZQ DDR0_ZQ_DRAM
1 1
R1698 R1699
240 DDR0 AND DDR1 WERE SWAPPED INTENTIONALLY FOR ROUTING 240
1% 1%
1/32W 1/32W
MF
01005 01005
2 2 MF
72 15 14 =PP1V2_S2R_DDR
72 15 14 =PP1V2_DDR_VDDQ
1 1
1
R1690 1
R1692 R1694 R1696
10K
1 C1694 10K
1 C1696
4.7K 1 C1690 4.7K 1 C1692 1% 0.1UF 1% 0.1UF
1% 0.1UF 1% 0.1UF 1/32W 20% 1/32W 20%
A 1/32W
MF
2 01005
20%
6.3V
2 X5R-CERM
01005
1/32W
MF
2 01005
2
20%
6.3V
01005
2
MF
01005 2
6.3V
01005
X5R-CERM
MF
2 01005
2
6.3V
01005
X5R-CERM
SYNC_MASTER=N/A SYNC_DATE=N/A A
X5R-CERM PAGE TITLE
VOLTAGE=0.6V
PPVREF_DDR1_CA_DRAM 14
VOLTAGE=0.6V
DDR: CHANNEL 0 AND 1
PPVREF_DDR1_DQ_DRAM 14 PPVREF_DDR0_DQ_DRAM 14
DRAWING NUMBER SIZE
1 1
1
R1695 1 C1695
1
R1697 1 C1697 Apple Inc. 051-0301
REVISION
D
R1691 1 C1691 R1693 1 C1693 10K 0.1UF 10K 0.1UF
4.7K 0.1UF 4.7K 0.1UF 1% 20% R
1% 20% 20%
1%
1/32W 2
20%
6.3V 1/32W
MF 2
6.3V
01005
BRANCH B.0.0
1/32W
01005 2 6.3V 01005 2 6.3V 01005 01005
2 01005 X5R-CERM NOTICE OF PROPRIETARY PROPERTY:
01005 01005 2 MF X5R-CERM
2 MF X5R-CERM 2 MF X5R-CERM THE INFORMATION CONTAINED HEREIN IS THE
1%
PAGE16 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
70 10 IN DDR3_CA<0> H18 DDR0_CA[0] OMIT_TABLE DDR1_CA[0] V17 DDR2_CA<0> IN 10 70 =PP1V2_DDR_VDDQ
72 15 14
70 10 IN DDR3_CA<1> H19 DDR0_CA[1] U1700 DDR1_CA[1] W17 DDR2_CA<1> IN 10 70
70 10 DDR3_CA<2> J18 DDR0_CA[2] BGA-1 DDR1_CA[2] V16 DDR2_CA<2> 10 70

IN IN
DRAM CRITICAL CRITICAL CRITICAL CRITICAL
70 10 IN DDR3_CA<3> J19 DDR0_CA[3] DDR1_CA[3] W16 DDR2_CA<3> IN 10 70
DDR3_CA<4> K19 (1 OF 3) W15 DDR2_CA<4> C1700 1 C1701 1 C1702 1 C1703 1 C1705 1 C1706 1 C1707 1 C1708 1
DDR0_CA[4] DDR1_CA[4] 15UF 15UF 4.3UF 4.3UF 1.0UF 1.0UF 1.0UF 1.0UF
CAPRI-DRAM
70 10 IN IN 10 70
70 10 IN DDR3_CA<5> R18 DDR0_CA[5] DDR1_CA[5] V10 DDR2_CA<5> IN 10 70

10 70
20%
4V
20%
4V
20%
4V 2
20%
4V 2
20%
6.3V 2
20%
6.3V 2
20%
6.3V 2
20%
6.3V 2
DDR3_CA<6> R19 W10 DDR2_CA<6> CERM 2 CERM 2 0610 0610 X5R
0201-1 X5R
0201-1 X5R
0201-1 X5R
0201-1
70 10 IN DDR0_CA[6] DDR1_CA[6] IN 0402 0402
X5R-CERM X5R-CERM
70 10 IN DDR3_CA<7> T19 DDR0_CA[7] DDR1_CA[7] W9 DDR2_CA<7> IN
10 70
70 10 IN DDR3_CA<8> T20 DDR0_CA[8] DDR1_CA[8] Y9 DDR2_CA<8> IN 10 70
70 10 IN DDR3_CA<9> U18 DDR0_CA[9] DDR1_CA[9] V8 DDR2_CA<9> IN 10 70
D 70 10 IN DDR3_CK_P M19 DDR0_CK DDR1_CK W13 DDR2_CK_P IN 10 70

D
70 10 IN DDR3_CK_N N19 DDR0_CKB DDR1_CKB W12 DDR2_CK_N IN 10 70
C1709 1 C1710 1 C1711 1 C1715 1 C1716 1 C1719 1
70 10 IN DDR3_CKE<0> L19 DDR0_CKE[0] DDR1_CKE[0] W14 DDR2_CKE<0> IN 10 70 220PF 0.47UF 0.47UF 0.1UF 0.1UF 100PF
10% 20% 20% 20% 20% 5%
NC_DRAM_DDR3_CKE<1> L18 DDR0_CKE[1] DDR1_CKE[1] V14 NC_DRAM_DDR2_CKE<1> 10V 4V
CERM-X5R-1 4V 6.3V 6.3V 16V
NO_TEST=TRUE NO_TEST=TRUE X7R-CERM 2 201
2
201
2
01005
2
01005
2 NP0-C0G 2
01005 01005
SEG: OK TO FLOAT CKE AND CS PINS SEG: OK TO FLOAT CKE AND CS PINS CERM-X5R-1 X5R-CERM X5R-CERM
70 10 IN DDR3_CSN<0> DDR0_CS[0] DDR1_CS[0] DDR2_CSN<0> IN 10 70
NC_DDR3_CS<1> NO_TEST=TRUE L20 Y14 NC_DDR2_CS<1> NO_TEST=TRUE

DDR0_CS[1] DDR1_CS[1]
K20 Y15
70 10 IN DDR3_DM<0> DDR0_DM[0] DDR1_DM[0] DDR2_DM<0> IN 10 70
DDR3_DM<1> L3 C14 DDR2_DM<1>

70 10 IN DDR0_DM[1] DDR1_DM[1] IN 10 70
DDR3_DM<2> N2 B12 DDR2_DM<2>

70 10 IN DDR0_DM[2] DDR1_DM[2] IN 10 70
DDR3_DM<3> G2 B18 DDR2_DM<3>

70 10 IN DDR0_DM[3] DDR1_DM[3] IN 10 70
T4 D9 72 14 =PP1V8_S2R_DDR AA19 OMIT_TABLE A10 A1 OMIT_TABLE F20
70
0 B13 U1700 A12 A18 F21
1
C17
DDR2_DQ<0> BI 10 70
CRITICAL U1700
H3 1 1 1 1 1 C2 CAPRI-DRAM A15 A2 G1
D17
DDR2_DQ<1> BI 10 70 C1720 C1725 C1726 C1728 C1729 BGA-1
CAPRI-DRAM
DDR3_DQ<2> H4
J2 B16 DDR2_DQ<2> 15UF 1UF 1UF 1.0UF 1.0UF C3 A16 A20 BGA-1 G18
20% 10% 10% 20% 20% DRAM
J3 C16 4V 6.3V 6.3V 6.3V 6.3V G19 A19 A21 DRAM G20
BI DDR3_DQ<3> DDR0_DQ[3] DDR1_DQ[3] DDR2_DQ<3> BI 10 70 CERM 2 CERM 2 CERM 2 X5R 2
0201-1 X5R 2
0201-1 (2 OF 3)
J4 D16 0402 402 402 M2 B14 A3 (3 OF 3) G21
BI DDR3_DQ<4> DDR0_DQ[4] DDR1_DQ[4] DDR2_DQ<4> BI
10 70
J5 E16 P18 VDD1 C19 A4 H2

DDR3_DQ<6> K2 B15 DDR2_DQ<6> V11 C21 A5 J20

70 10 DDR3_DQ<7> K3 C15 DDR2_DQ<7> W20 D4 A6 K5

DDR3_DQ<8> P3 C11 DDR2_DQ<8> W21 D6 A8 L5

70 10 BI DDR0_DQ[8] DDR1_DQ[8] BI 10 70
DDR3_DQ<9> P4 D11 DDR2_DQ<9> 10 70 C1734 1 C1735 1 C1736 1 C1739 1

Y19 E12 AA1 M20
BI DDR0_DQ[9] DDR1_DQ[9] BI 100PF 0.1UF 0.1UF 100PF VDDQ
DDR3_DQ<10> R2 B10 DDR2_DQ<10> 5% 20% 20% 5% Y5 E17 AA2 M3
DDR0_DQ[10] DDR1_DQ[10]
DDR0
DDR1
BI BI 10 70
25V 6.3V 6.3V
X5R-CERM 16V
DDR3_DQ<11> R3 C10 DDR2_DQ<11> C0G 2 01005
2 2 NP0-C0G 2 Y6 F1 AA3 N20
0201 01005 01005
C BI DDR3_DQ<12>
DDR3_DQ<13>
R4
R5
DDR0_DQ[12]
DDR0_DQ[13]
DDR1_DQ[12]
DDR1_DQ[13]
D10
E10
DDR2_DQ<12>
DDR2_DQ<13>
BI 10 70
10 70
X5R-CERM
AA18
F3
H5
AA6
AA7
P2
R20
C
BI BI
T2 B9 AA20 J1 B1 T5
72 15 14 =PP1V2_S2R_DDR AA21 K1
BI DDR3_DQ<15> T3 DDR0_DQ[15] DDR1_DQ[15] C9 DDR2_DQ<15> BI
10 70 B11 U1
DDR3_DQ<16> E2 B20 DDR2_DQ<16> CRITICAL CRITICAL CRITICAL AA4 L2 B17 VSS VSS U20
C1746 1
DDR3_DQ<17> E3 C20 DDR2_DQ<17> 10 70 C1740 1 C1742 1 C1743 1 C1745 1
AA5 N1 B2 V18
BI DDR0_DQ[17] DDR1_DQ[17] BI 15UF 4.3UF 4.3UF 1UF 1UF
DDR3_DQ<18> E4 D20 DDR2_DQ<18> 20% 20% 20% 10% 10% B3 N5 B21 V19
4V 4V 4V 6.3V 6.3V
2
CERM 2 X5R-CERM 2 X5R-CERM 2 CERM 2 402 B4 R1
DDR3_DQ<19> E5 DDR0_DQ[19] DDR1_DQ[19] E20 DDR2_DQ<19> 10 70 0610 0610 C1 V5
BI BI 0402 402 CERM
F2 B19 E13 W4 C13 V6
E21
BI DDR3_DQ<21> F4 DDR0_DQ[21] DDR1_DQ[21] D19 DDR2_DQ<21> BI 10 70
10 70
C4 V7
F5 E19 M5 D1 W1
BI DDR3_DQ<22> DDR0_DQ[22] DDR1_DQ[22] DDR2_DQ<22> BI VDD2
DDR3_DQ<23> G5 E18 DDR2_DQ<23> P20 D2 W18
DDR3_DQ<24> U2 B8 DDR2_DQ<24> V20 D21 W5

BI DDR0_DQ[24] DDR1_DQ[24] BI 10 70 C1748 1 C1749 1 C1755 1 C1756 1 C1759 1
DDR3_DQ<25> V2 B7 DDR2_DQ<25> V21 D3 W6
BI DDR0_DQ[25] DDR1_DQ[25] BI 10 70 1.0UF 1.0UF 0.1UF 0.1UF 100PF
20% 20% 20% 20% 5% W19
DDR3_DQ<26> V3 DDR0_DQ[26] DDR1_DQ[26] C7 DDR2_DQ<26> 10 70 6.3V 6.3V 6.3V 6.3V 16V D5 W7
BI BI 10 70 X5R 2 X5R 2 2 2 NP0-C0G 2
V4 D7 0201-1 0201-1 01005 01005 Y11 E1 Y1
BI DDR3_DQ<27> DDR0_DQ[27] DDR1_DQ[27] DDR2_DQ<27> BI X5R-CERM X5R-CERM
01005
W2 B6 Y18 E14 Y10
Y20
BI DDR3_DQ<29> W3 DDR0_DQ[29] DDR1_DQ[29] C6 DDR2_DQ<29> BI 10 70 E15 Y12
DDR3_DQ<30> Y3 B5 DDR2_DQ<30> Y21 E6 Y13
BI DDR3_DQ<31> Y4 DDR0_DQ[31] DDR1_DQ[31] C5 DDR2_DQ<31> BI 10 70

E7 Y16
72 15 14 =PP1V2_S2R_DDR H20 E9 Y2
K4 DDR0_PDQS[0] K18
BI DDR3_DQS_P<0> DDR1_PDQS[0] D15 DDR2_DQS_P<0> BI 10 70 CRITICAL F18 Y7
70 10 BI DDR3_DQS_N<0> L4 DDR0_NDQS[0] DDR1_NDQS[0] D14 DDR2_DQS_N<0> BI 10 70
C1760 1 C1765 1 C1766 1 C1768 1 C1769 1 M18 F19 Y8
15UF 1UF 1UF 1.0UF 1.0UF N18
20% 10% 10% 20% 20%
N4 D12 4V 6.3V 6.3V 6.3V 6.3V T18
70 10 BI DDR3_DQS_P<1> DDR0_PDQS[1] DDR1_PDQS[1] DDR2_DQS_P<1> BI 10 70 CERM 2 CERM 2 402
2 X5R 2
0201-1 X5R 2
0201-1
N3 C12 0402 402 V12 VDDCA
70 10 BI DDR3_DQS_N<1> DDR0_NDQS[1] DDR1_NDQS[1] DDR2_DQS_N<1> BI 10 70 CERM
V13
B 70 10 BI DDR3_DQS_P<2>
G3
G4 DDR0_PDQS[2]
C18
DDR1_PDQS[2] D18 DDR2_DQS_P<2> BI 10 70
V15 B
DDR3_DQS_N<2> DDR2_DQS_N<2> V9
Y17
U4 D8
70 10 BI DDR3_DQS_P<3> U3 DDR0_PDQS[3] DDR1_PDQS[3] C8 DDR2_DQS_P<3> BI 10 70 C1774 1 C1775 1 C1776 1 C1779 1
DDR3_DQS_N<3> DDR2_DQS_N<3> 100PF 0.1UF 0.1UF 100PF

5% 20% 20% 5%
P19 25V 6.3V 6.3V 16V
W11 2
C0G 2
0201 01005
2
01005
2 01005
15 PPVREF_DDR3_CA_DRAM M4 DDR0_VREF_CA DDR1_VREF_CA D13 PPVREF_DDR2_CA_DRAM 15 X5R-CERM X5R-CERM NP0-C0G
15 PPVREF_DDR3_DQ_DRAM DDR0_VREF_DQ DDR1_VREF_DQ PPVREF_DDR2_DQ_DRAM 15

U19 W8
DDR3_ZQ_DRAM DDR0_ZQ DDR1_ZQ DDR2_ZQ_DRAM
1 1
R1798 R1799
240 240
1% DDR2 AND DDR3 WERE SWAPPED INTENTIONALLY FOR ROUTING 1%
1/32W 1/32W
MF MF
01005
2 2 01005
72 15 14 =PP1V2_S2R_DDR
72 15 14 =PP1V2_DDR_VDDQ
1 1
1
R1790 1
R1792 R1794 R1796
10K
1 C1794 10K
1 C1796
4.7K 1 C1790 4.7K 1 C1792 1% 0.1UF 0.1UF
1% 0.1UF 0.1UF 1/32W 20% 20%
A 2
1/32W
MF
01005 2
20%
6.3V
01005
01005
2 MF
20%
6.3V
2 X5R-CERM
01005
2
MF
01005 2
6.3V
01005
X5R-CERM
01005
2 MF
6.3V
2 X5R-CERM
01005 SYNC_MASTER=N/A SYNC_DATE=N/A A
1/32W PAGE TITLE
X5R-CERM 1/32W
VOLTAGE=0.6V
1%
VOLTAGE=0.6V
VOLTAGE=0.6V
1%
VOLTAGE=0.6V
DDR: CHANNEL 2 AND 3
PPVREF_DDR3_DQ_DRAM 15 PPVREF_DDR2_DQ_DRAM 15
DRAWING NUMBER SIZE
1 1
1
R1795 1 C1795
1
R1797 1 C1797 Apple Inc. 051-0301
REVISION
D
R1791 1 C1791 R1793 1 C1793 10K 0.1UF 10K 0.1UF
4.7K 0.1UF 4.7K 0.1UF 1% 20% R
1% 20% 1% 20%
1%
1/32W
20%
6.3V
2 X5R-CERM
6.3V
2 X5R-CERM
01005
BRANCH B.0.0
1/32W
MF 2 6.3V
X5R-CERM 1/32W
MF 2 6.3V
X5R-CERM MF 01005 01005 NOTICE OF PROPRIETARY PROPERTY:
01005 01005 2 01005 2
MF
2 01005 2 01005 THE INFORMATION CONTAINED HEREIN IS THE
PAGE17 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
72 =PP3V3_NAND =PP1V8_NAND 16 70 72
1 C1800 1 C1801 1 C1802 1 C1840 1 C1841 1 C1842 1 C1810 1 C1811 1 C1812 1 C1813 1 C1814 1 C1815
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
0402-2 0402-2 0402-2 0402-2 0402-2 0402-2 0402-2 0402-2 0402-2 0402-2 0402-2 0402-2
1 C1804 1 C1805 1 C1806 1 C1807 1 C1808 1 1 1 1 1 1

1.0UF 1.0UF 1.0UF 100PF 100PF
C1820 C1821 C1822 C1823 C1824 C1825
20% 20% 20% 5% 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF 1.0UF
20% 20% 20% 20% 20% 20%
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2
16V
2 NP0-C0G 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
0201-1 0201-1 0201-1 01005 X5R X5R X5R X5R X5R X5R
5% 0201-1 0201-1 0201-1 0201-1 0201-1 0201-1
16V
NP0-C0G
01005
PPVDDI_NAND
VOLTAGE=1.2V
1 C1852 1 C1851 1 C1850

27PF 1.0UF 1.0UF 1 C1830 1 C1831
5% 20% 20% 100PF 100PF
2 16V 2 6.3V 2 6.3V
C NP0-C0G
01005
X5R
0201-1
X5R
0201-1
5%
16V
2 NP0-C0G
01005
5%
16V
2 NP0-C0G
01005
C
OB8
OC8
OD8
OE0
OF8
OA8
B6
F2
M6
N1
N7
G0
VDDI
VCC VCCQ
=PP1V8_NAND 16 70 72
70 7 BI ANC0_AD<0> G3 IO0-0 OMIT_TABLE
CE0* A5 ANC0_CE0_L IN 7 69 70
70 7 ANC0_AD<1> H2 IO1-0 U1800
BI A3 ANC0_CLE
J3 THGBX3T0DBKLA0B CLE0 IN 7 70
70 7 BI ANC0_AD<2> IO2-0 C1
ALE0 ANC0_ALE IN 7 70
70 7 BI ANC0_AD<3> K2 IO3-0 LGA E3 NOSTUFF NOSTUFF
WE0* ANC0_WE_L IN 7 70 1 1
ANC0_AD<4> L5 R1856 R1855
NAND-1YNM-128GX8-MLC-PPN1.5-64G
70 7 BI IO4-0
70 7 ANC0_AD<5> K6 IO5-0 100K 100K
BI
J5 RE0 B4 NC ANC0_RE_L
5% 5%
70 7 BI ANC0_AD<6> IO6-0 1/32W
MF
1/32W
MF
H6 RE0* C7 IN 7 70
70 7 BI ANC0_AD<7> IO7-0 2 01005 2 01005
ANC0_DQS
G1 DQS0 H4 IN
70 7 BI ANC1_AD<0> IO0-1 DQS0* F4 7 70
7 BI ANC1_AD<1> J1 IO1-1 NC
7 BI ANC1_AD<2> L1 IO2-1
N3 IO3-1 RY/BY0* E5 70 NAND_SLOT0_RDYBSY_L
7 BI ANC1_AD<3>
7 BI ANC1_AD<4> N5 IO4-1
CE1* C5 ANC1_CE0_L IN 7 69 70
7 BI ANC1_AD<5> L7 IO5-1 C3
J7 CLE1 ANC1_CLE IN 7 70
7 BI ANC1_AD<6> IO6-1 D2
G7 ALE1 ANC1_ALE IN 7 70
7 BI ANC1_AD<7> IO7-1 E1
WE1* ANC1_WE_L IN 7 70 =PP1V8_NAND 16 70 72
RE1 D4 NC ANC1_RE_L
RE1* D6 IN 7 70
B DQS1 M4
ANC1_DQS
IN
1
R1890 1 C1890
B
7 70
DQS1* K4 NC 10K 0.01UF
1% 10%
RY/BY1* E7 NAND_SLOT1_RDYBSY_L 1/32W
MF 2 6.3V
X5R
2 01005
01005
VOLTAGE=0.9V
VREF G5 70 PPVREF_ANC_NAND
70 TP_ANC_TCKC_NAND OA0 TCKC ZQ A1 ANC_ZQ_NAND
70 TP_ANC_TMSC_NAND OB0 TMSC
VSS VSSQ
1
R1854
B2
F6
L3
A7
M2
OC0
OD0
OE8
OF0
G8
243 1 1 C1891
1% R1891
1/32W 10K 0.01UF
MF 1% 10%
2 01005 1/32W 2 6.3V
X5R
RDAR://PROBLEM//16961728 MF 01005
2 01005
PAGE TITLE
NAND
DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
PAGE18 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_ALT_HEAD

PART NUMBER
OSCAR 155S00016 155S0686 FL2000 & MORE

TABLE_ALT_ITEM
D D
FL2000
OSCAR2
APN 337S4534 (A0) FL2001
120-OHM-25%-250MA-0.5DCR 120-OHM-25%-250MA-0.5DCR
17 =PP1V8_S2R_OSCAR 69 PP1V8_OSCAR_FILT PP1V2_OSCAR_FILT
72
1 2 69 1 2 =PP1V2_S2R_OSCAR 72
01005 01005
C2000 1 C2001 1
E12
D13
1.0UF 1.0UF
B2
C1
20% 20%
6.3V 2 6.3V 2
X5R X5R
0201-1
0201-1
VDDIO VDDC
CRITICAL
U2000
LPC18B1UK/CPA0-00
WLCSP
70 6 OUT UART_OSCAR2SOC_TX C11 U0_TXD/GPIO0[15] CLKOUT/GPIO0[0] F5 OSCAR_BIDIR_TIME_SYNC_HOST_IRQ BI 6
70 6 IN UART_SOC2OSCAR_TX A9 U0_RXD/GPIO0[16] GPIO0[7] E4 GPIO_GYRO2OSCAR_IRQ1 IN 18
GPIO_OSCAR2WLAN_CONTEXT_A E10 GPIO0[8] D3 GPIO_COMPASS2OSCAR_IRQ

GPIO_GYRO2OSCAR_IRQ2 IN 18
OUT U1_RXD/GPIO0[22] A13
C 18 OUT SPI_OSCAR2ACCEL_SCLK R2003 1 33
01005 5%
2 MF
1/32W
68
68
OUT
GPIO_OSCAR2WLAN_CONTEXT_B F11
U1_TXD/GPIO0[23]
NMI/GPIO0[24]
GPIO0[26] A3 GPIO_ACCEL2OSCAR_IRQ1
IN
IN
18
18
C
70 TP_OSCAR_P0_05 F1 U2_RXD/GPIO0[5] SWO/GPIO0[27] A11 GPIO_ACCEL2OSCAR_IRQ2 18
IN
18 OUT SPI_OSCAR2PHOS_SCLK R2002 1 33 2 MF 70 TP_OSCAR_P0_06 F3 U2_TXD/GPIO0[6] WDFLAG/GPIO1[2] D11 TP_OSCAR_P1_03
TP_OSCAR_P1_02 70
01005 5% 1/32W
UART_OSCAR2BB_TX D5
F9 U3_TXD/GPIO0[1] ALARM1/GPIO1[3] 70
18 OUT SPI_OSCAR2COMPASS_SCLK R2001 1 33 2 MF

71 68 IN
ALARM0/GPIO1[4] C3 GPIO_OSCAR2PMU_HOST_WAKE OUT 6 62
01005 5% 1/32W 71 68 UART_BB2OSCAR_TX F13 U3_RXDGPIO0[2]
PLACE_NEAR=U2000.A7:2MM OUT B10 SWD_OSCAR_IO_1V8
SWDIO/GPIO0[19] BI 9 70
18 OUT SPI_OSCAR2GYRO_SCLK R2000 1 33 2 MF SPI_SENSORS_SCLK A7 SPI0_SCK/GPIO0[12] SWCLK/GPIO0[20] B8 SWD_OSCAR_CLK_1V8 IN 9 70

01005 5% 1/32W
18 IN SPI_SENSORS_MISO A5 SPI0_MISO/GPIO0[13] CLK32K/GPIO0[21] E2 TP_OSCAR_P0_21 70
SPI_SENSORS_MOSI_R B6 SPI0_MOSI/GPIO0[14]
18 OUT SPI_SENSORS_MOSI R2020 1 33 2 MF
SPI_OSCAR2GYRO_CS_L D9 I2C0_SDAP/GPIO0[10] B12 I2C_OSCAR2PROX_SDA_1V8 BI 58 70
PROX ADDR: 0B0101000X
01005 5% 1/32W 18 OUT SPI0_SSEL0/GPIO0[3] HELIUM ADDR: 0B1110000X
B4 I2C0_SCL/GPIO0[11] A1 I2C_OSCAR2PROX_SCL_1V8 OUT 58 70
TEMP ADDR: 0B1110111X
18 OUT SPI_OSCAR2PHOS_CS_L
SPI_OSCAR2COMPASS_CS_L SPI0_SSEL1/GPIO0[18]
R2021 1 33 D7
18 OUT SPI_OSCAR2COMPASS_MOSI 2 MF 18 OUT SPI0_SSEL2/GPIO0[4] I2C1_SDA/GPIO0[9] E6 TP_OSCAR_P0_09 70
01005 5% 1/32W
18 OUT SPI_OSCAR2ACCEL_CS_L C5 SPI0_SSEL3/GPIO0[25] I2C1_SCL/GPIO0[17] E8 TP_OSCAR_P0_17 70
F7 RESET* I2C2_SDA/GPIO1[0] GPIO_PROX2OSCAR_IRQ_L 58

IN
C9 GPIO_OSCAR2COMPASS_TRIGGER
I2C2_SCL/GPIO1[1] OUT 18
C7
72 17 =PP1V8_S2R_OSCAR
VSS
1
R2010
D1
C13
100K
5%
1/32W
MF
2 01005
70 69 62 IN CLK_PMU2OSCAR_32K_AND_RESET_L
NOSTUFF
1 C2010
56PF
5%
6.3V
2 NP0-C0G
B 01005
B
PAGE TITLE
SENSOR: OSCAR
DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
PAGE 20 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SENSORS
D
FL2180
ACCEL D
120-OHM-25%-250MA-0.5DCR
VOLTAGE=1.8V
72 =PP1V8_S2R_ACCEL 1 2 PP1V8_ACCEL_FILT
GYRO
APN: 338S1192
01005
1 C2180
0.1UF
20%
1 C2181
0.1UF
20%
R2150 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0.00 2 VOLTAGE=3.0V 01005 01005
7
72 =PP3V0_S2R_GYRO 1 69 PP3V0_GYRO_FILT =PP1V8_S2R_GYRO 72
0% VDD VDDIO
1/32W
MF
C2150 1
C2155 1 1 C2157
01005 10UF
20% 0.22UF 0.22UF U2180
6.3V 20% 20% BMA282
CERM-X5R 2 6.3V 6.3V
0402-2 X5R 2 2 X5R LGA
01005-1 01005-1 CRITICAL
17 IN SPI_OSCAR2ACCEL_CS_L 4 CS* SCX 1 SPI_OSCAR2ACCEL_SCLK IN 17 PLACE_NEAR=U2180.3:2MM
CKPLUS_WAIVE=PWRTERM2GND
SDX 2 SPI_SENSORS_MOSI IN 17 18
R2180
3 33
SDO SPI_ACCEL_MISO_R 1 2 SPI_SENSORS_MISO
15
VDD 16
OUT 17 18
1
5%
RES/VDD VDD_IO 1/32W
MF
01005
GPIO_ACCEL2OSCAR_IRQ1 6 INT1 PS 13
U2150 17 OUT
AP3GDL20HAB18TR 17 OUT GPIO_ACCEL2OSCAR_IRQ2 5 INT2
LGA
CRITICAL GND
5 CS GNDIO
17 IN SPI_OSCAR2GYRO_CS_L SCL/SPC 2 SPI_OSCAR2GYRO_SCLK IN 17 PLACE_NEAR=U2150.4:2MM
6 DRDY/ SDA/SDI/SDO 3 R2151
9
11
12
14
10
17 OUT GPIO_GYRO2OSCAR_IRQ2 SPI_SENSORS_MOSI IN 17 18
8 INT2 33
DEN SDO/SA0 4 SPI_GYRO_MISO_R 1 2 SPI_SENSORS_MISO OUT 17 18
5%
GPIO_GYRO2OSCAR_IRQ1 1/32W
C 17 OUT
7 INT1 RES0 9
RES1 10
MF
01005 C
RES2 11
13 GND
12 GND
CAP 14 GYRO_CAP CAP APN: 132S0288

PLACE_NEAR=U2150.14:2MM
1 C2152
0.1UF
10%
16V
2 X5R-CERM
0201
PHOSPHORUS APN: 338S00044

FL2120
120-OHM-25%-250MA-0.5DCR
VOLTAGE=1.8V
72 =PP1V8_S2R_PHOS 1 2 69 PP1V8_PHOS_FILT
01005
1 C2120 1 C2125
0.1UF 1.0UF
20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R
0201-1
B 01005
B
6
VDD VDDIO
PLACE_NEAR=U2120.4:3MM U2120 R2122
R2121 BMP282BC
3 SDI 5 33
18 17 IN SPI_SENSORS_MOSI LGA SDO SPI_PHOS_MISO_R 1 2 SPI_SENSORS_MISO OUT 17 18
33 4 SCK
17 IN SPI_OSCAR2PHOS_SCLK 1 2 SPI_OSCAR2PHOS_SCLK_R CRITICAL
5%
1/32W
5% 17 SPI_OSCAR2PHOS_CS_L 2 CS* MF
1/32W IN 01005
GND
MF
01005
COMPASS
1
7
FL2140 APN: 338S1014 FL2141
120-OHM-25%-250MA-0.5DCR 120-OHM-25%-250MA-0.5DCR
72 =PP3V0_S2R_COMPASS PP3V0_COMPASS PP1V8_COMPASS =PP1V8_S2R_COMPASS
1 2 69 18 1 2 72
01005 01005
C2142 1 C2140 1 1 C2141
B1
C4
1.0UF 0.1UF 0.1UF

20% 20% 20%
6.3V 6.3V VDD VID 6.3V
X5R 2 X5R-CERM 2 2 X5R-CERM
0201-1 01005 01005
U2140
18 GND_COMPASS AK8963C GND_COMPASS 18
CSP
D1 CAD0 CRITICAL
SCL/SK A3 SPI_OSCAR2COMPASS_SCLK_R R2141 2 150 1 MF SPI_OSCAR2COMPASS_SCLK IN 17
01005 1% 1/32W
D2 CAD1 SDA/SI A4 SPI_OSCAR2COMPASS_MOSI IN 17
C2 TST1 CSB* A2 SPI_OSCAR2COMPASS_CS_L 17

NC IN
R2142 1 33
A NC
B3 RSV SO B4 SPI_COMPASS_MISO_R
01005 5%
2 MF
1/32W
SPI_SENSORS_MISO OUT 17 18
PAGE TITLE
17 IN GPIO_OSCAR2COMPASS_TRIGGER C3 TRG DRDY A1 GPIO_COMPASS2OSCAR_IRQ OUT 17
SENSOR: CARBON, PHOS+, MAGN
69 18 PP1V8_COMPASS D4 RST* DRAWING NUMBER SIZE
VSS
REVISION
C1
XW2140 R
VOLTAGE=0V SHORT-10L-0.25MM-SM
BRANCH
B.0.0
18 GND_COMPASS 1 2
SHEET
18 OF 73
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
HALL EFFECT
D D
C C
HALL EFFECT APN 353S3687
72 30 =PP3V0_S2R_HALL
C2260 1
0.22UF
20%
B1
6.3V 2
X5R
01005-1
PLACE_NEAR=U2260.B1:10MM VDD
U2260
BU52054GWZ
UCSP
CRITICAL OUT B2 GPIO_HALL2PMU_IRQ0 OUT 62 69
GND
A1
A2
B B
PAGE TITLE
SENSOR: HALL EFFECT

DRAWING NUMBER SIZE

REVISION
R
BRANCH
B.0.0
SHEET
19 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
FRONT & REAR CAMERA CONNECTORS

D D
FRONT CAMERA CONNECTOR REAR CAMERA CONNECTOR

CRITICAL CRITICAL
C MATCHES FRONT_CAM_FLEX_FGF 3.0.0 05/05/14
J2700
503548-1820
MLB APN: 516S0876
FLEX APN: 516S0869
J2701
AA07A-S026VA1 MLB APN: 516S0846
FLEX APN: 516S0750
C
F-ST-SM F-ST-SM
20 MATCHES REAR_CAM_FLEX 2.0.0 05/05/14
27 28
19
69 21 ISP_CAM_FRONT_CLK_F 1 2 69 21 IN ISP_CAM_REAR_CLK_F 1 2 MIPI_CAM_REAR_DATA_FILT_N<0> OUT 21 70

IN
69 21 ISP_CAM_FRONT_SCL_F 3 4 MIPI_CAM_FRONT_DATA_FILT_N<1> 21
3 4 MIPI_CAM_REAR_DATA_FILT_P<0> OUT 21 70
IN OUT
69 21 ISP_CAM_FRONT_SDA_F 5 6 MIPI_CAM_FRONT_DATA_FILT_P<1> 21
69 21 IN ISP_CAM_REAR_SHUTDOWN_L_F 5 6
BI OUT
7 8 69 21 BI ISP_CAM_REAR_SDA_F 7 8 MIPI_CAM_REAR_DATA_FILT_N<1> OUT 21 70
MIPI_CAM_REAR_DATA_FILT_P<1>
69 21 PP1V2_CAM_FRONT_FILT 9 10 MIPI_CAM_FRONT_CLK_FILT_N 21 70
69 21 IN ISP_CAM_REAR_SCL_F 9 10
OUT 21 70
OUT
69 21 PP1V8_CAM_FRONT_FILT 11 12 MIPI_CAM_FRONT_CLK_FILT_P 21 70
69 21 PP1V8_CAM_REAR_FILT 11 12
OUT
69 21 ISP_CAM_FRONT_SHUTDOWN_L_F 13 14 69 21 PP2V6_CAM_REAR_AF_FILT 13 14 MIPI_CAM_REAR_CLK_FILT_N OUT 21 70
IN
69 21 PP2V9_AVDD_CAM_FRONT_FILT 15 16 MIPI_CAM_FRONT_DATA_FILT_N<0> 21 70
15 16 MIPI_CAM_REAR_CLK_FILT_P OUT 21 70
OUT
17 18 MIPI_CAM_FRONT_DATA_FILT_P<0> 21 70
69 21 PP1V25_CAM_REAR_FILT 17 18
OUT
19 20 MIPI_CAM_REAR_DATA_FILT_N<2> OUT 21 70
21 70 21 OUT MIPI_CAM_REAR_DATA_FILT_N<3> 21 22 MIPI_CAM_REAR_DATA_FILT_P<2> OUT 21 70
22 70 21 OUT MIPI_CAM_REAR_DATA_FILT_P<3> 23 24
25 26 PP2V9_AVDD_CAM_REAR_FILT 21 69
29 30
B B
PAGE TITLE
CAMERA: CAM CONNS

DRAWING NUMBER SIZE

REVISION
R
BRANCH
B.0.0
SHEET
20 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_5_HEAD

TABLE_5_ITEM
FRONT CAMERA SUPPORT

155S00018 7 FERRITE,80OHM,25%,500MA,0.18DCR FL2800,FL2802,FL2803,FL2861,FL2871,FL2881,FL2891 CRITICAL
TABLE_5_ITEM
155S0667 8 COMMON MODE CHOKE,90OHM,100MA L2810,L2811,L2812,L2852,L2853,L2854,L2855,L2856 CRITICAL
TABLE_ALT_HEAD

OMIT_TABLE PART NUMBER
FL2802 L2810 155S0885 155S0610 ? FL2860, ECT RDAR://PROBLEM/128S0271

TABLE_ALT_ITEM
80-OHM-25%-500MA 2 OMIT_TABLE 3
VOLTAGE=1.8V 70 20 IN MIPI_CAM_FRONT_CLK_FILT_P MIPI_CAM_FRONT_CLK_P OUT 8 70
=PP1V8_CAM_FRONT 1 2 PP1V8_CAM_FRONT_FILT
72 21 0201 20 69
D
1 C2880
100PF
5%
1 C2881
1.0UF
20%
70 20 IN MIPI_CAM_FRONT_CLK_FILT_N 1
SYM_VER-2
TCM0605
4
MIPI_CAM_FRONT_CLK_N OUT 8 70 D
XW2880 XW2881 16V 6.3V
SM SM 2 NP0-C0G 2 X5R 90-OHM-0.1A
1 2 GND_PP1V8_CAM_FRONT1 2 01005 0201-1
VOLTAGE=0V
L2811 72 21 =PP1V8_CAM_FRONT
70 20 IN MIPI_CAM_FRONT_DATA_FILT_P<0> 2 OMIT_TABLE 3 MIPI_CAM_FRONT_DATA_P<0> OUT 8 70
OMIT_TABLE
1
FL2800 4 R2802 1R2803
80-OHM-25%-500MA 70 20 MIPI_CAM_FRONT_DATA_FILT_N<0> 1 MIPI_CAM_FRONT_DATA_N<0> 8 70
2.2K 2.2K
VOLTAGE=2.9V IN OUT 5% 5%
72 =PP2V9_CAM_FRONT 1 2 PP2V9_AVDD_CAM_FRONT_FILT 20 69
SYM_VER-2
TCM0605 1/32W 1/32W
MF MF
0201 90-OHM-0.1A 2 01005 2 01005
1 C2801 1 C2803 21 8 ISP_CAM_FRONT_SCL
100PF 1.0UF ISP_CAM_FRONT_SDA
5% 20% L2812 21 8
XW2800 XW2801 2 16V
NP0-C0G 2 6.3V
X5R
SM VOLTAGE=0V SM
01005 0201-1 20 IN MIPI_CAM_FRONT_DATA_FILT_P<1> 2 OMIT_TABLE 3 MIPI_CAM_FRONT_DATA_P<1> OUT 8
1 2 GND_PP2V9_CAM_FRONT1 2
1 MIPI_CAM_FRONT_DATA_N<1>
OMIT_TABLE 20 IN MIPI_CAM_FRONT_DATA_FILT_N<1> OUT 8
SYM_VER-2 4
FL2803 TCM0605
CRITICAL
80-OHM-25%-500MA 90-OHM-0.1A FL2860
VOLTAGE=1.2V
72 =PP1V2_CAM_FRONT 1 2 PP1V2_CAM_FRONT_FILT 20 69
CRITICAL 150OHM-25%-200MA-0.7DCR
0201 FL2805 ISP_CAM_FRONT_CLK 1 2 ISP_CAM_FRONT_CLK_F
1 C2808 1 C2805 70-OHM-300MA 8 IN OUT 20 69
100PF 01005
5% 1.0UF ISP_CAM_FRONT_SCL 1 2 ISP_CAM_FRONT_SCL_F 1 C2800
20% 21 8 IN OUT 20 69
XW2803 XW2802 2 16V
NP0-C0G 6.3V 56PF
SM VOLTAGE=0V SM 2 X5R 01005-1 5%
01005 0201-1 6.3V
1 2 GND_PP1V2_CAM_FRONT1 2 2 NP0-C0G
01005
CRITICAL
C FL2801
70-OHM-300MA
CRITICAL
FL2880 C
120-OHM-25%-250MA-0.5DCR
21 8 BI ISP_CAM_FRONT_SDA 1 2 ISP_CAM_FRONT_SDA_F BI 20 69
8 ISP_CAM_FRONT_SHUTDOWN_L 1
01005
2 ISP_CAM_FRONT_SHUTDOWN_L_F 20 69
IN OUT
01005-1
R28401
100K
5%
1/32W
MF
01005 2
REAR CAMERA SUPPORT 8 IN ISP_CAM_REAR_CLK

150OHM-25%-200MA-0.7DCR
1 2
CRITICAL
FL2853
ISP_CAM_REAR_CLK_F
01005
1 C2854
OUT 20 69
OMIT_TABLE 56PF
5%
FL2861 2 6.3V
NP0-C0G
80-OHM-25%-500MA 01005
1 2
VOLTAGE=2.9V L2852
72 =PP2V9_CAM_REAR PP2V9_AVDD_CAM_REAR_FILT 20 69
2 OMIT_TABLE 3
0201 70 20 OUT MIPI_CAM_REAR_CLK_FILT_P MIPI_CAM_REAR_CLK_P IN 8 70
CRITICAL
FL2852
1 C2860 1 C2861 MIPI_CAM_REAR_CLK_FILT_N 4 MIPI_CAM_REAR_CLK_N 120-OHM-25%-250MA-0.5DCR
100PF 1.0UF 70 20 OUT
1
IN 8 70
20% ISP_CAM_REAR_SHUTDOWN_L 1 2 ISP_CAM_REAR_SHUTDOWN_L_F
6.3V 8 20 69
B 2 2 X5R
0201-1
SYM_VER-2
TCM0605
90-OHM-0.1A
IN
R28501
01005
OUT
B
100K
OMIT_TABLE 5%
L2853 1/32W
FL2871 MIPI_CAM_REAR_DATA_FILT_P<0> 2 OMIT_TABLE 3 MIPI_CAM_REAR_DATA_P<0>
MF
01005 2
80-OHM-25%-500MA 70 20 OUT IN 8 70
VOLTAGE=2.6V
72 =PP2V6_CAM_REAR_AF 1 0201
2 PP2V6_CAM_REAR_AF_FILT 20 69
CRITICAL
5% MIPI_CAM_REAR_DATA_FILT_N<0> 4 MIPI_CAM_REAR_DATA_N<0>
70 20 OUT
1
IN 8 70 FL2850
16V
1 C2875 SYM_VER-2 70-OHM-300MA
1 C2876 TCM0605
100PF
01005 1.0UF 90-OHM-0.1A 21 8 IN ISP_CAM_REAR_SCL 1 2 ISP_CAM_REAR_SCL_F OUT 20 69
5% 20% 01005-1
2 16V
NP0-C0G
NP0-C0G 2 6.3V
X5R
01005 0201-1 L2854
70 20 MIPI_CAM_REAR_DATA_FILT_P<1> 2 OMIT_TABLE 3 MIPI_CAM_REAR_DATA_P<1> 8 70
OUT IN
OMIT_TABLE
FL2881 MIPI_CAM_REAR_DATA_FILT_N<1> 4 MIPI_CAM_REAR_DATA_N<1> CRITICAL
80-OHM-25%-500MA 70 20
1 8 70 FL2851
VOLTAGE=1.8V OUT IN
72 21 =PP1V8_CAM_REAR 1 2 PP1V8_CAM_REAR_FILT 20 69
SYM_VER-2
TCM0605 70-OHM-300MA
0201 90-OHM-0.1A 21 8 IN ISP_CAM_REAR_SDA 1 2 ISP_CAM_REAR_SDA_F OUT 20 69
1 C2885 1 C2886 01005-1
100PF 1.0UF L2855
5% 20% OMIT_TABLE
2 16V
NP0-C0G 2 6.3V
X5R 70 20 MIPI_CAM_REAR_DATA_FILT_P<2> 2 3 MIPI_CAM_REAR_DATA_P<2> 8
01005 0201-1 OUT IN
MIPI_CAM_REAR_DATA_FILT_N<2> 1
4 MIPI_CAM_REAR_DATA_N<2> 72 21 =PP1V8_CAM_REAR
70 20 OUT IN 8
SYM_VER-2
OMIT_TABLE TCM0605
FL2891 1 1
80-OHM-25%-500MA 90-OHM-0.1A R2800 R2801
VOLTAGE=1.25V
2.2K 2.2K
5% 5%
=PP1V25_CAM_REAR 1 2 PP1V25_CAM_REAR_FILT
A 72
0201
20 69
70 20 MIPI_CAM_REAR_DATA_FILT_P<3> 2
L2856
OMIT_TABLE
3 MIPI_CAM_REAR_DATA_P<3> 8
1/32W
MF
2 01005
1/32W
MF
2 01005 SYNC_MASTER=N/A SYNC_DATE=N/A A
1 1 OUT IN PAGE TITLE
C2895 C2896 ISP_CAM_REAR_SCL
100PF
5%
16V
1.0UF
20%
6.3V MIPI_CAM_REAR_DATA_FILT_N<3> 1
4 MIPI_CAM_REAR_DATA_N<3>
21 8
21 8 ISP_CAM_REAR_SDA CAMERA: CAM SUPPORT
2 NP0-C0G 2 X5R 70 20 OUT IN 8 DRAWING NUMBER SIZE
01005 0201-1 SYM_VER-2
TCM0605
Apple Inc. 051-0301
REVISION
D
90-OHM-0.1A
R
BRANCH B.0.0
28 OF 155
SHEET
21 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_ALT_HEAD

72 =PPVCC_MAIN_AUDIO PART NUMBER
CRITICAL CRITICAL CRITICAL MIKEY BUS FILTER U3000
TABLE_ALT_ITEM
72 24 =PP1V8_AUDIO C3004 1 1 C3040 1 C3041 1 C3042 338S1213 338S1116 RDAR://PROBLEM/13394605

PLACE_NEAR=U3000.A8:5MM 0.1UF 10UF
6.3V
10UF
6.3V
10UF
6.3V
TABLE_ALT_ITEM
1 C3002 1 C3015 10%
6.3V
20%
X5R
20%
X5R
20%
X5R
155S0661 155S0511 RDAR://PROBLEM/12639854
0.1UF 0.1UF CERM-X5R 2 2 0402-10 2 0402-10 2 0402-10 L3000,L3001,L3002,L3003,L3004,L3005

20% 20% 0201
6.3V
2 X5R-CERM 2 6.3V 1 C3030
01005 X5R-CERM
01005 100PF
5%
VOLTAGE=4.2V
16V
2 NP0-C0G
MIN_LINE_WIDTH=0.3MM R3051 R3030 01005
MIN_NECK_WIDTH=0.15MM 1.00 2
PPVCC_VPROG_CP 1 12 2
VOLTAGE=1.7V
PLACE_NEAR=U3000.J4:10MM 1
R3050
D 1
1.00 2
69
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
PP1V7_VCP
1 C3014
0.1UF
1%
0201
1/20W
MF-LF
L81_MBUS_P
5%
1/20W 1
NOSTUFF
C3031
D
10% 22 MF
201 100PF MIKEY_TS_P BI 25 69
1% 6.3V
1/20W CRITICAL CRITICAL 2 CERM-X5R 22 L81_MBUS_N 5% MIKEY_TS_N BI 25 69
72 =PP1V7_VA_VCP MF-LF 1 C3050 1 C3051 0201 R3031 2 16V
NP0-C0G
0201 12 2
PLACE_NEAR=U3000.G1:5MM
4.7UF 1.0UF 1
01005
CRITICAL CRITICAL 20% 20%
X5R
6.3V 6.3V
1 C3001 1 C3003 2 2 0201-1 PLACE_NEAR=U3000.K4:10MM MF
5%
402 201
1/20W
4.7UF 0.1UF X5R VOLTAGE=4.2V
20%
6.3V
10%
6.3V
69 22 GND_AUDIO_CODEC MIN_LINE_WIDTH=0.3MM R3052 1 C3032
2
402
2 CERM-X5R MIN_NECK_WIDTH=0.15MM
PPVCC_VPROG_MB_F 1
255K 2 100PF
0201 5%
69 22 GND_AUDIO_CODEC X5R
1% 16V
2 NP0-C0G
1 C3013 1/20W
201 01005
CRITICAL 0.1UF MF
C3005 10%
6.3V
4.7UF 2 CERM-X5R
0201
2 1 L81_FLYP
VPROG_CP G10
70
G1
VCP0 G8
VCP1 G9
A9
VL A8
VP0 E8
VP1 E9
VPROG_MB H1
CRITICAL
6.3V
VA
C3007
VD
X5R
20%
402
70 L81_FLYC 4.7UF
1 2
CRITICAL
C3006 CRITICAL 20%
6.3V
4.7UF H10 FLYP U3000 +VCP_FILT H9 70 L81_PVCP MIN_NECK_WIDTH=0.15MM X5R
2 1 402
70 L81_FLYN J10 FLYC CS42L81-CWZR-A1 J9
MIN_LINE_WIDTH=0.3MM GNDCP GND_AUDIO_CODEC 22 69
20% MIN_NECK_WIDTH=0.15MM K10 FLYN WLCSP K9 70 L81_NVCP MIN_NECK_WIDTH=0.15MM
6.3V -VCP_FILT CRITICAL
R3001 X5R SYM 1 OF 2 C3008
402 4.7UF
1
2.21K2 NC_MIC1_BIAS NO_TEST=TRUE H2 MIC1_BIAS AOUT1+ F10 NC_CODEC_AOUT1_P NO_TEST=TRUE L3000 CRITICAL
E3 1 2 FERR-33-OHM-0.8A-0.09-OHM
1%
22 AIN1P AIN1+ AOUT1- F9 NC_CODEC_AOUT1_N NO_TEST=TRUE
1/20W 22 AIN1N E4 AIN1- 20% 1 2 CONN_HP_LEFT_FILT 23 69

MF 0201 OUT
H3 6.3V PLACE_NEAR=J3100.3:10MM
201 22 MIC1_BIAS_FILT MIC1_BIAS_FILT X5R CRITICAL
402
C CRITICAL AOUT2+
D10 NC_CODEC_AOUT2_P NO_TEST=TRUE
L3001
FERR-33-OHM-0.8A-0.09-OHM C
C3011 1
AOUT2- D9 NC_CODEC_AOUT2_N NO_TEST=TRUE 1
0201
2 PLACE_NEAR=J3100.1:10MM CONN_HP_RIGHT_FILT OUT 23 69
1.0UF L81_MIC2_BIAS_IN J3 MIN_LINE_WIDTH=0.20MM
20% CRITICAL MIC2_BIAS_IN MIN_NECK_WIDTH=0.15MM
6.3V 2 G4
X5R C3012 L81_MIC2_BIAS MIC2_BIAS
0201-1 K3
4.7UF MIC2_BIAS_FILT_IN DP J4 L81_MBUS_P 22
1 2 F3 L3002
L81_MIC2_BIAS_FILT_IN L81_MIC2_BIAS_FILT MIC2_BIAS_FILT DN K4 L81_MBUS_N 22 FERR-33-OHM-0.8A-0.09-OHM
20% 402 L81_AIN2_POS C1 AIN2+ HPOUTA J8 CODEC_HP_LEFT
6.3V 1 2
CRITICAL CONN_HP_HS3_FILT 23 69
D1 IN
X5R L81_AIN2_NEG AIN2- HPOUTB K8 CODEC_HP_RIGHT 0201
HS3 J1 22 CODEC_HP_HS3 CRITICAL MIN_NECK_WIDTH=0.20MM
NO_XNET_CONNECTION=TRUE
XW3002 C3016 L3003
0.1UF HS4 K1 22 CODEC_HP_HS4
FERR-33-OHM-0.8A-0.09-OHM
PLACE_NEAR=J3100.14:10MM TO HEADPHONE JACK
SHORT-8L-0.25MM-SM H4 K7
CODEC_HP_HS4 2 1 HP_MIC_POS 1 2 NC_MIC3_BIAS NO_TEST=TRUE MIC3_BIAS HS3_REF CODEC_HP_HS3_REF
22
C3 J7 1 2 CONN_HP_HS4_FILT IN 23 69
69 22 AIN3P AIN3+ HS4_REF CODEC_HP_HS4_REF 0201 PLACE_NEAR=J3100.13:10MM
10% C2
6.3V 69 22 AIN3N AIN3- HPDETECT H8 CODEC_HP_DET MIN_NECK_WIDTH=0.20MM
NOTE:EXTMIC INPUTS FROM HS3/HS4.

EXTERNAL SWITCHES FOR RETURN
MUST USE
CURRENTS CERM-X5R
0201 22 MIC3_BIAS_FILT
G3
MIC3_BIAS_FILT
LINEOUTA L3004 CRITICAL
XW3003 C3017 F4 K6 NC_CODEC_LINEOUTA NO_TEST=TRUE
FERR-33-OHM-0.8A-0.09-OHM
0.1UF LINEOUTB
SHORT-8L-0.25MM-SM NC_MIC4_BIAS NO_TEST=TRUE J6 NC_CODEC_LINEOUTB NO_TEST=TRUE
2 1 1 2 MIC4_BIAS LINEOUT_REF 1 2
22 CODEC_HP_HS3 HP_MIC_NEG D2 H6
CONN_HP_HS3_REF_FILT IN 23 69
10% 22 AIN4P AIN4+ 0201 PLACE_NEAR=J3100.12:10MM
AIN4N E2
F2 AIN4-
6.3V
0201
22
FILT+ L3005 CRITICAL
CERM-X5R 22 MIC4_BIAS_FILT MIC4_BIAS_FILT E1 L81_FILT FERR-33-OHM-0.8A-0.09-OHM
FILT-
F1 1 2 CONN_HP_HS4_REF_FILT
IN 23 69
1 C3010 0201 PLACE_NEAR=J3100.11:10MM
C10 10UF
GNDHS
NC_SPEAKER_VQ NO_TEST=TRUE GNDHS
GNDP
GNDD
GNDA
SPEAKER_VQ 20%
2 6.3V
CERM-X5R
0402-2 L3020
R3020 240-OHM-0.2A-0.8-OHM
3.3K 2
B
E10
A10
K2
J2
G2
B 1
5%
CODEC_HP_DET_R 1 2
0201-2
CONN_HP_HEADSET_DET_FILTIN 23 69
1/32W 1 C3020
MF NOSTUFF
01005
XW3000 10%
SM 10V
2 4700PF
VOLTAGE=0V
1 2 GND_AUDIO_CODEC 22 69
201
X7R
GND0 C6
70 28 DMIC_BTN_SD 22 5% 1 2 MF R3012 DMIC_BTN_SD_R B1 DMIC1_SD
IN 1/32W 01005 D3
B2 GND1
CODEC_AIN AIN1P 22
69 28 OUT DMIC_BTN_SCLK 22 5% 1
1/32W
2 MF
01005
R3013 DMIC_BTN_SCLK_R DMIC1_SCLK CRITICAL D5
GND2
MAKE_BASE=TRUE
AIN1N 22 5%
U3000 GND3 D6
DMIC_MIC_SD 22 1/32W
1 2 MF R3014 DMIC_MIC_SD_R B7 DMIC2_SD CS42L81-CWZR-A1
AIN3P
AIN3N 22 69
70 23 IN 01005 GND4 D7
1 DMIC_MIC_SCLK 22 5% 1 2 MF R3015 DMIC_MIC_SCLK_R B6 DMIC2_SCLK WLCSP
C3090 22 69
69 23 OUT 1/32W 01005 GND5 D8
0.01UF SYM 2 OF 2
10% AIN4P 22
MCLK GND6 E5
I2S_SOC2CODEC_ASP_MCK C8
2 6.3V
X5R AIN4N 22
70 6 IN
GND7 E6
01005 A3 E7
70 6 IN I2S_SOC2CODEC_ASP_BCLK ASP_SCLK GND8
70 6 I2S_SOC2CODEC_ASP_LRCK B3 ASP_LRCK GND9 F5
IN
R3010 70 6 IN I2S_SOC2CODEC_ASP_DOUT A2 ASP_SDIN GND10 F6
I2S_CODEC2SOC_ASP_DOUT 1
22 2 I2S_CODEC2SOC_ASP_DOUT_R A1 F7
70 6 OUT ASP_SDOUT GND11
5% GND12 F8
CODEC_MIC_BIAS_FILT MIC1_BIAS_FILT 1/32W
22
MF 70 6 I2S_SOC2CODEC_XSP_BCLK B4 XSP_SCLK GND13 G5
MAKE_BASE=TRUE 01005 IN
MIC3_BIAS_FILT 22
70 6 I2S_SOC2CODEC_XSP_LRCK B5 XSP_LRCK_FSYNC GND14 G6
IN
MIC4_BIAS_FILT 22 R3011 70 6 IN I2S_SOC2CODEC_XSP_DOUT A5 XSP_SDIN_DAC2_MUTE GND15 G7
22 A4
A 1 C3091
70 6 OUT I2S_CODEC2SOC_XSP_DOUT 1
5%
2
25 IN
I2S_CODEC2SOC_XSP_DOUT_R
L81_MBUS_REF
SPI_CODEC_CS_L
K5
XSP_SDOUT
MBUS_REF
GND16
GND17
H5
H7 SYNC_MASTER=N/A SYNC_DATE=N/A A
1/32W PAGE TITLE
0.01UF MF C5 CS* GND18 J5
10%
2 6.3V
X5R
01005
6
6 OUT
OUT SPI_CODEC_SCLK A6 CCLK AUDIO: L81 CODEC
01005 6 SPI_CODEC_MOSI B8 CDIN DRAWING NUMBER SIZE
IN
6 OUT SPI_CODEC_MISO A7 CDOUT Apple Inc. 051-0301 D
TSTI0 C4 REVISION
B9 TSTI1 C7 R
B.0.0
70 6
OUT GPIO_CODEC2SOC_IRQ_L INT* BRANCH
B10 TSTI2 D4 NOTICE OF PROPRIETARY PROPERTY:
70
69 62
OUT GPIO_CODEC2PMU_HS_IRQ_L WAKE*
62 GPIO_PMU2CODEC_RESET_L C9 RESET* THE INFORMATION CONTAINED HEREIN IS THE
IN PROPRIETARY PROPERTY OF APPLE INC.
PAGE 30 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AUDIO JACK AND DMIC CONN

ALS FILTERS FL3125 AUDIO JACK B2B CONNECTOR
70-OHM-300MA MATCHES ALS_AUDIO_JACK_FLEX 2.1.0 02/18/14
D 72 =PP3V0_HP_ALS 1
01005-1
2
VOLTAGE=3.0V
PP3V0_HP_ALS_FILT 23 69
CRITICAL
D
J3100
1 C3132 BM20P-0.6-24DS-0.4V MLB: 516S1321
27PF F-ST-SM FLEX: 516S1322
5% 25 26
16V
2 NP0-C0G
01005
1 2
NC NC
3 4
NC
FL3133 5 6 GPIO_SOC2AJ_HS4_SHUNT_EN_FILT 23 69
70-OHM-300MA
59 PP3V0_S2R_ANT_SW_FILT 7 8 GPIO_SOC2AJ_HS3_SHUNT_EN_FILT 23 69
=I2C_HP_ALS_SDA_1V8 1 2 I2C_HP_ALS_SDA_1V8_FILT
4 BI
CKPLUS_WAIVE=I2C_PULLUP
23 69 70
59 GPIO_BB2ANT_SW0_FILT 9 10
01005-1
59 GPIO_BB2ANT_SW1_FILT 11 12 CONN_HP_HEADSET_DET_FILT 22 69
OUT
13 14 CONN_HP_RIGHT_FILT IN 22 69
FL3134 PP3V0_HP_ALS_FILT 15 16 CONN_HP_LEFT_FILT
70-OHM-300MA 69 23 IN 22 69
1 2
17 18 CONN_HP_HS4_REF_FILT OUT 22 69
4 IN =I2C_HP_ALS_SCL_1V8 I2C_HP_ALS_SCL_1V8_FILT 23 69 70
01005-1 CKPLUS_WAIVE=I2C_PULLUP 69 23 GPIO_HP_ALS2SOC_IRQ_L_FILT 19 20 CONN_HP_HS3_REF_FILT OUT 22 69
70 69 23 I2C_HP_ALS_SCL_1V8_FILT 21 22 CONN_HP_HS4_FILT OUT 22 69
FL3135 70 69 23 I2C_HP_ALS_SDA_1V8_FILT
23 24 CONN_HP_HS3_FILT OUT 22 69
6 OUT GPIO_HP_ALS2SOC_IRQ_L 1 2 GPIO_HP_ALS2SOC_IRQ_L_FILT 23 69

27 28
01005 NOSTUFF K K NOSTUFF
120-OHM-25%-250MA-0.5DCR
D3101 D3100
SM-201 SM-201
DSF01S30SC DSF01S30SC
A A
C C
SHUNT FILTERS
FL3140
9 GPIO_SOC2AJ_HS3_SHUNT_EN 1 2 GPIO_SOC2AJ_HS3_SHUNT_EN_FILT 23 69
IN
01005
120-OHM-25%-250MA-0.5DCR
MIC FLEX CONNECTOR
FL3141 CRITICAL
J3150
9 IN GPIO_SOC2AJ_HS4_SHUNT_EN 1 2 GPIO_SOC2AJ_HS4_SHUNT_EN_FILT 23 69 AA07A-S010-VA1 MLB: 516S0899
F-ST-SM
01005 12 FLEX: 516S0900
120-OHM-25%-250MA-0.5DCR MATCHES MIC_FLEX_ALS 1.0.0 02/17/14
11
23 DMIC_MIC_SD_FILT 2 1 GPIO_BTN_ONOFF_L_FILT 23
23 DMIC_MIC_SCLK_FILT 4 3 PP1V8_DMIC_MIC_FILT 23 69
6 5
PP3V0_MIC_ALS_FILT
69 23 8 7 GPIO_MIC_ALS2SOC_IRQ_L_F 23 69
70 69 23 I2C_MIC_ALS_SDA_1V8_F 10 9 I2C_MIC_ALS_SCL_1V8_F 23 69 70
13
14
DMIC FILTERS
FL3150
B 69 22 IN DMIC_MIC_SCLK 1 2 DMIC_MIC_SCLK_FILT 23
B
01005
120-OHM-25%-250MA-0.5DCR 1 C3150
27PF
5%
2 16V
NP0-C0G
01005
FL3151
70 22 OUT DMIC_MIC_SD 1 2 DMIC_MIC_SD_FILT 23
01005
120-OHM-25%-250MA-0.5DCR 1 C3151
27PF
5%
2 16V
NP0-C0G
01005 FL3124
70-OHM-300MA
FL3100 =I2C_MIC_ALS_SCL_1V8 1 2 I2C_MIC_ALS_SCL_1V8_F
4 IN 23 69 70
VOLTAGE=1.8V
CKPLUS_WAIVE=I2C_PULLUP
72 28 =PP1V8_DMIC 1 2 PP1V8_DMIC_MIC_FILT 23 69
01005-1
01005
120-OHM-25%-250MA-0.5DCR FL3123
1 C3100 70-OHM-300MA
27PF
5% 4 =I2C_MIC_ALS_SDA_1V8 1 2 I2C_MIC_ALS_SDA_1V8_F 23 69 70
BI
2 16V
NP0-C0G CKPLUS_WAIVE=I2C_PULLUP
01005-1
01005 TABLE_5_HEAD

FL3122
150OHM-25%-200MA-0.7DCR 155S00018 1 FERRITE,80OHM,25%,500MA,0.18DCR L3121 CRITICAL
TABLE_5_ITEM
6 OUT GPIO_MIC_ALS2SOC_IRQ_L 1 2 GPIO_MIC_ALS2SOC_IRQ_L_F 23 69
A 01005
L3121 SYNC_MASTER=N/A SYNC_DATE=N/A A
80-OHM-25%-500MA PAGE TITLE
L3113
240-OHM-25%-0.20A-1.0DCR R3113 72 =PP3V0_MIC_ALS 1 2 PP3V0_MIC_ALS_FILT 23 69
AUDIO: HP/DMIC FLEX CONNS
240 0201 VOLTAGE=3.0V
DRAWING NUMBER SIZE
GPIO_BTN_ONOFF_L 1 2 GPIO_BTN_ONOFF_R_L 1 2 GPIO_BTN_ONOFF_L_FILT
69 62 6 5 OUT
01005
1%
23
OMIT_TABLE 1 C3121 Apple Inc. 051-0301 D
1/32W 1.0UF REVISION
MF 20%
01005 2 DZ3113 6.3V
2 X5R
R
B.0.0
201-1 BRANCH
12.8V-100PF 0201-1 NOTICE OF PROPRIETARY PROPERTY:
1
SHEET
23 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D
72 24
RIGHT SPEAKER AMP
=PPBATT_AUDIO PLACE_NEAR=U3200.B1:2MM
CRITICAL
=PP1V8_AUDIO 22 24 72
D
1 C3235 1 C3200 1 C3201 69
VOLTAGE=8V
PPVBOOST_R
1 C3202
100PF 10UF 0.1UF 0.1UF
5% 20% 20%
2 16V
NP0-C0G 2 6.3V 6.3V
2 X5R-CERM CRITICAL CRITICAL 2
01005 X5R 01005 1 C3220 1 C3221 1 C3223
0402-10
10UF 25V X5R-
10UF 0.1UF 10%
20% CERM
20% 10% 16V
2 25V
X5R-CERM 2 0603 25V
2 X5R =PP1V8_SPKRAMP_DVDD
X5R-CERM 24 72
0603 0201 0201
PLACE_NEAR=L3210.2:3MM 1 C3203
CRITICAL CRITICAL CRITICAL CRITICAL 1.0UF
20%
PVDD D1
C3210 C3211 C3213 C3230
VBST E1
VBAT B1
VIOC A4
DVDD E5
1 1 1
10UF 10UF 10UF CRITICAL 1.0UF 2 6.3V
X5R
20%
6.3V
6.3V
20%
X5R
6.3V
20%
X5R
L3210 1 2
0201-1
X5R 2 0402-10 2 0402-10 2 1.0UH-20%-3.2A-0.065OHM
0402-10 VOLTAGE=8V 20% X5R
1
PIFE25201T-SM
2 PPVBOOST_R_LX D2 LX 6.3V
0201-1
E2 CRITICAL
LX U3200VREFC1 B6 CRITICAL
SPKRAMP_VREFC1_R
=I2C_SOC2SPKRAMP_SCL_1V8 E4
SCL
WLP
VREFC2 E3 SPKRAMP_VREFC2_R C3231
24 4
1.0UF
MAX98721BEWV
IN
72 24 22 =PP1V8_AUDIO 24 4 =I2C_SOC2SPKRAMP_SDA_1V8 D4 SDA 1 2
BI
NOSTUFF1 D3 20% X5R
24 SPKRAMP_ADDRESS_RIGHT ADDR 6.3V
R3200 GPIO_SOC2SPKRAMP_KEEPALIVE 0201-1
10K 24 6
A3 WDT
5% IN
1/32W
24 6 B3 OUTP A1 SPKRAMP_R_OUT_P
MF
01005 70 IN I2S_SOC2SPKRAMP_MCK MCLK (SPKRAMP_R_OUT_P)
OUT 27 69 70
2 (SPKRAMP_R_OUT_N)
8 GPIO_SPKRAMP2SOC_RIGHT_IRQ_L D5 IRQ* OUTN A2 SPKRAMP_R_OUT_N OUT 27 69 70
OUT
I2S_SOC2SPKRAMP_BCLK 2 2
A6 BCLK
70 24 6 IN B5
XW3200 XW3201
C 72 24 22 =PP1V8_AUDIO 70 24 6 IN I2S_SOC2SPKRAMP_LRCK
A5
LRCLK SHORT-10L-0.1MM-SM
PLACE_NEAR=J3700.10:2MM
SHORT-10L-0.1MM-SM
PLACE_NEAR=J3700.6:2MM C
R3201 1 70 24 6 IN I2S_SOC2SPKRAMP_DOUT B4 DIN VSNSP E6 SPKRAMP_R_VSENSE_P 1 1
1.00K 70 24 6 OUT I2S_SPKRAMP2SOC_DOUT DOUT VSNSN D6 SPKRAMP_R_VSENSE_N

5%
GND PGND
MF
01005
1/32W 2 APN: 353S4488
C3
B2
C1
C2
C4
C5
C6
SPKRAMP_ADDRESS_RIGHT 24
SPKRAMP_ADDRESS_LEFT 24
R32511
1.00K
5%
1/32W
MF
01005
2
72 24
LEFT SPEAKER AMP
=PPBATT_AUDIO PLACE_NEAR=U3250.B1:2MM
CRITICAL
=PP1V8_AUDIO 22 24 72
1 C3285 1 C3250 1 C3251 69

VOLTAGE=8V
PPVBOOST_L
1 C3252
100PF 10UF 0.1UF 0.1UF
6.3V
20% 20%
X5R CRITICAL CRITICAL
2 2 0402-10 2 6.3V
X5R-CERM 125V 1 25V 1 2
01005
NP0-C0G
01005 C3270
X5R-CERM C3271
X5R-CERM C3273
10UF
0603
10UF
0603
0.1UF 10%
16V 20% 20% 10% 16V
5% 25V =PP1V8_SPKRAMP_DVDD
2 2 2 X5R X5R-CERM 24 72
0201 0201
PLACE_NEAR=L3260.2:3MM 1 C3253
CRITICAL CRITICAL CRITICAL CRITICAL 1.0UF
C3280 20%
PVDD D1
C3260 C3261 C3263
VBST E1
VBAT B1
VIOC A4
DVDD E5
1 1 1
2 6.3V
B 10UF
20%
6.3V
10UF
6.3V
20%
X5R
10UF
6.3V
20%
X5R
CRITICAL
L3260
1.0UF
1 2
X5R
0201-1 B
X5R 2 0402-10 2 0402-10 2 1.0UH-20%-3.2A-0.065OHM 20% X5R
0402-10 VOLTAGE=8V
6.3V
1 2 PPVBOOST_L_LX D2 LX 0201-1
PIFE25201T-SM E2 CRITICAL
LX U3250VREFC1 B6 CRITICAL
SPKRAMP_VREFC1_L C3281
E4 WLP
24 4 =I2C_SOC2SPKRAMP_SCL_1V8 SCL VREFC2 E3 SPKRAMP_VREFC2_L 1.0UF
MAX98721BEWV
IN
72 24 22 =PP1V8_AUDIO 24 4 =I2C_SOC2SPKRAMP_SDA_1V8 D4 SDA 1 2
BI
20% X5R
NOSTUFF1 24 SPKRAMP_ADDRESS_LEFT D3 ADDR 6.3V
R3250 0201-1
10K 24 6 GPIO_SOC2SPKRAMP_KEEPALIVE A3 WDT
5% IN
1/32W
MF
B3 OUTP A1 SPKRAMP_L_OUT_P
01005 70 24 6 IN I2S_SOC2SPKRAMP_MCK MCLK (SPKRAMP_L_OUT_P)
OUT 27 69 70
2 (SPKRAMP_L_OUT_N)
8 GPIO_SPKRAMP2SOC_LEFT_IRQ_L D5 IRQ* OUTN A2 SPKRAMP_L_OUT_N OUT 27 69 70
OUT
2 2
I2S_SOC2SPKRAMP_BCLK A6
70 24 6 IN B5 BCLK
XW3250 XW3251
70 24 6 IN I2S_SOC2SPKRAMP_LRCK LRCLK SHORT-10L-0.1MM-SM SHORT-10L-0.1MM-SM
A5 PLACE_NEAR=J3700.14:2MM PLACE_NEAR=J3700.18:2MM
70 24 6 IN I2S_SOC2SPKRAMP_DOUT B4 DIN VSNSP E6 SPKRAMP_L_VSENSE_P 1 1
70 24 6 OUT I2S_SPKRAMP2SOC_DOUT DOUT VSNSN D6 SPKRAMP_L_VSENSE_N

GND PGND
APN: 353S4488
C3
B2
C1
C2
C4
C5
C6
PAGE TITLE
AUDIO: SPEAKER AMPS

DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
PAGE32 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_5_HEAD
D 155S0667 2 COMMON MODE CHOKE,90OHM,100MA L3530,L3531 CRITICAL

TABLE_5_ITEM
D
TABLE_ALT_HEAD
72 =PP3V0_S2R_TRISTAR =PP3V3_ACC 72 PART NUMBER ALTERNATE FOR

PART NUMBER
TABLE_ALT_ITEM
1 C3530 1 C3535 1 C3540 1 C3542 1 C3532 377S0155 377S0104 ? RDAR://PROBLEM/12840267
1.0UF 0.22UF 15PF 15PF 0.22UF DZ3500,DZ3501,DZ3502,DZ3503,DZ3590

20% 20% 5% 5% 20%
2 6.3V
X5R
6.3V
2 X5R
16V
2 NP0-C0G-CERM
16V
2 NP0-C0G-CERM 2 6.3V
X5R
0201-1 0201 01005 01005 0204
72 =PP1V8_S2R_TRISTAR
1 C3531 1 C3541 OMIT_TABLE
VDD_1V8 F3
VDD_3V0 F4
ACC_PWR D5
0.22UF 15PF VOLTAGE=15V L3530
20%
6.3V
5%
16V
PPVBUS_PROT 65 69 90-OHM-0.1A
2 X5R 2 NP0-C0G-CERM TCM0605
SYM_VER-1
0201 01005 1
1 C3543 C3534 1 C3545 1 4 E75_DPAIR1_CONN_P BI 27 69
8.2PF 1UF 1UF
+/-0.5PF 10% 10%
50V
2 C0G-CERM 2 25V
X5R
25V
2 X5R E75_DPAIR1_CONN_N
U3500 201 402 402 2 3
BI 27 69
CBTL1610A1UK
C3 WLCSP
69 22 BI MIKEY_TS_P DIG_DP
CRITICAL P_IN F6
C4
69 22 BI MIKEY_TS_N DIG_DN ACC1 C5 PPOUT_E75_ACC_ID1 26
CRITICAL
2 2 CRITICAL
6 A1 ACC2 E5 PPOUT_E75_ACC_ID2 26 DZ3500 DZ3501

8 BI USB_BB_P USB1_DP ESD0P2RF-02LS ESD0P2RF-02LS
71 62 USB_BB_N B1 USB1_DN DP1 A2 E75_DPAIR1_P TSSLP-2-1 TSSLP-2-1
BI
E75_DPAIR1_N
DN1 B2 0.4PF
C OUT PMU_USB_BRICKID C2 BRICK_ID
DP2 E75_DPAIR2_P
0.4PF 1 1
C
69 5 USB_SOC_P A3 USB0_DP A4 E75_DPAIR2_N
BI
ACCESSORY USB B3 DN2
69 5 BI USB_SOC_N USB0_DN B4
UART0_TX TS_E75_ACC_DET_L
E2 CON_DET_L E3 OMIT_TABLE
ACCESSORY UART UART_SOC2ACC_TX
70 6 IN
E1 L3531
70 6 OUT UART_ACC2SOC_TX UART0_RX POW_GATE_EN* D6 OVP_SW_EN_L OUT 65 90-OHM-0.1A
TCM0605
TRISTAR TX IS AN INPUT F2
SYM_VER-1
AND ITS RX IS AN OUT 69 6 IN UART_SOC2DEBUG_TX UART1_TX SWITCH_EN E4 RESET_SOC_L IN 4 5 10 62 68 69 70

1 4
SOC DEBUG UART F1 E75_DPAIR2_CONN_P BI 27 69
69 6 OUT UART_DEBUG2SOC_TX UART1_RX HOST_RESET B6 GPIO_TS2PMU_RESET OUT 62
BB DEBUG UART UART_BB2SOC_TX D2 SDA

D3
(T’S OFF TO SOC UART) 71 68 6 IN UART2_TX =I2C_SOC2TRISTAR_SDA_1V8 OUT 4
2 3 E75_DPAIR2_CONN_N
UART_SOC2BB_TX D1 D4 BI 27 69
71 68 6 OUT UART2_RX SCL
INT =I2C_SOC2TRISTAR_SCL_1V8 IN 4
C6 GPIO_TS2SOC2PMU_IRQ
JTAG_SOC_TCK_R A5 OUT 6 62
JTAG_CLK BYPASS E6
B5 JTAG_DIO BYPASS_TS CRITICAL CRITICAL
JTAG_SOC_TMS_R 2 2
DZ3502 DZ3503
DVSS
DVSS
DVSS
PLACE_NEAR=U3500.A5:5MM 1 C3533 ESD0P2RF-02LS ESD0P2RF-02LS
R3530 1.0UF TSSLP-2-1 TSSLP-2-1
0.00 20% 0.4PF
F5
C1
A6
69 5 OUT JTAG_SOC_TCK 1 2 2 6.3V
X5R 1 1 0.4PF
0% MF 0201-1
1/32W 01005
R3531
JTAG_SOC_TMS 1
0.00 2
69 5 BI
MF 01005
0%
1/32W FL3590
R3590 120-OHM-25%-250MA-0.5DCR
10K 1 2
1 2 E75_ACC_DET_R_L E75_ACC_DET_CONN_L IN 27 69
5% 01005
1/32W
B CRITICAL K
D3591
MF
01005
NOSTUFF
C3590 1
2
CRITICAL
DZ3590 B
SM-201 15PF ESD0P2RF-02LS
5% TSSLP-2-1
DSF01S30SC 16V
A NP0-C0G-CERM 2
01005 1
XW3500
SHORT-10L-0.25MM-SM
22 OUT L81_MBUS_REF 1 2
PAGE TITLE
IO: TRISTAR
DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
PAGE35 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
L3600
FERR-22-OHM-1A-0.055OHM
25 PPOUT_E75_ACC_ID1 1 2 PPOUT_E75_ACC_ID1_CONN 27 69
0201
0.055 OHM DCR C
DZ3691
1 C3670
14.2V-6PF 15PF
D A
0201-1
5%
16V
2 NP0-C0G-CERM
01005
D
TABLE_ALT_HEAD

PART NUMBER
L3601 TABLE_ALT_ITEM
FERR-22-OHM-1A-0.055OHM 377S0116 377S0108 DZ3660 RDAR://PROBLEM/8370432

VOLTAGE=3.3V VOLTAGE=3.3V TABLE_ALT_ITEM
25 PPOUT_E75_ACC_ID2 1 2 PPOUT_E75_ACC_ID2_CONN 27 69 155S0320 155S0513 L3600,L3601 RDAR://PROBLEM/9625601

0201 C TABLE_ALT_ITEM
0.055 OHM DCR DZ3692

1 C3671 155S0741 155S0397 L3657 RDAR://PROBLEM/11238851
15PF
14.2V-6PF 5%
0201-1 16V
2 NP0-C0G-CERM
A 01005
CRITICAL
L3657
FERR-70-OHM-4A
VOLTAGE=15V
72 =PPVBUS_USB_EMI 1 2 PPVBUS_E75_USB_CONN 27 69
0603
2 1
1 1
R3690 DZ3660 C3683 1 C3672
C3622 0.01UF 15PF
15PF 100K 27V-100PF 10% 5%
C 5%
16V
2 NP0-C0G-CERM
5%
1/20W
MF
0402 2 50V
X7R
402
16V
2 NP0-C0G-CERM
01005
C
01005 2 201 1
B B
PAGE TITLE
IO: FILTERS
DRAWING NUMBER SIZE

REVISION
R
BRANCH
B.0.0
SHEET
26 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
IO FLEX HOTBAR PADS

OMIT
J3700 MLB: 998-5877
PCB-X110
FLEX: 998-5876
MATCHES IO_FLEX_WINGS 3.0.0 05/05/14
HB-SM
1
2
C 3
5
4
6
C
70 69 24 SPKRAMP_L_OUT_N 7
IN 8
9
10
70 69 24 IN SPKRAMP_L_OUT_P 11
13
12 E75_ACC_DET_CONN_L OUT 25 69
14
70 69 24 IN SPKRAMP_R_OUT_P 15
16
17
PPOUT_E75_ACC_ID2_CONN 26 69
18
70 69 24 SPKRAMP_R_OUT_N 19
IN 20
21
22
23
25
24 E75_DPAIR2_CONN_P BI 25 69
69 26 PPOUT_E75_ACC_ID1_CONN
27
26 E75_DPAIR2_CONN_N BI 25 69
28
29
30 E75_DPAIR1_CONN_N BI 25 69
69 26 PPVBUS_E75_USB_CONN 31
32
33
E75_DPAIR1_CONN_P BI 25 69
34
35
36
37
38
39
40
41
42
43
44
45
46
47
B B
A SYNC_MASTER=N/C SYNC_DATE=N/A A
PAGE TITLE
IO: HOTBAR PADS

DRAWING NUMBER SIZE

REVISION
R
BRANCH
B.0.0
SHEET
27 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
BUTTON CONNECTOR
L3910
240-OHM-25%-0.20A-1.0DCR R3910
1 2 240
6 OUT GPIO_BTN_VOL_DOWN_L 01005 GPIO_BTN_VOL_DOWN_R_L 1 2 GPIO_BTN_VOL_DOWN_L_FILT 28 69
CRITICAL
C 1%
1/32W
MF
J3910 C
DZ3910 2 AA07A-S010-VA1
F-ST-SM MLB: 516S0899
01005 201-1
12.8V-100PF MATCHES BUTTON_FLEX 2.1.0 02/18/14 12 FLEX: 516S0900
11
1
28 DMIC_BTN_SCLK_FILT 1 2
28 DMIC_BTN_SD_FILT 3 4
L3911 69 28 PP1V8_DMIC_BTN_FILT 5 6
240-OHM-25%-0.20A-1.0DCR R3911 GPIO_BTN_VOL_UP_L_FILT 7 8
240 69 28
6 OUT GPIO_BTN_VOL_UP_L 1 2 GPIO_BTN_VOL_UP_R_L 1 2 GPIO_BTN_VOL_UP_L_FILT 28 69
69 28 GPIO_BTN_VOL_DOWN_L_FILT 9 10
01005
1%
1/32W
MF DZ3911 2 13
201-1
0100512.8V-100PF 14
DMIC FILTERS
FL3950
69 22 IN DMIC_BTN_SCLK 1 2 DMIC_BTN_SCLK_FILT 28
01005
120-OHM-25%-250MA-0.5DCR 1 C3950
27PF
5%
2 16V
NP0-C0G
01005
B B
FL3951
70 22 DMIC_BTN_SD 1 2 DMIC_BTN_SD_FILT 28
OUT
01005
120-OHM-25%-250MA-0.5DCR 1 C3951
27PF
5%
2 16V
01005
NP0-C0G
FL3900
VOLTAGE=1.8V
72 23 =PP1V8_DMIC 1 2 PP1V8_DMIC_BTN_FILT 28 69
01005
120-OHM-25%-250MA-0.5DCR 1 C3900
27PF
5%
16V
2 NP0-C0G
01005
PAGE TITLE
IO: BUTTON FLEX CONN

DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
PAGE39 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
STINGER
72 30 =PP5V25_GRAPE PPVDD_STINGER_BOOST 29 69
1 C4019 1 C4020 1 C4021

4.7UF 0.1UF 10UF
20% 20%
=PPVCC_MAIN_GRAPE 25V
72 30 29 2 X5R-CERM 2 2 X5R-CERM
0201
0402 0603
D 1 C4016
0.1UF
1 C4018
4.7UF
10V X5R
25V
10%
D
10% 20%
10V 6.3V =PP1V8_GRAPE_EXT_SW
2 X5R-CERM 2 X5R-CERM1 29 30 72
0201
402
VDDIO J10
1 C4022
VBAT N7
VBATDRV N9
B6
E6
H7
J5
L5
B5
F5
H6
H9
K5
M5
0.1UF
20%
4V
CRITICAL VDDH VDDHV 2 X5R
01005
J4020
AA21 MLB APN: 516S1070
MATCHES GRAPE_FLEX_ALT3 1.1.0 01/13/14 F-ST-SM FLEX APN: 516S1071 CRITICAL
43 44
30 IN CUMULUS_VSTM<0> A2 TXI0 U4003 TXO0 A3 MT_PANEL_OUT<0> 29 70
30 IN CUMULUS_VSTM<1> A4 TXI1 STINGER TXO1 A5 MT_PANEL_OUT<1> 29 70

1 2
CUMULUS_VSTM<2> A7 TXI2 CSP TXO2 A6 MT_PANEL_OUT<2> 29 70
MT_PANEL_OUT<39> 3 4 MT_PANEL_OUT<0> 30 IN
70 29 29 70
30 IN CUMULUS_VSTM<3> A9 TXI3 TXO3 A8 MT_PANEL_OUT<3> 29 70
70 29 MT_PANEL_OUT<38> 5 6 MT_PANEL_OUT<1> 29 70
B1 B2
30 IN CUMULUS_VSTM<4> TXI4 TXO4 MT_PANEL_OUT<4> 29 70
30 IN CUMULUS_VSTM<5> B3 TXI5 TXO5 B4 MT_PANEL_OUT<5> 29 70
70 29 MT_PANEL_OUT<36> 9 10 MT_PANEL_OUT<3> 29 70 30
IN CUMULUS_VSTM<6> B8 TXI6 TXO6 B7 MT_PANEL_OUT<6> 29 70

B10 B9 MT_PANEL_OUT<7>
30 IN CUMULUS_VSTM<7> TXI7 TXO7 29 70
C1 C2
30 IN CUMULUS_VSTM<9> C3 TXI9 TXO9 C4 MT_PANEL_OUT<9> 29 70
30
C8 C7
IN CUMULUS_VSTM<10> TXI10 TXO10 29 70
C10 C9 MT_PANEL_OUT<10>
D1 D2
D3 D4
MT_PANEL_OUT<11> 30 IN CUMULUS_VSTM<13> TXI13 TXO13 MT_PANEL_OUT<13> 29 70
70 29 MT_PANEL_OUT<28> 25 26 29 70
D5 D6
MT_PANEL_OUT<12> 30
IN CUMULUS_VSTM<14> TXI14 TXO14 MT_PANEL_OUT<14> 29 70
70 29 MT_PANEL_OUT<27> 27 28 29 70
D8 D7
D10 D9
MT_PANEL_OUT<25> 31 32
C
70 29
70 29 MT_PANEL_OUT<24> 33 34
MT_PANEL_OUT<15>
MT_PANEL_OUT<16>
29 70
29 70
30
30 IN
IN
CUMULUS_VSTM<17>
CUMULUS_VSTM<18>
E1
E3
TXI17
TXI18
TXO17
TXO18
E2
E4
MT_PANEL_OUT<17>
MT_PANEL_OUT<18>
29 70
29 70
C
70 29 MT_PANEL_OUT<23> 35 36 29 70
E8 E7
70 29 MT_PANEL_OUT<22> 37 38 29 70
MT_PANEL_OUT<18> 30
IN CUMULUS_VSTM<20> E10 TXI20 TXO20 E9 MT_PANEL_OUT<20> 29 70
70 29 MT_PANEL_OUT<21> 39 40 29 70
F1 F2
70 29 MT_PANEL_OUT<20> 41 42 29 70
30
IN CUMULUS_VSTM<22> F3 TXI22 TXO22 F4 MT_PANEL_OUT<22> 29 70
30 IN CUMULUS_VSTM<23> F8 TXI23 TXO23 F7 MT_PANEL_OUT<23> 29 70

45 46
30 CUMULUS_VSTM<24> F10 TXI24 TXO24 F9 MT_PANEL_OUT<24> 29 70
IN
30 CUMULUS_VSTM<25> G1 TXI25 TXO25 G2 MT_PANEL_OUT<25> 29 70
30 IN
CUMULUS_VSTM<26> G3 TXI26 TXO26 G4 MT_PANEL_OUT<26> 29 70
IN
30 CUMULUS_VSTM<27> G5 TXI27 TXO27 G6 MT_PANEL_OUT<27> 29 70
IN
30
IN CUMULUS_VSTM<28> G8 TXI28 TXO28 G7 MT_PANEL_OUT<28> 29 70
30 IN CUMULUS_VSTM<29> G10 TXI29 TXO29 G9 MT_PANEL_OUT<29> 29 70

30
IN CUMULUS_VSTM<30> H1 TXI30 TXO30 H2 MT_PANEL_OUT<30> 29 70
30 IN CUMULUS_VSTM<31> H3 TXI31 TXO31 H4 MT_PANEL_OUT<31> 29 70
30 CUMULUS_VSTM<32> J1 TXI32 TXO32 J2 MT_PANEL_OUT<32> 29 70

IN
30 CUMULUS_VSTM<33> J3 TXI33 TXO33 J4 MT_PANEL_OUT<33> 29 70
30 IN
CRITICAL CUMULUS_VSTM<34> K1 TXI34 TXO34 K2 MT_PANEL_OUT<34>
IN MT_PANEL_OUT<35> 29 70
J4040 MLB APN: 516S1174 30 IN CUMULUS_VSTM<35> K3 TXI35 TXO35 K4 29 70
FLEX APN: 516S1175 CUMULUS_VSTM<36> L1 TXI36 TXO36 L2 MT_PANEL_OUT<36>

MATCHES GRAPE_FLEX_ALT3 1.1.0 01/13/14
30 IN MT_PANEL_OUT<37> 29 70
CUMULUS_VSTM<37> L3 TXI37 TXO37 L4

35
F-ST-SM AA21-
36 30 IN MT_PANEL_OUT<38> 29 70
1 30 CUMULUS_VSTM<38> M1 M2
S034VA1 R4010 1 C4012 IN TXI38 TXO38
29 70
78.7K 33000PF 30 CUMULUS_VSTM<39> M3 TXI39 TXO39 M4 MT_PANEL_OUT<39>
69 30 PP3V0_S2R_GRAPE_HALL_FILT 1 2 GPIO_HALL2PMU_IRQ1_FILT OUT 30 69
1% 10%
IN 29 70
3 4 1/32W 6.3V
2 X5R
MF
01005
MT_PANEL_IN<29> 5 6 MT_PANEL_IN<14> 201 STINGER_FREQ J6 FREQ GAIN0 L6 =PP1V8_GRAPE_EXT_SW 29 30 72
70 30 OUT OUT 30 70 2
70 30 MT_PANEL_IN<28> 7 8 MT_PANEL_IN<13> 30 70
GAIN1 K6
OUT OUT
STINGER_SS L7 SS GAIN2 J7
B 70 30
70 30
OUT
OUT
MT_PANEL_IN<27>
MT_PANEL_IN<26>
9
11
10
12
MT_PANEL_IN<12>
MT_PANEL_IN<11>
OUT
OUT
30 70
30 70
B
MT_PANEL_IN<25> 13 14 MT_PANEL_IN<10> M8 PCTL0 K8
70 30 OUT OUT 30 70
DIDT=TRUE M9 SW PCTL1 K7
70 30 OUT MT_PANEL_IN<24> 15 16 MT_PANEL_IN<9> OUT 30 70 SWITCH_NODE=TRUE
STINGER_LX M10
70 30 OUT MT_PANEL_IN<23> 17 18 MT_PANEL_IN<8> OUT 30 70
PD* J9 GPIO_GRAPE2STINGER_SHDWN_L
70 30 OUT MT_PANEL_IN<22> 19 20 MT_PANEL_IN<7> OUT 30 70 IN 30
STINGER_COMP M6 COMP
70 30 OUT MT_PANEL_IN<21> 21 22 MT_PANEL_IN<6> OUT 30 70
70 30 MT_PANEL_IN<20> 23 24 MT_PANEL_IN<5> 30 70
SYNC J8 GPIO_GRAPE2STINGER_SYNC IN 30
OUT OUT
MT_PANEL_IN<19> 25 26 MT_PANEL_IN<4> 29 STINGER_FB K10 FBK_IN
70 30 OUT OUT 30 70
MT_PANEL_IN<18> 27 28 MT_PANEL_IN<3> EN N5 GPIO_GRAPE2STINGER_EN IN 30

70 30 OUT OUT 30 70
MT_PANEL_IN<17> 29 30 MT_PANEL_IN<2> 70 30 IN I2C_GRAPE_SCL_1V8 N2 SCL

70 30 OUT
MT_PANEL_IN<16> 31 32 MT_PANEL_IN<1>
OUT 30 70
R40111 70 30 BI I2C_GRAPE_SDA_1V8 N3 SDA STEP_CLOCK H10 IN 30
70 30 OUT OUT 30 70 3.09K
MT_PANEL_IN<15> MT_PANEL_IN<0> 1% CLK_GRAPE2STINGER_STEP
K9 FBK_GND
70 30
33 34 30 70
OUT OUT 1/20W
MF RDY/TMUX N4 30
IN
N8 SGND
201
37 38 2 GPIO_GRAPE2STINGER_RDY
AVSS PGND PBKG
STINGER_COMP_R
C6
F6
H5
N6
L8
L9
L10
A1
A10
C5
E5
H8
M7
N1
N10
C4013 1
33000PF
10%
6.3V
X5R 2
201
R4013
10K VOLTAGE=0V
29 STINGER_FB 1 2 GND_STINGER_FB
1%
1/32W
1 MF
R4012 01005
154K
1%
1/32W
A CRITICAL
MF
2 01005 SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
L4001 D4001
BOOST INPUT 10UH-20%-0.89A-228MOHM NSR10F40NXT5G GRAPE: STINGER & CONN
VOLTAGE=21.2V
72 30 29 =PPVCC_MAIN_GRAPE 2
VLS4012E-SM
1 A K PPVDD_STINGER_BOOST 29 69
DRAWING NUMBER SIZE
DSN2 Apple Inc. 051-0301

REVISION
D
1 C4015 1 C4014 1 C4017 R
10UF 10UF 10UF BRANCH B.0.0
20% 20% 20%
2 6.3V 2 2 25V
X5R-CERM NOTICE OF PROPRIETARY PROPERTY:
0402-10 0603 0603
X5R X5R-CERM THE INFORMATION CONTAINED HEREIN IS THE
25V PROPRIETARY PROPERTY OF APPLE INC.
PAGE 40 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_5_HEAD

TABLE_5_ITEM
343S00018 2 IC,CUMULUS,C1,OPTION1 U4100,U4150 CRITICAL
72 30 29 =PP1V8_GRAPE_EXT_SW =PP1V8_GRAPE_EXT_SW 29 30 72
R4152 =PP1V8_GRAPE_EXT_SW
R41021 1
4.7K
72 30 29
4.7K 1%
1% 1/32W
1/32W MF 1 1
MF 01005 R4180 R4181
01005 2
2 4.7K 4.7K
1% 1%
30 CUMULUS_M_BCFG_RTCK JTAG_CUMULUS_S_TMS 30
1/32W
MF
1/32W
MF
01005
70 30 JTAG_CUMULUS_M_TMS CUMULUS_S_BCFG_RTCK 30 2 01005 2
D R41041 1
R4154 70 30 29 I2C_GRAPE_SCL_1V8 D
4.7K 4.7K 70 30 29 I2C_GRAPE_SDA_1V8
1% 1%
1/32W 1/32W
MF 01005
01005
2 2 MF
MASTER CUMULUS SLAVE CUMULUS

72 30 29 =PP5V25_GRAPE =PP1V8_GRAPE_EXT_SW 29 30 72 72 30 29 =PP5V25_GRAPE =PP1V8_GRAPE_EXT_SW 29 30 72
1 C4100 1 C4101
1 C4106 1 C4150
1UF 100PF 0.1UF 1UF 1 C4156
20% 5% 20% 20%
10V
0.1UF
4V 2 X5R 20%
2 10V 16V
2 NP0-C0G 2 X5R
X5R 01005 01005
0201 2 4V
X5R
0201
01005
PPVDDCORE_CUMULUS_S =PP1V8_GRAPE_EXT_SW 29 30 72
VOLTAGE=1.8V
=PP1V8_GRAPE_EXT_SW 29 30 72 PPVDDANA_CUMULUS_S
PPVDDCORE_CUMULUS_M VOLTAGE=1.8V 1 C4159 1 C4158
VOLTAGE=1.8V
PPVDDANA_CUMULUS_M
1 C4108 1 C4109 1 C4110 1 C4155 1 C4152 1 C4153 1 C4154 0.1UF 100PF
4.7UF 0.1UF 100PF 56PF 2.2UF 2.2UF 56PF 20% 5%
VOLTAGE=1.8V
20% 20% 5% 5% 20% 20% 5% 2 4V
X5R 2 6.3V
VDDANA B1
VDDCORE C1
VDDH C8
C5
F4
VDDLDO A1
1 1 1 1 6.3V 4V 6.3V 6.3V 4V 4V 6.3V 01005
C4105 C4102 C4103 C4104 2
402 X5R-
2 X5R
01005
2 2 NP0-C0G 2 X5R-CERM 2 X5R-CERM
0201
2 NP0-C0G 01005
VDDANA B1
VDDCORE C1
VDDH C8
C5
F4
VDDLDO A1
56PF 2.2UF 2.2UF 56PF CERM1
01005 01005 0201 01005 CERM
5% 20% 20% 5% CERM
2
6.3V 4V
2 X5R-CERM
4V
2 X5R-CERM 2
6.3V VDDIO
01005 0201 01005
NP0-C0G
0201
NP0-C0G
VDDIO
70 29
70 29 IN MT_PANEL_IN<15> B9 IN0_0 U4150 VSTM_0 E9 CUMULUS_VSTM<20> OUT 29
70 29 IN MT_PANEL_IN<0> B9 IN0_0 U4100 VSTM_0 E9 CUMULUS_VSTM<0> OUT 29 IN MT_PANEL_IN<16> B8 IN1_0 CUMULUS-C1 VSTM_1 E5 CUMULUS_VSTM<21> OUT 29
70 29 MT_PANEL_IN<1> B8 IN1_0 CUMULUS-C1 VSTM_1 E5 CUMULUS_VSTM<1> 29 MT_PANEL_IN<17> A9 IN2_0 WLBGA VSTM_2 F7 CUMULUS_VSTM<22> 29
IN OUT IN OUT
C 70 29
70 29
IN
IN
MT_PANEL_IN<2>
MT_PANEL_IN<3>
A9
B7
IN2_0
IN3_0
WLBGA
OMIT_TABLE
VSTM_2
VSTM_3
F7
E6
CUMULUS_VSTM<2>
CUMULUS_VSTM<3>
OUT
OUT
29
29
IN
IN
MT_PANEL_IN<18>
MT_PANEL_IN<19>
B7
B6
IN3_0
IN4_0
OMIT_TABLE VSTM_3
VSTM_4
E6
E7
CUMULUS_VSTM<23>
CUMULUS_VSTM<24>
OUT
OUT
29
29
C
70 29 MT_PANEL_IN<4> B6 IN4_0 VSTM_4 E7 CUMULUS_VSTM<4> 29 MT_PANEL_IN<20> A8 IN5_0 VSTM_5 F8 CUMULUS_VSTM<25> 29
IN OUT IN OUT
70 29 IN MT_PANEL_IN<5> A8 IN5_0 VSTM_5 F8 CUMULUS_VSTM<5> OUT 29 70 29 IN MT_PANEL_IN<21> B5 IN6_0 VSTM_6 G9 CUMULUS_VSTM<26> OUT 29
70 29 IN MT_PANEL_IN<6> B5 IN6_0 VSTM_6 G9 CUMULUS_VSTM<6> OUT 29 IN MT_PANEL_IN<22> B4 IN7_0 VSTM_7 D6 CUMULUS_VSTM<27> OUT 29
70 29 IN MT_PANEL_IN<7> B4 IN7_0 VSTM_7 D6 CUMULUS_VSTM<7> OUT 29 IN MT_PANEL_IN<23> A7 IN8_0 VSTM_8 D7 CUMULUS_VSTM<28> OUT 29
A7 D7 70 29 B3 D8
70 29 IN MT_PANEL_IN<8> IN8_0 VSTM_8 CUMULUS_VSTM<8> OUT 29 70 29 IN MT_PANEL_IN<24> IN9_0 VSTM_9 CUMULUS_VSTM<29> OUT 29
70 29 MT_PANEL_IN<9> B3 IN9_0 VSTM_9 D8 CUMULUS_VSTM<9> 29 70 MT_PANEL_IN<25> A6 IN10_0 VSTM_10 F9 CUMULUS_VSTM<30> 29

IN OUT 70 29
9
IN OUT
70 29 MT_PANEL_IN<10> A6 IN10_0 VSTM_10 F9 CUMULUS_VSTM<10> 29
2 MT_PANEL_IN<26> A3 IN11_0 VSTM_11 D5 CUMULUS_VSTM<31> 29
IN OUT IN OUT
70 29 MT_PANEL_IN<11> A3 IN11_0 VSTM_11 D5 CUMULUS_VSTM<11> 29 MT_PANEL_IN<27> A5 IN12_0 VSTM_12 F6 CUMULUS_VSTM<32> 29
IN OUT IN OUT
70 29 MT_PANEL_IN<12> A5 IN12_0 VSTM_12 F6 CUMULUS_VSTM<12> 29 MT_PANEL_IN<28> A4 IN13_0 VSTM_13 F5 CUMULUS_VSTM<33> 29
IN OUT IN OUT
70 29 IN MT_PANEL_IN<13> A4 IN13_0 VSTM_13 F5 CUMULUS_VSTM<13> OUT 29 IN MT_PANEL_IN<29> B2 IN14_0 VSTM_14 G4 CUMULUS_VSTM<34> OUT 29
70 29 IN MT_PANEL_IN<14> B2 IN14_0 VSTM_14 G4 CUMULUS_VSTM<14> OUT 29 NC_CUMULUS_S_IN14_1 A2 IN14_1 VSTM_15 E8 CUMULUS_VSTM<35> OUT 29
NO_TEST=TRUE
NC_CUMULUS_M_IN14_1 A2 IN14_1 VSTM_15 E8 CUMULUS_VSTM<15> OUT 29 VSTM_16 G8 CUMULUS_VSTM<36> OUT 29
NO_TEST=TRUE
VSTM_16 G8 CUMULUS_VSTM<16> OUT 29 TP_CUMULUS_S_CS_L
70 E4 H_CS* VSTM_17 G7 CUMULUS_VSTM<37> OUT 29
70 6 SPI_GRAPE_CS_L E4 H_CS* VSTM_17 G7 CUMULUS_VSTM<17> 29 29 CLK_GRAPE2STINGER_STEP F1 H_INT* VSTM_18 G6 CUMULUS_VSTM<38> 29

IN OUT OUT OUT
70 6 OUT GPIO_GRAPE2SOC_IRQ_L F1 H_INT* VSTM_18 G6 CUMULUS_VSTM<18> OUT 29 29 OUT
GPIO_GRAPE2STINGER_SYNC D3 H_SCLK VSTM_19 G5 CUMULUS_VSTM<39> OUT 29
70 6 IN SPI_GRAPE_SCLK D3 H_SCLK VSTM_19 G5 CUMULUS_VSTM<19> OUT 29 29 OUT GPIO_GRAPE2STINGER_RDY D2 H_SDI

70 6 IN SPI_GRAPE_MOSI
SPI_GRAPE_MISO D2 H_SDI 29 OUT
GPIO_GRAPE2STINGER_EN E1 H_SDO GPIO_1/CK G1 CUMULUS_M2S_CLK 30 70
E1 G1 CUMULUS_M2S_CLK
R4159 1 D4 CUMULUS_M2S_SDA
70 6 OUT H_SDO GPIO_1/CK 30 70 4.7K GPIO_2/SD 30 70
=PP1V8_GRAPE_EXT_SW GPIO_2/SD D4 CUMULUS_M2S_SDA 30 70

1% NC_CUMULUS_S_TCK C4 JTAG_TCK GPIO_3 F2 TP_CUMULUS_S_GPIO_3 70
72 30 29 NO_TEST=TRUE
TP_JTAG_CUMULUS_M_TCK C4 F2 DISPLAY_SYNC MF NC_CUMULUS_S_TDI C3 F3 GPIO_GRAPE2STINGER_SHDWN_L
70 JTAG_TCK GPIO_3 IN 6 70 01005 NO_TEST=TRUE
JTAG_TDI GPIO_4 OUT 29
1/32W
70 TP_JTAG_CUMULUS_M_TDI C3 JTAG_TDI GPIO_4 F3 CUMULUS_M_GPIO_4 2 NC_CUMULUS_S_TDO E2 JTAG_TDO
R41011 70 30 29 BI I2C_GRAPE_SDA_1V8 E2 JTAG_TDO 30 JTAG_CUMULUS_S_TMS
NO_TEST=TRUE
C6 JTAG_TMS TM_ACS* C2 NC_CUMULUS_S_TM_ACS_L
4.7K C6
NO_TEST=TRUE NO_TEST=TRUE
1% 70 30 JTAG_CUMULUS_M_TMS JTAG_TMS TM_ACS* C2 NC_CUMULUS_M_TM_ACS_L TM_OVR G3
1/32W
MF
01005 TM_OVR G3 I2C_GRAPE_SCL_1V8 OUT 29 30 70
30 CUMULUS_S_BCFG_RTCK E3 BCFG_RTCK
2 CUMULUS_M_BCFG_RTCK E3 BCFG_RTCK CLK_SOC2GRAPE_32K D1 CLKIN/RESET*
B 70 69 30 9 IN
30
CLK_SOC2GRAPE_32K D1 CLKIN/RESET*
70 69 30 9
70 30 6
IN
IN GPIO_SOC2GRAPE_RESET_L D9 RSTOVR* B
70 30 6 IN GPIO_SOC2GRAPE_RESET_L D9 RSTOVR* 1 R4106 1 R4110 GND
100K 4.7K
GND 5% 1%
1/32W
C7
C9
G2
MF 1/32W
MF
01005 01005
C7
C9
G2
2 2
72 =PP1V8_S2R_GRAPE_EXTERNAL_SW
1 C4196
72 29 =PPVCC_MAIN_GRAPE 1.0UF
20%
1 2 6.3V
X5R
C4190 0201-1
HALL EFFECT 0.1UF

CRITICAL
1
2
FL4124 VDD
10%
240-OHM-25%-0.20A-1.0DCR 16V U4190
62 OUT GPIO_HALL2PMU_IRQ1 1 2 GPIO_HALL2PMU_IRQ1_FILT IN 29 69 X5R-CERM SLG5AP1443V
01005 0201 TDFN
VCC_MAIN_GRAPE_RAMP 7 CAP D 3
FL4125
70-OHM-300MA GPIO_SOC2GRAPE_EXT_SW_ON 2 5 PP1V8_GRAPE_EXT_SW
A VOLTAGE=3.0V
6 IN
1
ON
GND
S
CRITICAL
69 72
19 =PP3V0_S2R_HALL
1 01005-1 2 PP3V0_S2R_GRAPE_HALL_FILT CRITICAL R4194 1 PAGE TITLE
72 29 69
C4193 1 C4195
GRAPE: CUMULUS
8
100K 10UF
4700PF 5% 20%
1 C4125 10% 1/32W DRAWING NUMBER SIZE
10V 2 MF 2 6.3V
X5R
27PF X7R
201 2 01005 0402-10 051-0301 D
5%
2 16V
Apple Inc. REVISION
NP0-C0G R
01005
BRANCH B.0.0
LAYOUT NOTE:
PAGE 41 OF 155
PUT THERMAL VIAS AROUND U4100 IN CASE OF SHORTED CONDITION II NOT TO REPRODUCE OR COPY IT
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_ALT_HEAD

PART NUMBER
DISPLAY CONNECTOR
TABLE_ALT_ITEM
131S00011 131S0641 ? C4550, ECT RDAR://PROBLEM/15682101
D D
DISPLAY CONNECTOR
CRITICAL
J4500 MLB APN: 516S1243
BM15P1.0-60DS-0.35V FLEX APN: 516S1244
F-ST-SM
MATCHES FLEX_DISPLAY_EDP 4.0.0 02/18/14
61 62
1 2 I2C_MESA_SDA_1V8_FILT BI 33
69 33 OUT GPIO_MESA2SOC_IRQ_FILT 3 4 I2C_MESA_SCL_1V8_FILT IN 33

5 6
69 33 SPI_MESA_MISO_FILT 7 8 GPIO_BTN_HOME_CONN_L 33 69
OUT OUT
69 33 IN SPI_MESA_MOSI_FILT 9 10 MESA_BOOST_ENABLE_FILT OUT 33 69
69 33 IN SPI_MESA_SCLK_FILT 11 12
EDP_DATA_EMI_CONN_N<3>
13 14 32 70
IN
69 33 PP1V825_S2R_MESA_FILT 15 16 EDP_DATA_EMI_CONN_P<3> IN 32 70
17 18
69 33 PP11V3_MESA_FILT
19 20 EDP_DATA_EMI_CONN_N<2> 32 70
IN
21 22 EDP_DATA_EMI_CONN_P<2>
C 69 33
PP3V1_S2R_MESA_FILT 23 24
IN 32 70
C
25 26 EDP_DATA_EMI_CONN_N<1> IN 32 70
32 OUT EDP_HPD_EMI_CONN 27 28 EDP_DATA_EMI_CONN_P<1> IN 32 70

29 30
NC EDP_DATA_EMI_CONN_N<0>
69 32 PPLED_BACK_REG_B 31 32
EDP_DATA_EMI_CONN_P<0> IN 32 70
33 34 32 70
IN
NC 35 36
EDP_AUX_EMI_CONN_N
69 32 PPLED_BACK_REG_A 37 38
EDP_AUX_EMI_CONN_P IN 32
NC 39 40
IN 32
41 42
LED_IO_1_B
69 63 31 OUT LED_IO_1_A 43 44
LED_IO_2_B OUT 31 63 69
69 63 31 OUT LED_IO_2_A 45 46
LED_IO_3_B OUT 31 63 69
69 63 31 OUT LED_IO_3_A 47 48
LED_IO_4_B OUT 31 63 69
69 63 31 OUT LED_IO_4_A 49 50
OUT 31 63 69
LED_IO_5_A 51 52 LED_IO_5_B
69 63 31 OUT LED_IO_6_B OUT 31 63 69
69 63 31 OUT LED_IO_6_A 53 54
OUT 31 63 69
55 56
69 32 31 PPVCC_MAIN_LCD_SW_CONN 57 58 PPVCC_MAIN_LCD_SW_CONN 31 32 69
59 60
63 64
SWAPPED LED STRING A AND B INTENTIONALLY TO EASE ROUTING

B B
69 63 31 OUT LED_IO_1_A
69 63 31 OUT LED_IO_2_A
69 63 31 OUT LED_IO_3_A
69 63 31 OUT LED_IO_4_A
69 63 31 OUT LED_IO_5_A
69 63 31 OUT LED_IO_6_A
1 C4555 1 C4554 1 C4553 1 C4552 1 C4551 1 C4550
56PF 56PF 56PF 56PF 56PF 56PF
2% 2% 2% 2% 2% 2%
50V 50V 50V 50V 50V 50V
2 NP0-C0G-CERM 2 NP0-C0G-CERM 2 NP0-C0G-CERM 2 NP0-C0G-CERM 2 NP0-C0G-CERM 2 NP0-C0G-CERM
0201 0201
0201 0201 0201 0201
69 63 31 OUT LED_IO_1_B
69 63 31 OUT LED_IO_2_B
69 63 31 OUT
LED_IO_3_B
69 63 31 OUT LED_IO_4_B
69 63 31 OUT LED_IO_5_B
69 63 31 OUT
LED_IO_6_B
1 C4565 1 C4564 1 C4563 1 C4562 1 C4561 1 C4560
56PF 56PF 56PF 56PF 56PF 56PF
2% 2% 2% 2% 2%
A 50V
2 NP0-C0G-CERM
0201
50V
2 NP0-C0G-CERM
0201
50V
2 NP0-C0G-CERM
0201
2
0201 NP0-
C0G-CERM
50V
2 NP0-C0G-CERM
0201
50V
2 NP0-C0G-CERM
0201 SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
50V
2% DISPLAY: CONNECTOR
DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
PAGE45 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
EDP CONNECTOR SUPPORT PART NUMBER
155S0914
ALTERNATE FOR
PART NUMBER
155S0897
BOM OPTION
?
REF DES COMMENTS:
TABLE_ALT_HEAD
TABLE_ALT_ITEM
72 =PPVCC_MAIN_LCD L4602, ECT RDAR://PROBLEM/15954071
1 C4640 1
0.1UF
C4639
10% 0.1UF
10%
2 16V
X5R-CERM 2 16V
1
0201 X5R-CERM
0201
VDD
U4600
CRITICAL
SLG5AP304V
D R4607 LCD_RAMP 7 CAP TDFN
D
CRITICAL
3 L4601
FERR-120-OHM-1.5A D
0.00 2 2 5
VOLTAGE=4.7V
1 2
VOLTAGE=4.7V
62 IN GPIO_PMU2LCD_PWREN 1 GPIO_LCD_PWREN_R ON S 69 PPVCC_MAIN_LCD_SW PPVCC_MAIN_LCD_SW_CONN 31 69
OMIT_TABLE 0402A
0%
1/32W
GND
MF CRITICAL 1
01005 1
R4605 C4641 1 1 C4603 1 C4602 C4630 C4632
8
1 1
R4601 15PF
100K 4700PF 51.1K 0.1UF 10UF 100PF 5%
5% 10%
10V
LAYOUT NOTE: 1% 10% 20% 5% 2 16V
1/32W
MF 2 X7R PUT THERMAL VIAS AROUND U4600 IN CASE OF SHORTED CONDITION 1/32W 2 16V
X5R-CERM 2 6.3V
X5R 2
16V
01005
NP0-C0G-CERM
01005
201 MF 0201 0402-10
2 01005 2 01005 NP0-C0G
TABLE_5_HEAD

TABLE_5_ITEM
353S4272 1 IC,SLG5AP1423V U4600 CRITICAL ?
CRITICAL HPD VOLTAGE DIVIDER 2.5V TO 1.8V

9 EDP_AUX_P C4650 1 2 0.1UF EDP_AUX_EMI_P L4642 EDP_AUX_EMI_CONN_P 31
L4690
IN OUT
01005 6.3V 20% X5R-CERM 2 3 R4690 240-OHM-25%-0.20A-1.0DCR
7.5K 2
EDP_AUX_N 0.1UF 4 31 IN EDP_HPD_EMI_CONN 1 69 EDP_HPD_EMI 1 2 EDP_HPD OUT 9
9 IN
C4651 1 2 EDP_AUX_EMI_N 1 EDP_AUX_EMI_CONN_N OUT 31 5%
01005
01005 6.3V 20% X5R-CERM SYM_VER-2

TAM0605-4SM MF
1/32W
1
R4641 1 3.25-OHM-0.1A-2.4GHZ 01005 1
R4691
R4643
100K 100K 20.0K
5% 5% 5%
1/32W 1/32W 1/32W
MF MF
C 2 01005
MF
2 01005 2 01005 C
CRITICAL
70 9 IN EDP_DATA_N<0> C4643 1 2 0.1UF 70 EDP_DATA_EMI_N<0> L4612 EDP_DATA_EMI_CONN_N<0> OUT 31 32 70
01005 6.3V 20% X5R-CERM 2 3
70 9 IN EDP_DATA_P<0> C4642 1 2 0.1UF 70 EDP_DATA_EMI_P<0> 1 4

EDP_DATA_EMI_CONN_P<0> OUT 31 32 70
01005 6.3V 20% X5R-CERM TAM0605-4SM
SYM_VER-2
3.25-OHM-0.1A-2.4GHZ
CRITICAL
70 9 EDP_DATA_N<1> C4644 1 2 0.1UF 70 EDP_DATA_EMI_N<1> L4622 EDP_DATA_EMI_CONN_N<1> 31 32 70
IN OUT
01005 6.3V 20% X5R-CERM 2 3
EDP_DATA_P<1> C4645 1 2 0.1UF 70 EDP_DATA_EMI_P<1> 1 4 EDP_DATA_EMI_CONN_P<1>

70 9 IN OUT 31 32 70
01005 6.3V 20% X5R-CERM SYM_VER-2
TAM0605-4SM
3.25-OHM-0.1A-2.4GHZ
CRITICAL
70 9 IN EDP_DATA_N<2> C4646 1 2 0.1UF 70 EDP_DATA_EMI_N<2> L4632 EDP_DATA_EMI_CONN_N<2> OUT 31 32 70

01005 6.3V 20% X5R-CERM 2 3
EDP_DATA_P<2> C4647 1 2 0.1UF EDP_DATA_EMI_P<2> 1 4

70 9 IN 70 EDP_DATA_EMI_CONN_P<2> OUT 31 32 70
01005 6.3V 20% X5R-CERM SYM_VER-2
TAM0605-4SM
R4680 3.25-OHM-0.1A-2.4GHZ
1.00M2
1 EDP_DATA_EMI_CONN_N<0> 31 32 70
B 01005
70 9 EDP_DATA_N<3> 0.1UF 70 EDP_DATA_EMI_N<3>
CRITICAL
L4602 EDP_DATA_EMI_CONN_N<3> 31 32 70
B
IN OUT
01005 6.3V 20% X5R-CERM 2 3
R4681 C4648 1 2
1.00M2 EDP_DATA_P<3> 0.1UF EDP_DATA_EMI_P<3> 1 4 EDP_DATA_EMI_CONN_P<3>
1 EDP_DATA_EMI_CONN_P<0> 31 32 70
70 9 IN 70
OUT 31 32 70
01005
C4649 X5R-CERM SYM_VER-2
TAM0605-4SM
01005 6.3V1 220% 3.25-OHM-0.1A-2.4GHZ
R4682
1.00M2
1 EDP_DATA_EMI_CONN_N<1> 31 32 70
01005
CRITICAL
R4683 L4680
1.00M2 120-OHM-25%-450MA
1 EDP_DATA_EMI_CONN_P<1> 31 32 70
VOLTAGE=20.4V
72 =PPLED_REG_B 1
0201
2 PPLED_BACK_REG_B 31 69
01005
1 C4680 1 C4681
8.2PF 56PF
R4684
1
1.00M2 2 2
EDP_DATA_EMI_CONN_N<2> 31 32 70 201 C0G- 0201 NP0-
01005 CERM 50V C0G-CERM 50V
+/-0.5PF 2%
R4685
1
1.00M2 CRITICAL
EDP_DATA_EMI_CONN_P<2> 31 32 70
01005
L4685
120-OHM-25%-450MA
A 72 =PPLED_REG_A 1
0201
2
VOLTAGE=20.4V
PPLED_BACK_REG_A 31 69 SYNC_MASTER=N/A SYNC_DATE=N/A A
PAGE TITLE
R4686
1
1.00M2
EDP_DATA_EMI_CONN_N<3> 31 32 70
1 C4685
8.2PF
1 C4686
56PF
DISPLAY: EDP SUPPORT
2% DRAWING NUMBER SIZE
01005
2
201 C0G-
2 50V
NP0-C0G-CERM
0201 Apple Inc. 051-0301
REVISION
D
CERM 50V R
R4687 +/-0.5PF BRANCH B.0.0
1
1.00M2 NOTICE OF PROPRIETARY PROPERTY:
EDP_DATA_EMI_CONN_P<3> 31 32 70
01005 PROPRIETARY PROPERTY OF APPLE INC.
PAGE46 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_5_HEAD

TABLE_5_ITEM
155S00018 3 FERRITE,80OHM,25%,500MA,0.18DCR FL4742,FL4744,FL4750 CRITICAL
MESA & HOME

MOJAVE
BUTTON
USING A1 BECAUSE NAVAJO NEEDS 11V3
D CRITICAL
L4770 VOLTAGE=13V
U4770
LM3638A1
D
1.0UH-20%-0.4A-0.636OHM DIDT=TRUE BGA
SWITCH_NODE=TRUE
B1 SW CRITICAL
72 =PPVCC_MAIN_MESA 1 2 MOJAVE_LX
0403 VOLTAGE=11.3V
A2 VIN VOUT C3 PP11V3_MESA 33
C4770 1
10UF =PP3V1_S2R_MESA B2 EN_M
20% 72 33 1 C4772 1 C4773
6.3V
X5R 2 33 MESA_BOOST_ENABLE A3 EN_S 100PF 2.2UF
0402-10 VOLTAGE=11.9V
5% 20%
EN_S HAS AN INTERNAL 200K PULL DOWN C2 LDOIN 16V 25V
PMID C1 PP11V9_MESA 2 NP0-C0G 2 X5R-CERM
A1 PGND
B3 AGND
01005 0402-1
1 C4771
2.2UF
20%
2 25V
X5R-CERM
0402-1
OMIT_TABLE
FL4742
80-OHM-25%-500MA
VOLTAGE=11.3V
33 PP11V3_MESA 1 2 PP11V3_MESA_FILT 31 69
0201
1 C4742 1 C4743
1UF 100PF
10% 5%
2 25V
X5R 2 16V
NP0-C0G
402 01005
C OMIT_TABLE
FL4744
C
80-OHM-25%-500MA
VOLTAGE=3.1V
72 33 =PP3V1_S2R_MESA 1 2 PP3V1_S2R_MESA_FILT 31 69
0201
1 C4744 1 C4745
1.0UF 100PF
20% 5%
2 6.3V
X5R
16V
2 NP0-C0G
0201-1 01005
U4750
OMIT_TABLE
FL4750
HOME BUTTON FILTERS FL4710
LP5907UVX-1.825-S 80-OHM-25%-500MA 240-OHM-25%-0.20A-1.0DCR R4711
DSBGA 1 2 100
A1 VIN VOUT A2 PP1V825_S2R_MESA PP1V825_S2R_MESA_FILT 31 69
62 6 5 GPIO_BTN_HOME_L 1 2 GPIO_BTN_HOME_CONN_R_L 1 2 GPIO_BTN_HOME_CONN_L 31 69
OUT IN
0201 01005 5%
1 1 C4752 1 C4753
C4750 1 B1 VEN CRITICAL C4751 1.0UF 100PF 1
1/20W
MF
1.0UF GND 2.2UF
20% 20% 5% C4711 201
20% 6.3V 6.3V
2 X5R 16V
2 NP0-C0G 27PF
5%
B2
6.3V 2 2 X5R
X5R 0201-1 0201-1 01005 2 16V
0201-1 NP0-C0G
01005
FL4706
70-OHM-300MA
B 4 IN =I2C_SOC2MESA_SCL_1V8 1
01005-1
2 I2C_MESA_SCL_1V8_FILT
CKPLUS_WAIVE=I2C_PULLUP OUT 31 B
FL4701
70-OHM-300MA
FL4707 6 IN SPI_MESA_SCLK 1 2 SPI_MESA_SCLK_FILT OUT 31 69
70-OHM-300MA 01005-1
4 BI =I2C_SOC2MESA_SDA_1V8 1 2 I2C_MESA_SDA_1V8_FILT BI 31 1
01005-1 CKPLUS_WAIVE=I2C_PULLUP R4701
100K
5%
1/32W
MF
2 01005 TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
155S00017 155S0755 RDAR://PROBLEM/15807137

FL4702 FL3910,FL3911,FL4124,L4690,FL4710
FL4705 70-OHM-300MA
TABLE_ALT_HEAD
6 IN SPI_MESA_MOSI 1 2 SPI_MESA_MOSI_FILT OUT 31 69 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
33 MESA_BOOST_ENABLE 1 2 MESA_BOOST_ENABLE_FILT IN 31 69
01005-1 PART NUMBER
01005 TABLE_ALT_ITEM
120-OHM-25%-250MA-0.5DCR 155S00018 155S0664 RDAR://PROBLEM/15796569
FL2800,FL2802,FL2803,FL2861,FL2871,FL2881,FL2891,FL4742,FL4744,FL4750,FL7900
A FL4700
FL4703
70-OHM-300MA SYNC_MASTER=N/A SYNC_DATE=N/A A
ACTIVE HIGH INTERRUPT PAGE TITLE
6 OUT GPIO_MESA2SOC_IRQ 1
01005
2 GPIO_MESA2SOC_IRQ_FILT IN 31 69
6 OUT SPI_MESA_MISO 1
01005-1
2 SPI_MESA_MISO_FILT IN 31 69
MESA: SUPPORT
DRAWING NUMBER SIZE
120-OHM-25%-250MA-0.5DCR
REVISION
R
BRANCH
B.0.0
SHEET
33 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
J82 - ROTTERDAM
D PP4800 SM
1 UART_SOC2ROTTERDAM_TX
D
P4MM PP 6 34
PP4801
P4MM
SM
1 UART_ROTTERDAM2SOC_TX
PP 6 34
PP4802
P4MM
SM
1 UART_SOC2ROTTERDAM_RTS_L
PP 6 34
PP4803SM 1 UART_ROTTERDAM2SOC_RTS_L
P4MM PP 6 34
PP4804
P4MM
SM
1 GPIO_SOC2ROTTERDAM_EN
PP 8 34
PP4806
P4MM
SM
1 GPIO_SOC2ROTTERDAM_DWLD_REQ
PP 8 34
72 =PPVCC_MAIN_ROTTERDAM
C4800 1
4.7UF
20%
10V
X5R-CERM 2 VOLTAGE=1.8V
0402
PPVDD_ROTTERDAM
72 34 =PP1V8_S2R_ROTTERDAM VOLTAGE=1.8V
C C4801
1UF
1
NC NC
34 PPSVDD_ROTTERDAM C
C6
C7
D7
D3
VUP G2
TVDD E7
SVDD_IN G1
SVDD B7
ESE_VDD C5
20%
10V
1 C4820 1 C4810 1 C4811
X5R 2 0.1UF 1UF 0.1UF
VDD/RF_IF_VDD
VBAT
VDHF
PVDD
0201 20% 20% 20%
6.3V 10V 6.3V
72 34 =PP1V8_S2R_ROTTERDAM 2 X5R-CERM 2 X5R 2 X5R-CERM
NOSTUFF 01005 0201 01005
1
R4800
100K
5%
1/32W U4800
MF
2 01005 PN65V
34 8 GPIO_SOC2ROTTERDAM_EN UFLGA
D1 IRQ OMIT_TABLE SIM_SWIO A4
34 8 GPIO_SOC2ROTTERDAM_DWLD_REQ NC NC
B3 SVDD_REQ SIM_VCC A5
NOSTUFF NC NC
1 34 8 IN GPIO_SOC2ROTTERDAM_DWLD_REQ A1 DWL SIM_PMU_VCC B5
NC
R4801 A2 F2
100K NC CLK_REQ TX_PWR_REQ NC
5% A3 CLK_XTAL1
1/32W NC ESE_DWPM_DBG D5
MF 34 6 IN UART_SOC2ROTTERDAM_TX C1 RX NC
2 01005 D2 ESE_DWPS_DBG E5 NC
34 6 OUT UART_ROTTERDAM2SOC_TX TX
UART_SOC2ROTTERDAM_RTS_L B1
34 6 IN CTS G7
ANT1 NC
34 6 OUT UART_ROTTERDAM2SOC_RTS_L B2 RTS
F6
E1 VEN RXP/RF_CLK_RX NC
34 8 IN GPIO_SOC2ROTTERDAM_EN G3
TX1 NC
PPSVDD_ROTTERDAM E3 SMX_RST* TX2 G5
34
NC
E4 SMX_CLK RXN/RF_CLK_RX F5
NC NC
NC
F4 ESE_IO1 ANT2 G6 NC
E6 ESE_IO2 VMID F7
NC NC
A7 ESE_IO3
NC RF_CLK_TX F1
A6 NC
B NC
C3
ESE_IO4
XTAL2
RF_DATA_IO B4 NC B
NC
TVSS
PVSS
VSS
GND
GND
GND
GND
GND
E2
B6
C4
D4
D6
F3
G4
C2
A A
PAGE TITLE
ROTTERDAM DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
B.0.0
BRANCH
TABLE_5_HEAD PROPRIETARY PROPERTY OF APPLE INC.
TABLE_5_ITEM
48 OF 155
338S00043 1 IC,ROTTERDAM,MP,UFLGA49 U4800 CRITICAL SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
AP INTERFACE & DEBUG CONNECTOR

CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSES ONLY - NOT A CHANGE REQUEST.
DEBUG CONNECTOR
PP_BATT_VCC
IN 35 44 53 68 73
NOSTUFF
D J5006 D
TEST POINTS PROBE POINTS AXE654124
56
M-ST-SM
55
PP5000 2 1
TP5000 1 50_BB_HSIC_STROBE TP5009 1 BB_JTAG_RST_L P4MM
A 39 68
A 35 39 SM
TP-P5 TP-P5 1 SLEEP_CLK_32K 37 39
4 3
PP
6 5
PP5001 8 7
TP5001
A 1
50_BB_HSIC_DATA
39 68
TP5010
A 1 BB_JTAG_TCK 35 39 P4MM
TP-P5 TP-P5 SM 1 BB_EEPROM_SCL 39 35 BB_JTAG_RST_L 10 9 PP_LDO11 35 36 38 39 40 42 43 44 73
OUT IN
PP 39 40
68 37 RF_PMIC_RESET_L 12 11
OUT NC BT_WAKE
PP5002 68 37 RADIO_ON_L 14 13
OUT
A
TP5002 1 BB_DEBUG_ERROR A
TP5011 1 BB_JTAG_TMS P4MM1 16 15
TP-P5
40
TP-P5
35 39
SM BB_EEPROM_SDA
NC PP_LDO5
BB_USB_VBUS 18 17
PP 39 40 68 39 OUT NC WLAN_REG_ON
A PP5003 39 35 90_BBUSB_N 20 19 RFFE1_DATA 35 40 44 45 46 47 48 49
BI BI
A TP5012 1 BB_JTAG_TDO P4MM1 22 21
TP5003 1 PS_HOLD_PMIC 35 37 TP-P5
35 39 SM ET_DAC_P
39 35 BI 90_BBUSB_P RFFE1_CLK BI 35 40 44 45 46 47 48 49
TP-P5 RESET_1V8_L 24 23 PMIC_RESOUT_L

A PP 40 44 68 OUT IN 35 37 39
PP5004 BB_JTAG_TCK 26 25 RFFE2_DATA
A TP5013 1 BB_JTAG_TDI
39 35 OUT BI 35 40 50 51 53
28 27
TP5004 1 PMIC_RESOUT_L 35 39 1 ET_DAC_N 39 35 OUT BB_JTAG_TMS
TP-P5
35 37 39 A TP-P5 SM
40 44 39 35 BB_JTAG_TDO 30 29 BB_HOST_RDY
40 68
PP IN IN
A P4MM BB_JTAG_TDI 32 31
TP5014 BB_JTAG_TRST_L 39 35 OUT NC BT_REG_ON BB_WAKE_HOST
TP5005 1 MDM_CLK A 1 35 39 39 35 BB_JTAG_TRST_L 34 33 40 68
TP-P5 PP_LDO6 OUT IN
37 39
36 35
A TP-P5 TP5029 1 RTCLK NC RFFE2_CLK BI 35 40 50 51 53
BB_DEBUG_STATUS A TP-P5
36 69 71 73
38 37 BB_RESET_DET_L IN 40 68
PP_LDO11 A
TP5015 1 40 39 BB_SIM_CLK
TP5006 1 35 36 38 39 40 42 TP-P5
40 37 35 OUT PS_HOLD_PMIC
NC
TP-P5 43 44 73 BB_UART_TXD 42 41 BB_SIM_DATA
A 68 40 IN NC
A BOOT_HSIC BB_UART_RXD 44 43 BB_SIM_DETECT
TP5016 1
68 40 OUT NC BB_RST_L
BB_UART_RTS_L 46 45
C TP5007
A 1 SPMI_DATA
TP-P5
37 39 A
TP-P5
RFFE1_CLK
35 40
BB_UART_CTS_L
NC
NC
48 47
NC
BB_SIM_RESET
OUT 37 68
C
50 49 BB_DEVICE_RDY 40 68
DEBUG_LED NC IN
TP5017 1 52 51 BOOT_HSIC
35 40 44 45 46 47 48 49
GPIO51/BOOT_CONFIG_3 NC GPIO54/BOOT_CONFIG_0 IN 35 40
TP5008 1 SPMI_CLK A TP-P5
54 53
TP-P5
37 39 RFFE1_DATA GPIO53/BOOT_CONFIG_1 NC NC GPIO48/BOOT_CONFIG_6
TP5018
A 1 35 40 44 45 46 47 48 49
58 57
TP5025 1 BOUNDARY_SCAN_EN TP-P5
RFFE2_CLK CONFIG _RF BOM OPTIONS
A TP-P5
39 69
TABLE_5_HEAD
TP5019 1 35 40 50 51 53
TP-P5 TABLE_5_ITEM
TP5021 1 PP_BATT_VCC 131S0273 1 0.8PF 0201 C6001 CRITICAL X137_RF

A TP-P5
35 44 53 68 73
TABLE_5_ITEM
TP5020 1 RFFE2_DATA 35 40 50 51 53
131S0273 1 0.8PF 0201 C6001 CRITICAL X202_RF
TP5028 1 TP-P5
131S0431 1 0.2PF 0201 C6013 CRITICAL X190_RF
TABLE_5_ITEM
A TP-P5
TABLE_5_ITEM
TP5031 1 90_BBUSB_N 131S0273 1 0.8PF 0201 C6013 CRITICAL X137_RF

TP5026 1 A TP-P5
35 39
TABLE_5_ITEM
A 131S0273 1 0.8PF 0201 C6013 CRITICAL X202_RF PP_LDO11

TP-P5 73 44 43 42 40 39 38 36 35
TP5030
A 1 90_BBUSB_P 35 39 152S2020 1 3.6NH +/-0.1NH 400MA 0201 L6001 CRITICAL X190_RF
TABLE_5_ITEM
TP5027
A 1
TP-P5
TABLE_5_ITEM
CELL
RADIO_BB
CELL
RADIO_BB
CELL
RADIO_BB
TP-P5 152S2022 1 4.3NH 3% 500MA 0201 L6001 CRITICAL X137_RF 1 1 1
R5001 R5002 R5003
TABLE_5_ITEM
152S2022 1 4.3NH 3% 500MA 0201 L6001 CRITICAL X202_RF 10K 10K 10K
1% 1% 1%
TABLE_5_ITEM
1/32W 1/32W 1/32W

131S0323 1 1.1PF 0201 C6421 CRITICAL X190_RF MF 2 MF 2 MF 2
TABLE_5_ITEM
01005 01005 01005
152S1217 1 1.0NH +/-0.1NH 750MA 0201 L6402 CRITICAL X190_RF
TABLE_5_ITEM
40 35 BOOT_HSIC
152S2042 1 1.8NH +/-0.1NH 800MA 0201 L6402 CRITICAL X137_RF 40 BOOT_HSIC_USB
TABLE_5_ITEM
40 WATCHDOG_DISABLE
B 152S2042 1 1.8NH +/-0.1NH 800MA 0201 L6402 CRITICAL X202_RF
TABLE_5_ITEM
B
152S1994 1 6.8NH 3% 210MA 01005 C6202 CRITICAL X190_RF
XW5001
TABLE_5_ITEM
152S1977 1 10.0NH 3% 170MA 01005 C6202 CRITICAL X137_RF

SM TABLE_5_ITEM
39 35 90_BBUSB_N 1 2 90_BB_USB_N BI 68 152S1994 1 6.8NH 3% 210MA 01005 C6202 CRITICAL X202_RF

TABLE_5_ITEM
RADIO <-- XW5002

SM
AP --> 152S00028 1 22NH 3% 120MA 01005 L6720 CRITICAL X190_RF
TABLE_5_ITEM
152S1979 1 18NH 1% 140MA 01005 L6720 CRITICAL X137_RF

39 35 90_BBUSB_P 1 2 90_BB_USB_P BI 68
TABLE_5_ITEM
152S1979 1 18NH 1% 140MA 01005 L6720 CRITICAL X202_RF

TABLE_5_ITEM
138S0831 5 MURATA 2.2UF CAPACITOR C5101,C5121,C5122,C6010,C6011 CRITICAL CELL REPLACES 138S0917. 138S0917 CAN ONLY
BE USED ON RAILS WITH 3V OR LESS
PP_VCC_MAIN CURRENT SENSE

REVISION DATE: 9/29/2014
A CELL
BOM ALTERNATES SYNC_MASTER=RADIO SYNC_DATE=09/29/2014 A
PAGE TITLE
U5000
TABLE_ALT_HEAD
CELL
INA216A2YFF
PART NUMBER ALTERNATE FOR
PART NUMBER
CELL: PROBE PTS & DEBUG CONN
BATT --> 68 53 44 35
73
PP_BATT_VCC
1
CELL
R5004
WCSP-4 R5005
0.00 2 152S1850 152S1721 MURATA IN, 2.2UH, 2016
TABLE_ALT_ITEM
DRAWING NUMBER SIZE
0.010
A1 IN+ OUT B2 ADC_IMEAS_RADIO 1 RADIO_TO_PMU_ADC_IMEAS_RADIO 68
L5101,L5103,L5104
TABLE_ALT_ITEM
Apple Inc. 051-0301

REVISION
D
1% 0% NOSTUFF 152S2050 152S1857 L5902 TAIYO IND, 2.2UH, 2012
1/6W A2 IN- 1/32W R
MF MF
01005
1 C5001
BRANCH B.0.0
2 0402 0.1UF
RADIO <-- 73 36 PP_BATT_VCC_RADIO
GND
B1
RADIO_ASM 20%
4V
2 X5R
50 OF 155
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 35 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C332
BASEBAND PMU (1 OF 2)
R302
L304
U301
SWITCHERS OUTPUT CAPS
VREG_SMPS1_0V90 36 38 69 VREG_SMPS2_1V25 36
CELL CELL CELL CELL CELL CELL
D RADIO_PMIC
C5127
RADIO_PMIC
C5129
RADIO_PMIC
1 C5137 PP5161 RADIO_PMIC
C5132
RADIO_PMIC
C5134
RADIO_PMIC
1 C5139 PP5163 D
P2MM-NSM P2MM-NSM
20UF 20UF 20UF SM
20UF 20UF 2.2UF SM
1 1
20% 6.3V
20% PP 20% 20% 20% PP
1 6.3V
CERM-X5R
6.3V
1 20%
CERM-X5R 2 CERM-X5R
0402 1 6.3V
0402 1 6.3V
CERM-X5R
6.3V
2 X5R
0402 0402 0201-1
0402 CERM-X5R
I783 I785
73 36 35 PP_BATT_VCC_RADIO
73 36 S1_GND 73 S2_GND
MAKE_BASE=TRUE
OMIT_TABLE OMIT_TABLE OMIT_TABLE CELL CELL MAKE_BASE=TRUE
2 2 2 2
RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC
1 C5121 1 C5122 1 C5101 1 C5123 1 C5124
2.2UF
20%
2.2UF
20% 20%
2.2UF 20UF
20%
20UF
20%
6.3V
2 X5R
6.3V
2 X5R
6.3V
2 X5R 2
6.3V
CERM-X5R 2
6.3V
0201-1 CERM-X5R
0201-1 0201-1 0402 0402 VREG_SMPS3_0V95 36 69 73 CELL VREG_SMPS4_2V075 36 73
CELL CELL CELL CELL CELL
RADIO_PMIC
RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC RADIO_PMIC
C5128 C5130 1 C5136 PP5159
P2MM-NSM
C5133
C5135 1 C5138
PP5162
P2MM-NSM
20UF 20UF 20UF 1
SM 20UF
20% 20UF 2.2UF
20% 1
SM
20%
20% 6.3V PP
1 6.3V PP
1 6.3V
CERM-X5R 1 CERM-X5R 2 6.3V
20%
CERM-X5R
CERM-X5R
0402
6.3V
1 20%
CERM-X5R 2 6.3V
X5R
0402 0402 I784 0201-1
0402 0402 I786
73 36 S3_GND S4_GND
MAKE_BASE=TRUE 73 36
MAKE_BASE=TRUE
2
2 2 2
C VREG_RF_CLK_BYP C
AVDD_BYP CELL
CELL RADIO_PMIC
C5131
SWITCHERS BULK CAPS REF_BYP
PP5157
RADIO_PMIC
PP5158
PP5160
1UF
P2MM-NSM
CELL U5201
P2MM-NSM
P2MM-NSM
CELL 20%
10V
RADIO_PMIC
C5126
PM8019 1 X5R
SM
PP
RADIO_PMIC BGA
SM
PP
SM
PP
C5125 0201
0.1UF SYM 5 OF 5
1
20%
1UF 20% 26 91
1
10V VDD_INT_BYP VREG_RFCLK
36 35 IN PP_BATT_VCC_RADIO VBATT_S1 36 X5R 1 4V
X5R 21 74 VREG_XO_PMIC
73 MAKE_BASE=TRUE 1 01005 REF_BYP REG VREG_XO
15 GND_REF CELL L5101 RADIO_PMIC
VBATT_S1
CELL 36
0201 27 2.2UH-20%-1.5A-0.16OHM
VREG_S1 2 VOLTAGE=0.9V
RADIO_PMIC 22 11 PP_VSW_S1 1235MA
1 C5117 36 VBATT_S1 VDD_S1 VSW_S1_1 16
73 1 2 CRITICAL VREG_SMPS1_0V90 OUT 36 38 69
MAKK2016-SM
20UF
20% 36 VBATT_S2 2 88 VDD_S2
VSW_S1_2
82 CELL L5103 RADIO_PMIC
6.3V 2 94 2.2UH-20%-1.5A-0.16OHM
2 CERM-X5R VDD_S2 VREG_S2 93
0402 73 PP_VSW_S2 1 2 CRITICAL 1100MA VREG_SMPS2_1V25
47 VSW_S2
S1_GND 36 73 36 VBATT_S3 VDD_S3 62 L5104 RADIO_PMIC
CELL MAKK2016-SM
36
VREG_S3
53 2.2UH-20%-1.5A-0.16OHM
VBATT_S4 1 1350MA
36 35 IN PP_BATT_VCC_RADIO VBATT_S2 36
36 VDD_S4
VSW_S3_1
58 73 PP_VSW_S3 1 2 CRITICAL VREG_SMPS3_0V95 36 69 73
73 MAKE_BASE=TRUE 92 VSW_S3_2
36 VREG_SMPS2_1V25 VDD_L1 23 MAKK2016-SM
VBATT_S2
CELL 36
6 CELL L5102 RADIO_PMIC
RADIO_PMIC VREG_SMPS4_2V075 2 VDD_L2_3
VREG_S4 2.2UH-20%-1.2A-0.15OHM
73 36
VSW_S4_1 12 PP_VSW_S4 550MA
1 C5118
4
73 1 2 0806 VREG_SMPS4_2V075 36 73
20UF
20%
VDD_L7_8_11 VSW_S4_2
6.3V 73 36 VREG_SMPS4_2V075 77
2 CERM-X5R VDD_L9 VREG_L1 86 VREG_RX 1.225V PP_LDO1
0402 OUT 38 42 43 73
72 VDD_L10 1.80V
VREG_L2 7 PP_LDO2 OUT
38 73
VREG_SMPS3_0V95 38 VDD_L12 VREG_L3 1.80V 37 38 55 73

73 69 36 8
B 36 35
73
IN PP_BATT_VCC_RADIO
MAKE_BASE=TRUE
VBATT_S3 36
73 36 VREG_SMPS4_2V075 85 VDD_XO_RFC 68 3.075V

PP_LDO3 OUT 38 73 B
VBATT_S3
CELL 36 VREG_L4 PP_LDO4 OUT 38 59 73
RADIO_PMIC 49 GND 1.8/2.85V PP_LDO5

VREG_L5 59 35 69 71 73
1 C5119 OUT
MDM_VREF_LPDDR2 52 VREG_SIM 1.8/2.85V PP_LDO6 38 40 73
20UF
20%
39 OUT VREF_DDR2
VREG_L6 48
OUT
6.3V PP_BATT_VCC_RADIO 43 PP_LDO7 42 43 73
2 CERM-X5R 36 35 IN VIN_VPH1 10 1.90V
0402 73 VREG_L7 VREG_TX OUT 38 73
S3_GND 54
36 73 VIN_VPH2 3 2.05V PP_LDO8 38 73
VREG_L8 OUT
PP_BATT_VCC_RADIO VBATT_S4 71 1.20V PP_LDO9

35 38 39 40 42 43 44 73
36 35 IN 36 VREG_L9 OUT
73 MAKE_BASE=TRUE 38 73
VBATT_S4 83 0.90V PP_LDO10

CELL 36 VREG_L10 OUT 38 55 69 73
RADIO_PMIC 9 VREG_IO 1.80V PP_LDO11 46 47 73

1 C5120 VREG_L11 OUT
20UF 33 0.95V PP_LDO12
20% VREG_L12 OUT
2 6.3V
CERM-X5R 34 2.95/1.8V PP_LDO13
0402 VREG_L13 OUT
S4_GND 36 73
28 2.7V PP_LDO14_RFSW
VREG_L14 OUT
CELL CELL CELL CELL CELL CELL CELL CELL CELL CELL CELL CELL CELL CELL CELL
RADIO_PMIC
C5102 1 RADIO_PMIC
RADIO_PMIC
RADIO_PMIC
RADIO_PMIC
RADIO_PMIC
RADIO_PMIC
RADIO_PMIC
1 RADIO_PMIC
RADIO_PMIC
RADIO_PMIC
RADIO_PMIC
1 RADIO_PMIC
RADIO_PMIC
RADIO_PMIC
C5103 C5104 C5105 C5106 C5107 C5108 C5109 C5110 1 C5111 1 C5112 C5113 C5114 C5115 C5116
1UF 10UF 1UF 1UF 1UF 1UF 1UF 1UF 10UF 10UF 10UF 1UF 10UF 1UF 1UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
10V
1 0201 6.3V 10V
2 CERM-X5R1 X5R
10V
1 X5R 10V
1 X5R 1 10V 10V
1 X5R 10V
1 X5R 6.3V 6.3V 6.3V
2 CERM-X5R2 CERM-X5R2 CERM-X5R
10V
1 X5R 6.3V
2 CERM-X5R
10V
1 X5R 1
X5R 0402-2 0201 0201 0201 0201 0201 0201 0402-2 0402-2 0402-2 0201 0402-2 0201 0201
X5R X5R
10V
A 2 2 2 2 2 2 2 2 2 2 A
PAGE TITLE
CELL: BB PMU (1/2)
DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
51 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C401
BASEBAND PMU (2 OF 2)
R411
L400
U404
D D
HW_REV_ID R5202 R5207 J82 REV J97 REV J99 REV
0.10V 887K 51.1K N/A PROTO0 N/A
0.20V 422K 51.1K PROTO0 PROTO0B PROTO0
0.30V 255K 51.1K PROTO1 PROTO1 PROTO1 1
XTAL19M_IN 37
0.40V 178K 51.1K PROTO2 RADIO_PMIC

R5204
100K
1%
0.50V 255K 100K EVT 1/32W
MF
201005
0.60V 102K 51.1K DVT NOSTUFF
0.70V 82.5K 51.1K PVT
Y5201
19.2MHZ-10PPM-7PF CELL
2.0X1.6-SM RADIO_PMIC
1 3 37 XTAL19M_IN U5201
PM8019 CELL
RADIO_PMIC
4 2 BGA
CELL R5208
RADIO_PMIC 90
SYM 2 OF 5
64 50_A0_PMCLK 1
100 2 50_RF_CLK
C U5201 XTAL19M_OUT 84
XTAL_19M_IN
XTAL_19M_OUT
CLOCK
XO_OUT_A0
67 1% MF RADIO_PMIC
OUT 41 43
C
PM8019 XO_OUT_A1 NC REF_CLK_FROM_BB 1/32W01005 C5202
BGA XO_OUT_D0_EN 73
SYM 4 OF 5
39 IN
CELL
GND_XO
SLEEP_CLK 80 SLEEP_CLK_32K OUT 35 39
18PF
5%
HW_REV_ID 39 13 RADIO_PMIC 79 78 1 16V
55 MPP_01 MPP_GPIO GPIO_01 NC R5206 XO_OUT_D0_EN CERM
XO_OUT_D0 MDM_CLK
CONFIG_SPARE NC 29 30
1100K2
01005
OUT 35 39
MPP_02 GPIO_02 BB_REQUEST_XO_CLK PP_LDO3 57
18 55 73 55 38 36 IN XO_THERM_Y1 46 XO_THERM 42 NOSTUFF
38 OUT VDDPX_BIAS MPP_03 GPIO_03 NC 1 PA_THERM1 NC
1% GND_XOADC
37 VPA_APT_SENSE44 MPP_04 GPIO_04 19
NC 1/32W CELL PA_THERM2 32
NC
MF I302
40
OUT VREF_DAC_BIAS35 MPP_05 GPIO_05 14 BB_BUA_SIM IN 40 01005 RADIO_PMIC
1 R5201 37
C5201 BATT_ID_THERM 2
37 VPA_ET_SENSE 24 MPP_06 GPIO_06 25
NC 1000PF 100KOHM-1%
10%
10V
2 X5R 01005
01005 2 NOSTUFF
CELL RADIO_PMIC
R5209
VPA_APT 1
0.00 2 VPA_APT_SENSE 37
49 45 44
0%
1/32W
MF
01005
CELL
R5210
0.00 2
49 48 47 46 44 VPA_ET 1 VPA_ET_SENSE 37
0%
1/32W
MF
01005
B CELL
RADIO_PMIC
CELL
RADIO_PMIC
B
CELL
RADIO_PMIC U5201 U5201
R5203 PM8019 PM8019
1.00K2 BGA BGA
68 35 IN BB_RST_L 1
SYM 1 OF 5 SYM 3 OF 5
5% RADIO_ON_L 70 CBL_PWR* OPT 66 5 GND_S1 GND 36
1/32W
68 35 IN
CONTROL NC INPUT_PWR
MF 31 PON_TRIG 87 GND_S2 GND 40
01005
CELL GND 89
63 GND_S3 GND 41
RADIO_PMIC
R5205 39 35 OUT PMIC_RESOUT_L 75 PON_RST* 56 17 50
GND GND_S4 GND
PS_HOLD 1
20.0K2 PS_HOLD_PMIC 65 45 51
39 IN 35 PS_HOLD GND GND
5% MF GND 60
1/32W0100568 20
RF_PMIC_RESET_L RESIN*
35 IN
GND 61
39 35 SPMI_CLK 81 SPMI_CLK GND 69
BI
39 35 SPMI_DATA 76 SPMI_DATA
BI
A A
PAGE TITLE
CELL: BB PMU (2/2) DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
52 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C538
BASEBAND (1 OF 3)
R500
L500
U502
CELL
RADIO_BB
U5401
ASIC-MDM9625M-333P
BGA (EBI1 PAD)
PP_LDO10 (MSM CORE)
J15 SYM 5 OF 6 F19 PP_LDO9
73 38 36 IN VDD_CORE VDD_P1 IN 36 38 73
K14 PWR L19 CELL
D K15
VDD_CORE
VDD_CORE
VDD_P1
VDD_P1 L20 U5401
RADIO_BB
D
L13 VDD_CORE VDD_P1 M1 ASIC-MDM9625M-333P
L14 VDD_CORE VDD_P1 T19 BGA
A2 GND GND M10
M8 SYM 6 OF 6
VDD_CORE
VDD_P2 B20(SDC1 PAD)
PP_LDO13 A20 GND GND M11
M9 VDD_CORE
IN 36 38 55 69 73
GND
C14 M14
M12 VDD_CORE VDD_P3 B2 (GENIO PP_LDO11
PAD) 35 36 38 39 40 42 43 44 73
GND GND
IN C20 GND GND M15
M13 VDD_CORE VDD_P3 J19
E14 GND GND M20
N7 VDD_CORE VDD_P3 K2
F12 GND GND N1
N8 VDD_CORE VDD_P3 V2
F13 GND GND N6
F14 GND GND N9
F20 GND GND N10
P7 VDD_CORE
VDD_P4 R19 (UIM1 PAD) G7 GND GND N13
P10 VDD_CORE
G11 GND GND N14
P11 VDD_CORE VDD_P5 U19 PP_LDO5 (UIM2 PAD)
IN 36 59 73
G12 GND GND P6
PP_LDO12 (MSM MEMORY)
E15 V9 (HSIC PAD)
PP_LDO9 36 38 73 H6 P8
73 38 36 IN VDD_MEM VDD_P6 IN GND GND
F8 VDD_MEM H7 GND GND P9
VREF_SDC A19 VDDPX_BIAS 37 38
F9 VDD_MEM IN H10 GND GND P12
VREF_UIM U20
F15 VDD_MEM H11 GND GND R20
G8 VDD_MEM VDD_USB_CORE V13 PP_LDO12 36 38 73
H14 GND GND T20
IN
K10 VDD_MEM H15 GND GND V20
VDD_USB_1P8 U11 PP_LDO2 36 38 73
L9 VDD_MEM IN J1 GND GND W1
L10 VDD_MEM VDD_USB_3P3 V10 PP_LDO4 36 73 J6 GND GND W5
IN
N15 VDD_MEM 36 38 40 73 J9 GND GND W9
VDD_A2 C12 PP_LDO7
P14 VDD_MEM
IN J10 GND GND W20
VDD_A2 C9
P15 VDD_MEM J13 GND GND W12
R7 VDD_A2 B12 J14 A12
C R8
VDD_MEM
VDD_MEM VDD_A1 B9 PP_LDO1 IN 36 38 42 43 73
K8
GND
GND
GND
GND A6 C
VDD_A2
C6 K9 GND GND E12
E5 VDD_MEM
VDD_A1 B6 K12 GND GND E9
(MODEM SUB SYSTEM)
VREG_SMPS1_0V90 F6 VDD_MODEM K13 A9
69 38 36 GND GND
IN
F7 VDD_MODEM VDD_A1 B15 PP_LDO1 IN 36 38 42 43 73 K19 E6
GND GND
F10 VDD_MODEM VDD_PLL U13 PP_LDO10 36 38 73 K20 GND GND A17
IN
F11 VDD_MODEM VDD_PLL R12 L1 GND GND C17
G6 VDD_MODEM VDD_PLL D17 L7 GND GND B17
G9 VDD_MODEM VDD_PLL2 E16 PP_LDO3 36 37 38 55 73
L8 GND GND P13
IN
G10 VDD_MODEM L11 GND GND R13
T17
G13 VDD_MODEM VDD_ALWAYS_ON NC L12 GND GND R14
G14 VDD_MODEM J20(LPDDR2)
PP_LDO11 L15 GND
VDD_DDR_CORE_1P8 IN 35 36 38 39 40 42 43 44 73
GND A15
G15 VDD_MODEM K1 M6 GND
VDD_DDR_CORE_1P8
H8 VDD_MODEM M7
VDD_DDR_CORE_1P2 E20(LPDDR2_CORE)
PP_LDO9 GND
H9 VDD_MODEM IN 36 38 73
VDD_DDR_CORE_1P2 H1
H12 VDD_MODEM
VDD_DDR_CORE_1P2 P1
H13 VDD_MODEM
VDD_DDR_CORE_1P2 P20
J7 VDD_MODEM
J8 VDD_MODEM VDD_QFPROM_PRG W8 (QFUSE PP_LDO3
PROGRAMMING)
36 37 38 55 73
IN
J11 VDD_MODEM
J12 VDD_MODEM
K6 VDD_MODEM
K7 VDD_MODEM
K11 VDD_MODEM
L6 VDD_MODEM
B B
(MSM CORE) (EBI1 PAD) (HSIC PAD) (USB 1.8V) (GPS ADC) (LPDDR2)
RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB
73 38 36 IN PP_LDO10 CELL CELL CELL CELL CELL CELL 73 38 36 IN PP_LDO9 CELL CELL 73 38 36 IN PP_LDO9 CELL 73 38 36 IN PP_LDO2 CELL 73 43 42 38 36 IN PP_LDO1 CELL 43 42
38 36 35 IN PP_LDO11 CELL
RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB 40 39 RADIO_BB
73 44
C5301 C5304 C5307 C5310 C5313 C5316 C5319 C5322 C5324 C5327 C5330 C5332 C5335
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 0.1UF 2.2UF
20% 2.2UF
20% 20% 20% 4V 20% 20% 20% 20% 20% 20% 20% 4V X5R-
1 4V
X5R-CERM 1 4V
X5R-CERM 1 4V
X5R-CERM 1 20%
X5R-CERM 1 4V
X5R-CERM 1 4V
X5R-CERM 1 4V
X5R-CERM 1 4V
X5R-CERM 1 4V
X5R-CERM 1 4V
X5R-CERM 1 4V
X5R 1 CERM 1
0201 0201 0201 0201 0201 0201 0201 0201 0201 0201 01005 0201 0201
NOSTUFF X5R-CERM
4V
(MSM MEMORY) (SDC1 PAD) (SDC/UIM) (COMBO DAC/BBRX) (PLL) (LPDDR2 20%
CORE)
RADIO_BB
PP_LDO12 RADIO_BB
PP_LDO13 NOSTUFF RADIO_BB
VDDPX_BIAS RADIO_BB
PP_LDO7 RADIO_BB
PP_LDO10 RADIO_BB
PP_LDO9
73 38 36 IN CELL CELL CELL CELL CELL CELL 69 55 38 36 IN 38 37 IN 73 40 38 36 IN CELL 73 38 36 IN 73 38 36 IN CELL CELL
2 RADIO_BB 2 RADIO_BB 2 RADIO_BB 2 RADIO_BB 2 RADIO_BB 2 RADIO_BB 73 2 RADIO_BB 2 2 RADIO_BB 2 RADIO_BB 2 RADIO_BB 2 RADIO_BB 2 RADIO_BB RADIO_BB
C5302 C5305 C5308 C5311 C5314 C5317 C5320 C5325 C5328 C5331 C5333 C5336 C5338
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 0.1UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
20% 20% 20% 20% 20% 20% 20% 20% 20% 20%
4V
1 20% 1 4V 1 4V 4V
1 X5R-CERM 4V
1 X5R-CERM 4V
1 X5R-CERM 4V
1 X5R-CERM 4V
1 X5R 1 4V
20% 1 4V 1 4V 1 4V
20% 1 4V
X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM
X5R-CERM 0201 0201 0201 0201 0201 0201 01005 0201 0201 0201
0201 NOSTUFF 0201 NOSTUFF NOSTUFF 0201
(PLL) (QFUSE)
(MODEM SUB SYSTEM) (GENIO PAD) (USB CORE) (BBRX) RADIO_BB
PP_LDO3 RADIO_BB
PP_LDO3
RADIO_BB RADIO_BB RADIO_BB RADIO_BB 73 55 38 37 36 IN 73 55 38 37 36 IN CELL
69 38 36 IN VREG_SMPS1_0V90
2 CELL 2 CELL 2 CELL 2 CELL 2 CELL 2 CELL 73 44
39 38 36 35 IN PP_LDO11 2 CELL CELL 73 38 36 IN PP_LDO12 2 CELL 42 38 36 IN PP_LDO1 2 CELL 2 2 RADIO_BB 2 RADIO_BB 2
RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB RADIO_BB 43 42 40 RADIO_BB RADIO_BB RADIO_BB 73 43 RADIO_BB C5334 C5337
20%
C5303 C5306 C5309 C5312 C5315 C5318 C5321 C5323 C5326 C5329
2.2UF 2.2UF
2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF
4V 2.2UF 2.2UF 20% 20%
20% 20% 20% 20% 20% 20% 20% 20% 1 4V 1 4V
1 4V
X5R-CERM 1 4V
X5R-CERM 1 4V
X5R-CERM 1 4V
X5R-CERM 1 4V
X5R-CERM 1 4V
X5R-CERM 1 4V
X5R-CERM 1 1 4V
X5R-CERM 1 4V
X5R-CERM
X5R-CERM
0201
X5R-CERM
0201
0201 20%
0201 0201 0201 0201 0201 0201 0201 0201 0201 NOSTUFF
X5R-CERM
A 2 2 2 2 2 2 2 2 2 2
2 2 A
PAGE TITLE
CELL: BASEBAND (1/2) DRAWING NUMBER SIZE

REVISION
R
BRANCH
B.0.0
53 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C600
BASEBAND (2 OF 3)
R606
L600
U602
D D
73 44 43 42 40 39 38 36 35
PP_LDO11
A2
VP
CELL
40 39 BB_SWD_ENABLE B2 IN1 IN2 C1 BB_SWD_ENABLE 39 40
U5402
TS5A2066
39 35 90_BBUSB_P B1 COM1 BGA COM2 C2 90_BBUSB_N 35 39
39 35 BB_JTAG_TCK A1 NO1 NO2 D2 BB_JTAG_TMS 35 39
GND
D1
RADIO_SIMCARD
CELL
PP_LDO11 35 36 38 39 40 42 43 44 73
RADIO_BB 1
R5401
10K
C 1%
1/32W
MF
010052
C
BB_SIM_DETECT 40 68 CELL
RADIO_BB
U5401
ASIC-MDM9625M-333P
PMIC_RESOUT_L W14 BGA V17 CELL
37 35 IN RESIN* RESOUT* NC
N2 SYM 1 OF 6 W18 RADIO_BB
35 IN BB_JTAG_RST_L SRST* DIGITAL PS_HOLD PS_HOLD OUT 37 CELL
W17 U5401
37 35 IN SLEEP_CLK_32K SLEEP_CLK
P5 RADIO_BB
TDO BB_JTAG_TDO OUT 35
R5404
BB_JTAG_TCK R2 BGA ASIC-
1 240 2
TCK
39 35 IN P3 PMIC_SPMI_DATA W15 SPMI_DATA EBI1_CAL R1 EBI1_CAL SYM 2 OF 6 EBI1_VREF N20 MDM_VREF_LPDDR2
35 IN BB_JTAG_TDI TDI V15 SPMI_CLK
BI 35 37
1% MF
MDM9625M-333P
EBI1_EBI2 M5
IN 36 39
P2 PMIC_SPMI_CLK EBI1_VREF
39 35 IN BB_JTAG_TMS TMS BI 35 37 1/32W01005 BDM_ZQG1 EBI1_ZQ R16
T4 U9 CELL CELL EBI1_VREF
35 IN BB_JTAG_TRST_L TRST* HSIC_CAL BB_HSIC_CAL
U10 RADIO_2G RADIO_2G 1 RADIO_BB RADIO_BB F18 H20
HSIC_DATA 50_BB_HSIC_DATA R5403 EBI2_CS* EBI2_AD_7
BOUNDARY_SCAN_EN R11 MODE_0 R10
BI 35 68
1 C5402 1 C5403 R5405 NC
F16 H19
NC
69 35 IN
R9 HSIC_STROBE 50_BB_HSIC_STROBE 35 68 240 240 2 NCG20 EBI2_CLE* EBI2_AD_6
H18NC
BI
MODE_1 33PF
2%
33PF
2%
1%
1/32W
1
EBI2_ALE* EBI2_AD_5
UIM1_RESET M19 16V 16V MF 1% MF NC NC
W19 G19 H16
37 35 IN MDM_CLK CXO
UIM1_CLK N18NC 2 NP0-C0G
01005
2 NP0-C0G
01005
201005 1/32W01005
NCG18
EBI2_WE* EBI2_AD_4 NC
XO_OUT_D0_EN V18 CXO_EN NC NOSTUFF NOSTUFF EBI2_OE* EBI2_AD_3 J18
37 OUT
UIM1_DATA P19 NCG16 NC
NC EBI2_BUSY* EBI2_AD_2 K18
N19 UIM1_DETECT NC NC
NC SDC1_DATA_3 B18 EBI2_AD_1 J16
NC NC
B19 SDC1_CMD SDC1_DATA_2 A18 EBI2_AD_0 K16
NC NC NC
C19 SDC1_CLK SDC1_DATA_1 D20
NC NC
SDC1_DATA_0 D19
68 35 BB_USB_VBUS U12 USB_HS_VBUS NC
IN
NCV12 USB_HS_ID USB_HS_DP V11 90_BBUSB_P BI 35 39
W13 W11
B USB_HS_SYSCLK USB_HS_DM
USB_HS_REXT W10
90_BBUSB_N
BB_USB_TRXTUNE
BI 35 39
B
CELL
1 RADIO_BB
R5402
200 CELL MDM_VREF_LPDDR2 36 39
PP_LDO11 1/32W
1%
35 36 38 39 40 42 43 44 73 RADIO_BB
2MF
CELL 01005 1 C5401
RADIO_2G 1.0UF
20%
1 C5404 2 6.3V
X5R
33PF 0201-1
5%
2 16V
PP_LDO11 35 36 38 39 40 42 43 44 73
NP0-C0G-CERM
01005
A1
VCC 1 CELL 1 CELL

CELL R5406 R5407
U5403
CAT24C08C4A 10K
1%
10K
1%
WLCSP 1/32W 1/32W
40 39 35
B1
BB_EEPROM_SCL SCL SDA B2 BB_EEPROM_SDA 35 39 40 MF
2 01005 201005
MF
VSS
40 39 35 BB_EEPROM_SCL
A2
BB_EEPROM_SDA
A 40 39 35
A
PAGE TITLE

REVISION
R
BRANCH
B.0.0
54 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C704
BASEBAND (3 OF 3)
U702
L700
R700
D D
CELL
RADIO_BB
U5401
ASIC-MDM9625M-333P
BGA
BB_SIM_DATA R18 GPIO_0 SYM 3 OF 6 GPIO_38 H5 GSM_TXBURST_IND
68 BI NC
CELL BB_SIM_DETECT U18 GPIO_1 GPIO GPIO_39 H2 CTRL_FWD_REV
68 39 IN
BLSP1 NC
RADIO_BB BB_SIM_RESET T18 GPIO_2 GPIO_40 H3 BB_GPS_SYNC (OLD)
68 OUT NC
U5401 BB_SIM_CLK P18 GPIO_3 GPIO_41 G3 UAT_SELECT
68 OUT NC
ASIC-MDM9625M-333P BB_UART_TXD U15 GPIO_4 GPIO_42 G2 LAT_SELECT
68 35 OUT NC
BGA BB_UART_RXD U14 GPIO_5 GPIO_43 F1
68 35 IN BB_UART_CTS_L GPIO_6 BLSP2 GRFC NC
SYM 4 OF 6 TX_DAC0_IREF C13 WTR_TX_IDAC V14 GPIO_44 F2
WTR_BB_PRX_I_P E11 BBRX_IP_CH0
OUT 40 41 68 IN BB_UART_RTS_L NC
41 IN ANALOG TX_DAC0_VREF E13 VREF_DAC_BIAS U16 GPIO_7 GPIO_45 D3
WTR_BB_PRX_I_N C11 BBRX_IM_CH0
37 40 68 OUT NC
41 IN U3 GPIO_8 GPIO_46 C1 NC
WTR_BB_PRX_Q_P E10 BBRX_QP_CH0
TX_DAC0_IP A14 WTR_BB_TX_I_P NC U4
41 IN
TX_DAC0_IM
OUT 41
GPIO_9 GPIO_47 G5 NC
WTR_BB_PRX_Q_N C10 BBRX_QM_CH0 B14 WTR_BB_TX_I_N NC BLSP3
41 IN OUT 41
W2 GPIO_10 GPIO_48 F3 NC
B11 TX_DAC0_QP B13 WTR_BB_TX_Q_P NC
41
WTR_BB_DRX_I_P BBRX_IP_CH1
OUT 41 V3 GPIO_11 GPIO_49 E3 WLAN_TX_BLANK
IN
A11 TX_DAC0_QM A13 WTR_BB_TX_Q_N NC NC
41
WTR_BB_DRX_I_N BBRX_IM_CH1
OUT 41 V7 GPIO_12 GPIO_50 F5 NC
IN
B10 NC
41
WTR_BB_DRX_Q_P BBRX_QP_CH1 TX_DAC1_IREF C8 PP_LDO7 V6 GPIO_13 GPIO_51 N5 NC
IN
A10
36 38 40 73
NC BLSP4
41
WTR_BB_DRX_Q_N E8 W7 N3 UART_BB2WLAN_COEX_RX
C 43
IN
WFR_BB_PRX_I_P
B5
BBRX_QM_CH1
BBRX_IP_CH2
TX_DAC1_VREF
TX_DAC1_IP A8
NC
NC
U8
GPIO_14
GPIO_15
GPIO_52
GPIO_53 T3 UART_WLAN2BB_COEX_TX
OUT
IN
57 70 71
57 70 71
C
43 IN A5 M18 GPIO_16 GPIO_54 E2 WTR_SSBI_TX_GPS OUT 41
WFR_BB_PRX_I_N BBRX_IM_CH2 TX_DAC1_IM B8 NC
43 IN B4 M16 GPIO_17 GPIO_55 D1 WTR_SSBI_PRX_DRX IN 41
WFR_BB_PRX_Q_P BBRX_QP_CH2 TX_DAC1_QP A7 NC BLSP5 SSBI
43 IN A4 N16 GPIO_18 GPIO_56 D2
WFR_BB_PRX_Q_N BBRX_QM_CH2 TX_DAC1_QM B7 NC NC
43
IN L16 GPIO_19 GPIO_57 E1 WFR_SSBI 43
C4 C7 NCD18 T1
OUT
43
IN WFR_BB_DRX_I_P C5 BBRX_IP_CH3 ET_DAC_M ET_DAC_N OUT 35 44 68 OUT BB_OTHER_TXD GPIO_20 GPIO_58 NC
E7 C18 R6 GSM_TX_PHASE_D1
43
IN WFR_BB_DRX_I_N B3 BBRX_IM_CH3 ET_DAC_P ET_DAC_P OUT 35 44 68 IN BB_OTHER_RXD GPIO_21 GPIO_59 OUT 41
WFR_BB_DRX_Q_P BB_EEPROM_SDA E19 BLSP6 R3 GSM_TX_PHASE_D0

43
IN A3 BBRX_QP_CH3 V16 39 35 BI GPIO_22 GPIO_60 OUT 41
DNC NC E18 U7
41 IN WFR_BB_DRX_Q_N BBRX_QM_CH3 W16 39 35 BI BB_EEPROM_SCL GPIO_23 GPIO_61 BB_CORE_DUMP IN 68
DNC
41 C15 D4
NC 68 35 OUT BB_RESET_DET_L P16 GPIO_24 GPIO_62 V8 BB_DEBUG_STATUS OUT 35
IN WTR_BB_GPS_I_P GNSS_BB_IP DNC NC L18 W4
41 C16 DNC C3 68 IN AP_WAKE_MODEM GPIO_25 GPIO_63 BB_DEBUG_ERROR OUT 35
IN WTR_BB_GPS_I_N GNSS_BB_IM NC L5 W3
41
WTR_BB_GPS_Q_P B16 68 OUT BB_ANTSW_GPIO0 GPIO_26 GPIO_64 BB_SWD_ENABLE OUT 39
IN A16 GNSS_BB_QP M3 U6 BB_IPC_GPIO
68 OUT BB_ANTSW_GPIO1 GPIO_27 GPIO_65 BI 68
IN WTR_BB_GPS_Q_N GNSS_BB_QM K3 T2
BB_LAT_GPIO2 NC GPIO_28 GPIO_66 BB_HOST_RDY IN 35 68
BB_LAT_GPIO3 L3 GPIO_29 GPIO_67 R15 BB_WAKE_HOST

NC OUT 35 68
BB_LAT_GPIO4 M2 GPIO_30 GPIO_68 V4 BB_DEVICE_RDY 35 68

NC K5 U17
OUT
BB_LAT_GPIO5 NC GPIO_31 GPIO_69 BB_BUA_SIM IN 37
B1 GRFC V1 BB_GPS_SYNC
BB_LAT_GPIO6 NC GPIO_32 GPIO_70 OUT 68
BB_HSIC_WAKE_PHY
FORCE_USB_BOOT C2 GPIO_33 GPIO_71 W6
NC NC RFFE2_DATA
35 IN WATCHDOG_DISABLE J5 GPIO_34 GPIO_72 U2
BI 35 50 51 53
35 BOOT_HSIC L2 GPIO_35 GPIO_73 U5 RFFE2_CLK 35 50 51 53

IN BI
BOOT_HSIC_USB J3 RFFE U1 RFFE1_DATA
35 IN GPIO_36 GPIO_74 BI 35 44 45 46 47 48 49
J2 GPIO_37 GPIO_75 R5 RFFE1_CLK
NC BI 35 44 45 46 47 48 49
41 40 WTR_TX_IDAC 40 37 VREF_DAC_BIAS
CELL CELL
RADIO_BB RADIO_BB RADIO_BB
B 1 C5501
0.1UF
10%
1 C5502
2200PF
1 C5503
2200PF
B
6.3V 10% 10%
2 X7R 2 6.3V 2 6.3V
0201 X5R-CERM X5R-CERM
01005 01005
73 40 38 36 PP_LDO7 NOSTUFF
I447
73 44 43 42 39 38 36 35
PP_LDO11 RFFE_VIO 45 46 47 48 49 50 51 53
MAKE_BASE=TRUE
A A
PAGE TITLE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
55 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C802
WTR TRANSCEIVER (1 OF 2)
R802
L800
U803
D D
CELL CELL
RADIO_WTR RADIO_WTR
U5601 U5601
WTR1625 WTR1625
BGA BGA
50_B8_PRX_WTR_IN 102 P R X _ L B 1 _ I N SYM 1 OF 5 PRX_BB_IP 99 WTR_BB_PRX_I_P SYM 2 OF 5
47 OUT 40
50_B8_B28B_DRX_WTR_IN 5 DRX_LB1_IN DRX_BB_IP 76 WTR_BB_DRX_I_P
LB1 DC PRX_BB_IM 108 WTR_BB_PRX_I_N LB1 DC
52 OUT 40
47
50_B20_PRX_WTR_IN 92 P R X _ L B 2 _ I N OUT 40
DRX_BB_IM 86 WTR_BB_DRX_I_N
PRX_BB_QP 107
97 WTR_BB_PRX_Q_P 52
50_B13_B17_DRX_WTR_IN 15 DRX_LB2_IN OUT 40
LB2 DC 47 WTR_BB_PRX_Q_N OUT 40

LB2 DC DRX_BB_QP 61
68 WTR_BB_DRX_Q_P
50_B26_PRX_WTR_IN 73 PRX_LB3_IN PRX_BB_QM 52 WTR_BB_DRX_Q_N OUT 40
46
OUT 40
50_B26_B28A_DRX_WTR_IN 16 DRX_LB3_IN DRX_BB_QM 40
OUT
LB3 DC 65 P R X _ L B 4 _ I N LB3 DC 52
50_B13_B17_B28_B29_PRX_WTR_IN 7 60
50_B20_B29_DRX_WTR_IN DRX_LB4_IN GNSS_BB_IP WTR_BB_GPS_I_P OUT 40
LB4 DC 91 LB4 DC 53
NO DC 43 OUT 50_WFR_PRX_LB_CA_IN PRX_LB_CA_OUT 32 GNSS_BB_IM WTR_BB_GPS_I_N OUT 40
43 OUT 50_WFR_DRX_LB_CA_IN DRX_LB_CA_OUT 67
MB1 50 MB1 NO DC GNSS_BB_QP 85 WTR_BB_GPS_Q_P
WTR_BB_GPS_Q_N OUT 40
43 IN 50_WFR_PRX_MB_CA_OUT PRX_MB_CA_IN 29 GNSS_BB_QM
43 IN 50_WFR_DRX_MB_CA_OUT DRX_MB_CA_IN OUT 40
MB2 DC MB2 DC
50 50_B34_B39_PRX_WTR_IN 51 PRX_MB1_IN 52 50_B34_DRX_WTR_IN 28
37
DRX_MB1_IN
MB3 DC MB3 DC NC
52
50_DCS_WTR_IN 43 PRX_MB2_IN
52
50_B39_DRX_WTR_IN 20 DNC
DRX_MB2_IN
52
HB1 NO DC 27 HB1 NO DC 1
50_PCS_WTR_IN PRX_MB3_IN NC DRX_MB3_IN
HB2 DC 19 HB2 DC 2
51 50_B40A_PRX_WTR_IN PRX_HMB4_IN 52 50_B40_DRX_WTR_IN DRX_HMB4_IN
HB3 DC HB3 DC 50_B38X_DRX_WTR_IN 4 DRX_HB1_IN
51 50_B40B_B38X_PRX_WTR_IN9 PRX_HB1_IN
52
HBMB4 NO DC HBMB4 NO DC
52
50_B41A_DRX_WTR_IN 12 DRX_HB2_IN
51
50_B41A_PRX_WTR_IN 17 PRX_HB2_IN 52
49 50_B7_DRX_WTR_IN 13 DRX_HB3_IN
50_B7_PRX_WTR_IN 18 PRX_HB3_IN
30 DRX_HB_CA_OUT
33 NC
C NC PRX_HB_CA_OUT
54 100_GPS_WTR_IN_P 36 GNSS_RF_INP
C
54 100_GPS_WTR_IN_N 44 GNSS_RF_INM
CELL
RADIO_WTR
U5601
WTR1625
BGA
WTR_BB_TX_I_P 151 TX_BB_IP SYM 3 OF 5 TX_LB1_OUT 162
40
NC
40 WTR_BB_TX_I_N 160 TX_BB_IM TX_LB2_OUT 153 50_LB_2G_WTR_TX_OUT 45
WTR_BB_TX_Q_P 152
161 TX_BB_QP TX_LB3_OUT 163 50_B8_B26_B20_WTR_TX_OUT 47
40 WTR_BB_TX_Q_N
40
TX_BB_QM TX_LB4_OUT 154 50_B13_B17_B28_WTR_TX_OUT 46
WTR_TX_IDAC 127 DAC_REF
40
TX_MB1_OUT 146 50_B3_B4_WTR_TX_OUT 48
40 GSM_TX_PHASE_D0123 GP_DATA0 TX_MB2_OUT 138 50_HB_2G_WTR_TX_OUT 45
40 GSM_TX_PHASE_D1104 GP_DATA1 TX_MB3_OUT 139 50_B1_B25_B34_B39_WTR_TX_OUT 48

CELL 141 155
B RADIO_WTR
94
GND TX_MB4_OUT NC B
R5601 GND TX_HB1_OUT 130 50_B7_WTR_TX_OUT 49
4.75K 71
1 2 WTR_RTUNE 140 RTUNE TX_HB2_OUT 121 50_B40_B38_B41_WTR_TX_OUT 49
1%
1/32W 109
MF
01005 55 GND ADC_IN
118 GND PDET_RFFB 117 50_FWD_OR_REV_RF 50
GND 122
105 SSBI_TX_GNSS GND
40 WTR_SSBI_TX_GPS
40 WTR_SSBI_PRX_DRX 95 SSBI_PRX_DRX
156
GND
131 XO_IN
CELL
RADIO_WTR
C5601
1000PF
43 37 50_RF_CLK 1 2 XO_WTR_IN
10% RADIO_WTR
10V
X5R C5602
01005 1
5%
100PF
10V
A 2 NP0-C0G
01005
NOSTUFF A
PAGE TITLE
CELL: RF TXCVR (1/3) DRAWING NUMBER SIZE

RF_CLK IS SHARED BETWEEN WTR AND WFR. LENGTH DIFFERENCE BETWEEN THE TWO SHOULD BE < 5MM.
Apple Inc. 051-0301
REVISION
D
R
BRANCH B.0.0
56 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C934
WTR TRANSCEIVER (2 OF 2)
TRUE
R926
L3802_RF
U902
PP_LDO8 VREG_2V
43 36
73
38 36
73 43
TRUE
PP_LDO1 VREG_1P3V
CELL
42 43
42 43
RADIO_WTR
WTR DECOUPLING L5701
CAPS CELL
CELL
R5705 MAKE_BASE=TRUE R5707 MAKE_BASE=TRUE 22NH-3%-0.25A MAKE_BASE=TRUE

0 0
43 42 VREG_2V 1 2 VREG_2V_FILT1 VDD_DRX_BB_2V 42 43 42 VREG_1P3V1 2 42 VREG_1P3V_FILT2 1 2VDD_PRX_PLL_1P3V 42 42 VREG_1P3V_FILT2 VDD_PRX_LO_HB_1P3V 42
D 5%
1/20W CELL
RADIO_WTR
C5710
5%
1/20W CELL
0201
RADIO_WTR
RADIO_WTR
C5718 CELL
RADIO_WTR
C5727
D
MF MF CELL
201
1 RADIO_WTR 1 100PF 201
1 RADIO_WTR 1 0.1UF 1 RADIO_WTR 1 0.1UF
C5701 5% C5704 20% C5707 20% RADIO_WTR
10UF
20% 10V 10UF
20% 4V 10UF
20% 4V U5601
NP0-C0G
2 01005 X5R
2 01005 X5R
2 01005
2 6.3V
CERM-X5R
NOSTUFF
2 6.3V
CERM-X5R
NOSTUFF
2 6.3V
CERM-X5R
CELL VDD_PRX_VCO_1P3V 90 VDD_RF1_P_VCO
WTR1625
0402-2 0402-2 0402-2 42
BGA
42
VDD_PRX_VCO_2V 80 VDD_RF2_P_VCO SYM 4 OF 5 VDD_RF2_T_DA 129 VDD_TX_DA_2V 42
VDD_TX_DA_2V 42 VDD_SHDR_PLL_1P3V 42 VDD_DRX_LB_1P3V 42 42 VDD_PRX_LO_HB_1P3V25 VDD_RF1_P_HB_LO VDD_RF1_T_DA 137 VDD_TX_DA_1P3V 42
RADIO_WTR RADIO_WTR VDD_PRX_LB_1P3V 72 136 VDD_TX_UPC_1P3V

C5711 C5719 42 VDD_RF1_P_LB VDD_RF1_T_UPC 42
135
1 100PF
5%
1 0.1UF
20% 42 VDD_PRX_HBMB_1P3V 34 VDD_RF1_P_HMB VDD_RF1_T_LO VDD_TX_LO_1P3V 42
10V 4V
2 NP0-C0G 2 X5R 42
57 VDD_RF1_P_HMB_LO VDD_RF2_T_BB 126 VDD_TX_BBF_2V 42
01005 01005 VDD_PRX_LO_HBMB_1P3V
CELL CELL 42 79 116 VDD_FBRX_2V
VDD_RF1_P_PLL VDD_RF2_FBRX 42
VDD_PRX_PLL_1P3V
VDD_TX_BBF_2V 42 42 VDD_PRX_BB_2V 98 VDD_RF2_P_BB VDD_RF2_T_VCO 157 VDD_TX_VCO_2V 42
RADIO_WTR RADIO_WTR
C5712 VDD_PRX_HBMB_1P3V 42 VDD_PRX_LB_1P3V 42 100 149 VDD_TX_VCO_1P3V
42 VDD_PRX_2V VDD_RF2_P_RX VDD_RF1_T_VCO 42
1 100PF
5% 14 115 VDD_TX_SYNTH_1P3V
10V 42 VDD_DRX_LO1_1P3V VDD_RF1_D_LB_LO VDD_RF1_T_SYN 42
2 NP0-C0G
01005 42 38 114 VDD_TX_PLL_2V
VDD_DRX_LO2_1P3V VDD_RF1_D_LOM VDD_RF2_T_PLL 42
NOSTUFF
42 VDD_DRX_LB_1P3V 31 VDD_RF1_D_LB VDD_RF1_G_LNA 52 VDD_GPS_LNA_1P3V 42
VDD_PRX_BB_2V 42
RADIO_WTR 42 VDD_DRX_HB_1P3V 22 VDD_RF1_D_HB VDD_RF1_G_VCO 74 VDD_GPS_VCO_1P3V 42

CELL VDD_DRX_MB_1P3V 11 93 VDD_GPS_PLL__1P3V
VDD_RF1_G_PLL
R5703 VDD_SHDR_VCO_1P3V 42 VDD_DRX_LO2_1P3V 42
42 VDD_RF1_D_MB 42
1
0.00 2 VDD_PRX_VCO_2V VDD_DRX_BB_2V 54 59 VDD_GPS_BB_1P3V
42 RADIO_WTR RADIO_WTR 42 VDD_RF2_D_BB VDD_RF1_G_BB 42
C 1%
1/20W
MF
RADIO_WTR
C5713 1
C5720
0.1UF
C5728
0.1UF
1 20% 42 VDD_SHDR_VCO_1P3V 48 VDD_RF1_S_VCO GND 113 PWRTERM2GND C
0201 1 0.1UF 20%
20% 4V X5R 42
VDD_SHDR_VCO_2V 62 VDD_RF2_S_VCO VDD_RF2_XO 147 VDD_XO_2V
4V 01005
2 X5R 2 4V 103
42
X5R 01005
2 01005 CELL CELL 42 VDD_SHDR_PLL_1P3V 78 VDD_RF1_S_PLL VDD_DIO VDD_MSM_1P8V 42
CELL
CELL
R5704 VDD_PRX_VCO_1P3V 42
VDD_DRX_LO1_1P3V 42
1
0.00 2 VDD_SHDR_VCO_2V
42 RADIO_WTR
1% RADIO_WTR C5708
1/20W
MF C5714 DELETED C3805 PR REVIEW FEEDBACK 1 0.1UF
20%
0201 1 0.1UF
20% 4V
4V
X5R 2 X5R
01005
2 01005 CELL
CELL
CELL
CELL RADIO_WTR
89
R5702 VDD_PRX_LO_HBMB_1P3V 42 VDD_DRX_MB_1P3V 42 56
GND U5601
WTR1625
0.00 2 GND BGA 111
1 VDD_TX_VCO_2V 42 RADIO_WTR 83 GND
C5705 CELL GND
1%
1/20W
RADIO_WTR 82 SYM 5 OF 5 101
MF C5715 1 0.1UF
20% 58
GND GND
0201 1 0.1UF 4V GND
GND 110
2 X5R
01005 35 GND
2 20% 8 GND 145
GND 144
01005 26 GND
GND 143
64 GND
4V GND 128
X5R VDD_TX_SYNTH_1P3V 42 VDD_DRX_HB_1P3V 42 42 GND
GND 120
VDD_TX_PLL_2VCELL 42 RADIO_WTR CELL 41 GND
RADIO_WTR
CELL C5721 CELL RADIO_WTR
GND
GND 119
81
B 1
C5702
0.1UF
1
4V
0.1UF
20%
1
R5701
21
GND
GND 106
150
B
20% 2 X5R
0.00
1%
GND GND
4V 01005 1/20W 6 GND GND 134
2 X5R
01005 MF 24
20201 GND 159
39 GND
CELL GND 142
GND
R5706 VDD_TX_LO_1P3V 42 VREG_1P3V_FILT2_GPS VDD_GPS_LNA_1P3V
CELL 42
10 GND GND 125
0.00 2 MAKE_BASE=TRUE 3 124
1 VDD_XO_2V 42 RADIO_WTR RADIO_WTR GND GND
0% RADIO_WTR C5722 CELL C5725 23 GND GND 148
1/32W
MF 1 C5703 1 0.1UF
20%
1 0.1UF
20%
46 GND GND 158
01005
0.1UF
10% 4V
01005
4V GND 133
2 X5R 2 X5R 49 GND
2
CERM-X5R
6.3V 01005 GND 112
69 GND
0201
GND 132
CELL 88 GND
70 GND GND 45
VDD_TX_UPC_1P3V 42 VDD_GPS_BB_1P3V 42
63 GND GND 66
VDD_FBRX_2V 42 RADIO_WTR 40 GND GND 84
C5723 CELL 75
RADIO_WTR VDD_GPS_PLL__1P3V
CELL 42
47 GND
I175 C5716 1 100PF
5% RADIO_WTR 87
GND
164
VDD_PRX_2V 42
1 0.1UF
20%
10V C5726
77
GND GND
4V 2 NP0-C0G 1 0.1UF GND
01005 96
2 X5R
01005 4V
20% GND
CELL
CELL 2 X5R
01005
R5708
1
0.00 2 VDD_TX_VCO_1P3V
MAKE_BASE=TRUE 42
43 40 39 38 36 35 PP_LDO11 VDD_MSM_1P8V
CELL 42 1% RADIO_WTR
73 44 1/20W C5706 CELL
RADIO_WTR RADIO_WTR MF VDD_GPS_VCO_1P3V 42
0201
A 1 C5709
1.0UF
C5717
20%
1 0.1UF
4V
1
4V
0.1UF
20% RADIO_WTR A
20% X5R 2 X5R PAGE TITLE
6.3V
2 X5R
0201-1 2 01005
NOSTUFF
CELL
L5702
01005
8.2NH-3%-0.19A-1.6OHM 051-0301 D
1 2 VDD_TX_DA_1P3V 42 Apple Inc. REVISION
R
01005 RADIO_WTR BRANCH B.0.0
C5724 NOTICE OF PROPRIETARY PROPERTY:
1 100PF
5% THE INFORMATION CONTAINED HEREIN IS THE
10V PROPRIETARY PROPERTY OF APPLE INC.
NP0-C0G THE POSESSOR AGREES TO THE FOLLOWING: PAGE
2 01005
NOSTUFF
57 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C1019
WFR TRANSCEIVER
R1016
L1000
U1002
CELL
RADIO_WFR
MAKE_BASE=TRUE
U5801
73 43 42 36 PP_LDO8 VREG_2V 42
WFR1620
D 73 42 38 36
MAKE_BASE=TRUE
PP_LDO1 VREG_1P3V 42 43
BGA
SYM 1 OF 2
GND 1 D
CELL MB1 DC 22 61
48 50_B25_PRX_WFR_IN PRX_MB1_IN RX_OTHER GND
RADIO_WFR 50_B1_B4_PRX_WFR_IN 16
MB2 NO DC 48 PRX_MB2_IN 13
6 PRX_MB3_IN SSBI_PRX_DRX WFR_SSBI 40
R5804 CELL R5802 48 50_B3_PRX_WFR_IN GND
MAKE_BASE=TRUE MAKE_BASE=TRUE MB3 DC 34
VREG_1P3V 1
0 VDD_DIG_1P3V PP_LDO8
0.00 2 VDD_PRX_VCO_WFR_2V 27
2 VREG_1P3V_FILT 1 43 50_WFR_PRX_HB_CA_IN PRX_HB_CA_IN
50_WFR_PRX_LB_CA_IN NC
43 42 43 73 43 42 36
5% RADIO_WFR 1% CELL RADIO_WFR PRX_LB_CA_IN PRX_MB_CA_OUT 5 50_WFR_PRX_MB_CA_OUT

1/20W CELL C5804 CELL 1/20W C5810 41
3 OUT 41
MF MF IN
RADIO_WFR RADIO_WFR 0201 DC 65 50_WFR_DRX_MB_CA_OUT 41
201
1 C5801
1 0.1UF
20%
1 C5803
1 0.1UF
20%
MB1
52 50_B25_DRX_WFR_IN 49 DRX_MB1_IN
DRX_MB_CA_OUT OUT
10UF 4V
X5R
10UF 4V
X5R MB2 NO DC 52 50_B1_B4_DRX_WFR_IN 54 DRX_MB2_IN PRX_BB_IP 29 WFR_BB_PRX_I_P 40
2 01005
20% 20%
6.3V
2 CERM-X5R
2 01005 6.3V
2 CERM-X5R 52 50_B3_DRX_WFR_IN 66 DRX_MB3_IN PRX_BB_IM 28 WFR_BB_PRX_I_N 40
0402-2 CELL 0402-2 MB3 DC 25
43 PRX_BB_QP 30 WFR_BB_PRX_Q_P 40
NC DRX_HB_CA_IN
PRX_BB_QM WFR_BB_PRX_Q_N 40
RADIO_WFR
50_WFR_DRX_LB_CA_IN 36
41 IN DRX_LB_CA_IN 62 WFR_BB_DRX_I_P
VDD_DRX_LO_1P3V 43 VDD_XO_WFR_2V 43 CELL DRX_BB_IP 40
RADIO_WFR RADIO_WFR RADIO_WFR 52 GND DRX_BB_IM 63 WFR_BB_DRX_I_N 40

C5805 C5811 57
DRX_BB_QP 64 WFR_BB_DRX_Q_P
1 0.1UF 1 0.1UF R5803 WFR_RTUNE19 R_TUNE
40
20% 20% 4.75K

1 2 DRX_BB_QM WFR_BB_DRX_Q_N 40
4V 4V 7 XO_IN
X5R X5R 1%
2 01005 2 01005 1/32W
CELL CELL CELL MF
01005
RADIO_WFR
C5815
VDD_DRX_LB_WFR_1P3V 43 1000PF
41 37 50_RF_CLK 1 2 XO_WFR_IN
10% RADIO_WFR
10V C5816
X5R
01005 1 100PF
C CELL
RADIO_WFR
5%
10V
2 NP0-C0G
C
01005
L5801 NOSTUFF
10NH-3%-0.14A-2.1OHM
1 2 VDD_DRX_MB_HB_FE_1P3V 43 VDD1_DRX_BB_2V 43
01005 RADIO_WFR RADIO_WFR
C5806 C5812
1 0.1UF
20%
X5R
1 0.1UF
20%
4V
01005 4V CELL
CELL X5R
RADIO_WFR 2 2 01005 RADIO_WFR
CELL CELL U5801
L5802 WFR1620
10NH-3%-0.14A-2.1OHM
BGA
1 2 VDD_PRX_MBHB_FE_1P3V 43 VDD1_PRX_BB_2V 43
01005 43 VDD_PRX_VCO_WFR_2V 37 VDD_RF2_P_VCO SYM 2 OF 2 GND 46
RADIO_WFR RADIO_WFR PWR_GND
C5807 C5813
43
33 VDD_RF1_P_VCO
VDD_PRX_VCO_WFR_1P3V GND 35
1 0.1UF
20%
1 0.1UF
20%
4V
VDD_PRX_LO_WFR_1P3V
31 VDD_RF1_P_LO 42
4V X5R 43 GND
X5R
2 01005 2 01005 43
44 VDD_RF1_P_PLL
VDD_PRX_PLL_WFR_1P3V GND 53
CELL CELL
43 VDD_PRX_LB_FE_1P3V 15 VDD_RF1_P_LB_FE GND 20
43
VDD1_PRX_BB_2V 23 VDD_RF2_P_BB GND 51
VDD_PRX_LB_FE_1P3V 43
43
10 VDD_RF1_P_MHB_FE
VDD_PRX_MBHB_FE_1P3V GND 41
43 VDD_DRX_LO_1P3V 47 VDD_RF1_D_LO GND 45

43
VDD1_DRX_BB_2V 56 VDD_RF2_D_BB GND 50
CELL
B RADIO_WFR GND 18 B
R5801 43 VDD_DRX_LB_WFR_1P3V39 VDD_RF1_D_LB_FE GND 9
MAKE_BASE=TRUE
1
0.00 2VDD_PRX_VCO_WFR_1P3V PP_LDO11 VDD1_1P8V 43 43 59 VDD_RF1_D_MHB_FE
VDD_DRX_MB_HB_FE_1P3V 11
43 73 44 42 40 39 38 36 35 GND
1%
1/20W
RADIO_WFR RADIO_WFR VDD_DIG_1P3V 24 VDD_RF1_DIG 21
C5808 C5814 43 GND
MF
0201 1 0.1UF
20%
1 0.1UF
20% PWRTERM2GND 14 GND GND 32
4V 4V VDD1_1P8V
X5R X5R 2 VDD_DIO GND 4
2 01005 2 01005 43
CELL CELL 17 VDD_RF2_XO 38

43 VDD_XO_WFR_2V GND
GND 55
40
VDD_PRX_PLL_WFR_1P3V 43
GND
RADIO_WFR
C5809
GND 60
20%
1 0.1UF
4V 48
X5R GND
01005
2 GND 58
CELL
GND 26
GND 8
VDD_PRX_LO_WFR_1P3V 43
RADIO_WFR GND 12
C5802
1 0.1UF
2
A CELL
20% A
PAGE TITLE
4V X5R
01005
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
58 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C1110
QFE DCDC
R1102
L1104
U1101
D D
CELL
CELL RADIO_QPOET
RADIO_QPOET
XW5901 U5901
SHORT-10L-0.25MM-SM L5901
PP_BATT_VCC_QPOET 1 2 VBATT_SW 44 FERR-22-OHM-1A-0.055OHM QFE1100
73 51 50 45 44
QPOET_BATT BGA PP_BATT_VCC_QPOET
NOSTUFF 73 51 50 45 44 PP_BATT_VCC_QPOET 1 2 14 BYP_BATT VDD_BATT 15 44 45 50 51 73
CELL 0201
SHOULD BE PLACED VPA_ET 10 BYP_LOAD VDD_BATT 16
MAX 0.25MM AWAY 1 RADIO_QPOET
C5903
49 48 47 46 44 37
FROM QPOET
10UF 44 VBATT_SW 28 VDD_BUCK VDD_AMP 5 APT_VINPUT 44
20%
XW5902 6.3V
2 CERM-X5R 27 17 CELL
SHORT-10L-0.25MM-SM
0402-2 73 44 GND_SW GND_BUCK VDD_1P8 PP_LDO11 35 36 38 39 40 42 43 44
1 2 GND_SW 44 73
7 QPOET_VSW 1.5UH-1.95A-0.111OHM 73
NOSTUFF 40 35 IN ET_DAC_P AMP_INP VSW_BUCK 23 1 2

PSB25201T-SM
BOTH XW’S ET_DAC_N 2 AMP_INM L5903
RADIO_QPOET
> 1.0MM AMP_OUT 4
40 35 IN
TO CREATE VPA_ET 37 44 46 47 48 49
INDUCTANCE RFFE1_DATA 26 SDATA
49 48 47 46 45 40 35 BI
C_BUCK 11 49 45 37 VPA_APT CELL
21 12 CELL RADIO_QPOET
49 48 47 46 45 40 35 BI RFFE1_CLK SCLK C_BUCK RADIO_QPOET C5907
CRITICAL C5906
13 8 1 470PF
BST_L NC MPP1 C_SW_BUCK
9
1 4.7UF
20% 10V X5R
10%
01005
C 73 51 50 45 44
PP_BATT_VCC_QPOET 1 CELL 2
0805
20 VSW_BOOST
C_SW_BUCK
C_GSM
6
GSM_CAP
10V
2 X5R-CERM
0402
2
VPA_ET_FILTER
CELL
1 RADIO_QPOET
C
2.2UH-20%-0.7A-0.23OHM 19 USID_LSB (USID) R5901
PA_VBAT 18
RADIO_QPOET
22 VPA_BATT 46 47 48 CELL 2.2
GND 49 RADIO_QPOET RADIO_QPOET 5%
CRITICAL TO STAY 1/32W
24 VOUT_BOOST 25 VOUT_BOOST 44 1 C5904 @ 4.7UF TO MEET MF
GND_BOOST 20UF QPOET TIMING 2 01005
L5902 GND 1 20%
2 6.3V
CERM-X5R
GND_AMP 3 0402
(CAN BE CHANGED TO 20UF)
VOUT_BOOST_GND 44 73
B B
BOOST FILTER
I/O @ 1.8V CELL
RADIO_QPOET
L5904
FERR-22-OHM-1A-0.055OHM
73
39 38 36 35 PP_LDO11 44 VOUT_BOOST 1
0201
2 APT_VINPUT
CELL 44
44 43 42 40 RADIO_QPOET
CELL CELL
1 RADIO_QPOET 1 RADIO_QPOET C5905
C5901 C5902
20%
10UF 10UF
20%
1 10UF
20%
2 6.3V 2 6.3V 10V
CERM-X5R CERM-X5R X5R-CERM
2 0402-7
0402-2 0402-2
73 44 VOUT_BOOST_GND
2
XW5903
SHORT-10L-0.25MM-SM
NOSTUFF
1
PP_VCC_MAIN CURRENT SENSE

CELL
U5962 CELL
A BATT --> 68 53 35
73
PP_BATT_VCC
1
CELL INA216A2YFF
WCSP-4 R5962
0.00 2
A
R5961
0.010 A1 IN+ OUT B2 ADC_IMEAS_QPOET 1 RADIO_TO_PMU_ADC_IMEAS_QPOET PAGE TITLE
1%
0402
A2 IN-
0%
1/32W
MF
NOSTUFF
1 C5910
68
CELL: QFE DCDC DRAWING NUMBER SIZE

01005 0.1UF
QPOET <-- 50 45 44
73 51
PP_BATT_VCC_QPOET 2 MF
1/6W GND RADIO_ASM 20%
4V
2 X5R Apple Inc. 051-0301
REVISION
D
B1 01005
R
BRANCH B.0.0
59 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C1208
2G PA
R1200
L1204
U1201
D D
CHANGE TO VBATT!!!!
R6001
600-OHM-25%-0.1A
73 51 50 44 PP_BATT_VCC_QPOET 1 2 73 PP_BATT_VCC_2GPA VPA_APT 37 44 49
CELL 0201-1
CELL OMIT_TABLE OMIT_TABLE
RADIO_2G RADIO_2G RADIO_2G
C6009 CELL RADIO_2G
C6015
1 C6010 1 C6011
1 56PF
5% 20%
1UF
2.2UF
2.2UF
20%
CELL
RADIO_2G
CELL 6.3V 1 10V 20% C6012

RADIO_2G 2 NP0-C0G
01005
X5R
0201
6.3V
2 X5R
6.3V
2 X5R 1 56PF
0201-1 0201-1 5%
C6005 6.3V
100PF NP0-C0G
2 01005 OMIT_TABLE
1 2 RADIO_2G
50_HB_2G_WTR_TX_OUT
41
2
L6001
5% RADIO_2G
3.6NH+/-0.1NH-0.5A
16V
NP0-C0G C6007 1 2 50_HB_2G_ASM_IN 50
01005 CELL
10
1 12PF 0201
4
RADIO_2G RADIO_2G RADIO_2G
5%
16V VBATT V2G
1 C6001 1 C6013
2 CERM 0.5PF 0.2PF
01005
NOSTUFF
U6001 +/-0.05PF
25V
+/-0.05PF
25V
RF5145 2 COG-CERM 2 COG-CERM
50_HB_2G_PA_IN5 HB_RF_IN LGA HB_RF_OUT 12 50_HB_2G_PA_OUT OMIT_TABLE
0201 0201
C 50_LB_2G_PA_IN6 LB_RF_IN LB_RF_OUT 7 50_LB_2G_PA_OUT OMIT_TABLE C
VIO 3 RFFE_VIO 40 46 47 48 49 CELL
50 51 53 RADIO_2G
SCLK RFFE1_CLK
SDATA
1 RFFE1_DATA
35 40 44 46 47
48 49 L6002
2
35 40 44 46 47
48 49
6.2NH-3%-0.4A
CELL GND THRM
1 2 50_LB_2G_ASM_IN 50
RADIO_2G
PAD 0201 CELL
C6006 RADIO_2G RADIO_2G
8
9
11
13
7.0PF 1 C6002 1 C6014
41 50_LB_2G_WTR_TX_OUT 1 2 1.0PF 1.5PF
RADIO_2G RADIO_2G
+/-0.05PF +/-0.1PF
+/-0.1PF 2 25V
C0G-CERM
25V
2 C0G-CERM
0201
1 C6004 16V C6008 0201
0.5PF
+/-0.05PF
NP0-C0G
01005
1
2%
33PF NOSTUFF
16V
2 C0G-CERM
16V
2 NP0-C0G
01005
CELL
01005
NOSTUFF
B B
A A
PAGE TITLE
CELL: 2G PA
DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
60 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C1332
VERY LOW BAND PAD (B13, B17, B28)
R1300
L4215_RF
U1304
CELL
RADIO_VLB_PAD
L6102
6.2NH-3%-0.22A-1.3OHM
D 1
01005
2 50_B28A_ASM_TRX 50 D
1
CELL
L6112
1 C6103
49 48 47 44 37 VPA_ET 1.3PF
18NH-3%-140MA +/-0.1PF
01005 2 16V
NP0-C0G
CELL RADIO_VLB_PAD NOSTUFF
RADIO_VLB_PAD 01005
CELL RADIO_VLB_PAD C6113 RADIO_VLB_PAD
2
RADIO_VLB_PAD 1 47PF
C6106
1 C6112 5%
16V
47PF 2 CERM CELL
100PF 5%
16V
01005 RADIO_VLB_PAD
46 50_B28_WTR_TX_OUT 1 2 2 CERM
01005
NOSTUFF L6103
49 48 47 44 VPA_BATT VLB_ET_RC_FILT 9.1NH-3%-0.17A-1.7OHM
5% PLACE INDUCTOR CLOSE TO PA
10V 1 1 2 50_B28B_ASM_TRX 50
NP0-C0G 1
01005 RADIO_VLB_PAD
CELL R6101 01005
RADIO_VLB_PAD 0.00
L6106 1 0%
22NH-5%-0.1A C6109 1/32W CELL
1UF MF CELL
01005
NOSTUFF 20% NOSTUFF
2 01005 1 L6113
1 C6102
10V
2 X5R 1.5PF
0201 RADIO_VLB_PAD 1.5PF 16V
2 +/-0.1PF 2 NP0-C0G
+/-0.1PF
16V
2 NP0-C0G 01005-1
01005-1 CELL
RADIO_VLB_PAD
RADIO_VLB_PAD RADIO_VLB_PAD
35
29
28
U6103 CELL
CELL BAND17 RADIO_VLB_PAD
CELL VBATVCC1VCC2 RADIO_VLB_PAD LFL15710MTCTD717
C6107 B28A_ANT 22 50_B28A_PAD_ANT C6114 0402 C6117
9.1NH-3%-0.17A-1.7OHM 50_B28_PAD_IN 40 B28IN U6101 B28B_ANT 11 50_B28B_PAD_ANT 9.1NH-3%-0.17A-1.7OHM 100PF
1 2 39 B17IN RF5147 25 PLACE INDUCTOR CLOSE TO PA 1 2 1 2 50_B17_ASM_TRX
46 50_B17_FILTER_TX_OUT 50_B17_PAD_IN B17ANT 50_B17_PAD_ANT 01005 50_B17_PAD_LPF_IN 4 IN OUT 2 50
01005 50_B13_PAD_IN 37 B13IN LGA 8 50_B13_PAD_ANT
C 1
RADIO_VLB_PAD SW1
CELL
RADIO_VLB_PAD
B13ANT
B29_RX_IN 17 50_B29_PAD_ANT 1
CELL
L6114 1
CELL
C6116
GND
50_B17_PAD_LPF_OUT 5%
10V
NP0-C0G
1 C
46 CTRL_VLB_BAND_SELECT_2 3 SW2
CTRL_VLB_BAND_SELECT_1 2.7PF 1.0PF
01005
1
3
RADIO_VLB_PAD L6107 4 +/-0.1PF +/-0.1PF L6117
01005
22NH-5%-0.1A 46
NOSTUFF 2 16V
NP0-C0G 2 16V
NP0-C0G 22NH-5%-0.1A
RX_OUT 01005-1 01005 01005
15 VIO 31 RFFE_VIO_VLB_PAD RADIO_VLB_PAD RADIO_VLB_PAD RADIO_VLB_PAD
2 SCLK 33 RFFE1_CLK 35 40 44 45 47 48 49 CELL NOSTUFF
RADIO_VLB_PAD 2
SDATA 32 RFFE1_DATA 35 40 44 45 47 48 49
C6115
CELL
2.7NH+/-0.1NH-0.370A
C6119 GND THRM 1 2 50_B13_ASM_TRX 50
1.8NH+/-0.1%-0.380A PAD 01005
1
1
2
5
6
7
9
10
12
13
14
16
18
19
20
21
23
24
26
27
30
34
36
38
41
46 50_B13_FILTER_TX_OUT 1 2
1
01005
RADIO_VLB_PAD 1
L6115 L6116
RADIO_VLB_PAD 15NH-3%-140MA
CELL 18NH-3%-140MA 01005
L6108 01005 RADIO_VLB_PAD
22NH-5%-0.1A RADIO_VLB_PAD NOSTUFF
NOSTUFF
01005 RADIO_VLB_PAD
R6102 2
NOSTUFF 2
RFFE_VIO 1
0.00 2 PLACE INDUCTOR CLOSE TO PA
53 51 50 49 48 47 45 40
2 1/32W
0%
MF
CELL
CELL
01005 1 C6121 L6101
47PF 5.1NH-3%-0.250A
5%
2 16V
CERM
01005
1 2 50_B29_ASM_TRX 50
RADIO_VLB_PAD 01005
1 RADIO_VLB_PAD
NOSTUFF
B RADIO_VLB_PAD
L6111
B
01005
18NH-3%-140MA
CELL
2 RADIO_WTR
CELL
C6120 L6118
100PF 22NH-100MA
1 2 1 2 50_B13_B17_B28_B29_PRX_WTR_IN
50_B13_B17_B28_B29_PAD_RX 50_B13_B17_B28_B29_MCH_RX
0201 41
46 CTRL_VLB_BAND_SELECT_1 5%
16V RADIO_WTR
PP_LDO14_RFSW
CELL 36 47 73 NP0-C0G
01005 C6118
46
CTRL_VLB_BAND_SELECT_2 RADIO_VLB_PAD 1 1.0PF
C6101 CELL +/-0.1PF
CELL CELL RADIO_VLB_PAD
RADIO_VLB_PAD
RADIO_VLB_PAD 1 47PF
5% 2 01005
C6105 C6108 16V FL6101
SAW-BAND13-TX-INTERSTAGE NP0-C0G
NOSTUFF
CERM
2 01005
1 100PF 1 100PF CELL
B8817 16V
1
5%
10V
5%
10V
VDD
C6111 LGA
2 NP0-C0G
01005 2 NP0-C0G 47PF
01005 1 INPUT_UNBAL
U6102 1 2 50_B13_TX_FILT_IN OUTPUT_UNBAL 4 50_B13_FILTER_TX_OUT 46
GND
GND
GND
CXA2973GC 5%
16V
1
RADIO_VLB_PAD
3 V1 BGA RF1 6 50_VLB_SW_MCH_IN 46 CERM CELL
2 V2 RADIO_VLB_PAD 01005
2
3
5
CELL RF2 5 50_B28_WTR_TX_OUT 46
RADIO_VLB_PAD L6110
CELL 7 50_B13_WTR_TX_OUT 18NH-3%-0.140A
RF3 01005-1
RADIO_VLB_PAD RF4 4 50_B17_WTR_TX_OUT
C6104 GND CELL
100PF
8
9
RADIO_VLB_PAD 2 CELL
1
50_B13_B17_B28_WTR_TX_OUT 2 50_VLB_SW_MCH_IN C6110 RADIO_VLB_PAD
A 41
5%
46
5.6NH-3%-0.23A-1.3OHM
FL6102
SAW-BAND17-TX-INTERSTAGE
A
10V 1 2 50_B17_WTR_FILT_IN PAGE TITLE
1
RADIO_VLB_PAD
NP0-C0G
01005
1
RADIO_VLB_PAD
01005
1
B8822
LGA
CELL: VLB PAD DRAWING NUMBER SIZE
L6104 L6105
22NH-5%-0.1A 01005
22NH-5%-0.1A
NOSTUFF
1 INPUT_UNBAL OUTPUT_UNBAL 4 50_B17_FILTER_TX_OUT Apple Inc. 051-0301 D
NOSTUFF
01005 46 REVISION
L6109
GND
GND
GND
V2 V1 BAND 15NH-3%-0.140A
R
BRANCH B.0.0
2 2 0 1 B28 01005
2
3
5
RADIO_VLB_PAD
1 0 B13 NOSTUFF
1 1 B17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
61 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C4317_RF
LOW BAND PAD (B8, B26, B20)
R1400
L4316_RF
U1402
CELL
RADIO_WTR CELL
C6211 L6201
100PF
22NH-100MA RADIO_WTR
D 1 2 50_B20_MATCH_1 1
0201
2 50_B20_PRX_WTR_IN 41 D
RADIO_WTR
5%
16V C6214
NP0-C0G 1 0.8PF
01005
+/-0.05PF
16V
2 C0G-CERM
01005
NOSTUFF
CELL CELL
RADIO_WTR RADIO_WTR
C6212 L6211
100PF 15NH-3%-0.140A
1 2 50_B26_MATCH_2 1 2 50_B26_PRX_WTR_IN 41
01005
5%
16V
NP0-C0G
01005 CELL
VPA_ET 37 44 46 48 49 RADIO_WTR
L6212
CELL
1
0.00 2 50_B26_MATCH_1
RADIO_LB_PAD
CAPACITOR THAT’S SUPPOSED TO GO HERE IS LOCATED ON
C6204 MID BAND PAD. THE 2 PAD’S NEED TO SHARE DECOUPLING 0%
1/32W
MF 1 C6216
01005
47 50_B20_WTR_TX_OUT 1100PF
2 49 48 46 44 VPA_BATT 0.9PF
+/-0.1PF
2 16V
NP0-C0G
5%
10V CELL 01005
NP0-C0G 1 RADIO_LB_PAD
C6218 RADIO_WTR
01005 CELL
RADIO_LB_PAD 1 47PF
L6204 5%
16V CELL CELL
2 CERM
C 01005 01005
C6213
RADIO_WTR RADIO_WTR
L6213 C
22NH-5%-0.1A 100PF 15NH-3%-0.140A
2 1 250_B8_MATCH_1 1
NOSTUFF 2 50_B8_PRX_WTR_IN 41
01005
5%
16V
36
NP0-C0G
5
6
01005 1 C6215
VBATT VCC1 VCC2 0.9PF
+/-0.1PF
CELL 2 16V
NP0-C0G
47 CTRL_LB_BAND_SELECT_1 28 SW1 RADIO_LB_PAD B20RX 25 50_B20_PAD_RX 01005
C6203 47 CTRL_LB_BAND_SELECT_2 27 SW2 U6202 B26RX 20 50_B26_PAD_RX RADIO_WTR

2.7NH+/-0.1NH-0.370A R6201 34
B20IN TQF6410 B8RX 10 50_B8_PAD_RX CELL
100PF 50_B20_PAD_IN LGA
47 50_B26_WTR_TX_OUT 1 2 50_B26_PAD_IN_MATCH 1 2 50_B26_PAD_IN 33 B26IN 22 50_B20_PAD_ANT
01005
50_B8_PAD_IN 31 B8IN B20ANT CELL
RADIO_LB_PAD
5% B26ANT 17 50_B26_PAD_ANT RADIO_LB_PAD
RADIO_LB_PAD
CELL 1 6.3V
CERM 1
B8ANT 14 50_B8_PAD_ANT C6208
RADIO_LB_PAD
01005 R6202 3.0NH+/-0.1NH-0.360A
RADIO_LB_PAD 0.00 VIO 3 RFFE_VIO 40 45 46 48 49 50 51 53
1 2
L6205 CELL 0% 50_B20_ASM_TRX 50
22NH-5%-0.1A 1/32W SCLK 1 RFFE1_CLK 35 40 44 45 46 48 49
01005
MF
01005
2 01005 SDATA 2 RFFE1_DATA 35 40 44 45 46 48 49
1 1
NOSTUFF NOSTUFF
RADIO_LB_PAD
2 CELL
PLACE INDUCTOR CLOSE TO PA RADIO_LB_PAD
THRM
GND L6209 L6210
PAD 1 C6217
5%
18NH-3%-140MA 12NH-3%-140MA
CELL 47PF 01005 01005
4
7
8
9
11
12
13
15
16
18
19
21
23
24
26
29
30
32
35
37
38
39
40
41
42
43
44
45
46
47
48
CERM NOSTUFF NOSTUFF
C6202 RADIO_LB_PAD
L6206 2
16V
6.8NH-3%-0.210A 100PF 01005 2 2
47 50_B8_WTR_TX_OUT 1
01005
2 50_B8_PAD_IN_MATCH 1 2
5% CELL
RADIO_LB_PAD
OMIT_TABLE
B 1
RADIO_LB_PAD
C6220
10V
NP0-C0G C6207 B
01005 5.6NH-3%-0.23A-1.3OHM
3.3PF
+/-0.1PF
16V
1 2 50_B26_ASM_TRX 50
2 NP0-C0G 01005
NOSTUFF
01005
1
PLACE INDUCTOR CLOSE TO PA CELL
RADIO_LB_PAD
RADIO_LB_PAD RADIO_LB_PAD
L6208
1 C6209
01005 1.0PF
12NH-3%-140MA
NOSTUFF +/-0.1PF
16V
2 01
NP00-C0G
05
2
PP_LDO14_RFSW 36 46 73 CELL
CELL C6206
RADIO_LB_PAD 5.6PF
C6205 1 2 50_B8_ASM_TRX 50
1 47PF
5% +/-0.1PF
1
16V 16V 1
VDD 2 CERM
01005
1 NP0-C0G-CERM
01005 CELL
RADIO_LB_PAD
CTRL_LB_BAND_SELECT_1 RADIO_LB_PAD RADIO_LB_PAD
47
47 CTRL_LB_BAND_SELECT_2 U6201 L6207 C6210

CXA2973GC PLACE INDUCTOR CLOSE TO PA 12NH-3%-140MA 01005
3 V1 BGA RF1 6 50_LB_SW_MCH_IN 47 01005
RADIO_LB_PAD NOSTUFF 15NH-3%-0.140A
2 V2 RF2 5 50_B8_WTR_TX_OUT 47
CELL CELL CELL 2
RADIO_LB_PAD RADIO_LB_PAD 7 50_B20_WTR_TX_OUT 47 V2 V1 BAND 2
C6219
100PF C6201 RF3
RF4 4 50_B26_WTR_TX_OUT 47
0 1 B8
8.2NH-3%-0.19A-1.6OHM GND
50_B8_B26_B20_WTR_TX_OUT 1 2 50_LB_WTR_BLOCK_OUT 1 0
1 B20
8
9
1 2 50_LB_SW_MCH_IN
A 41
5%
01005 47
1 B26 A
WTR OUTPUT HAS DC 10V
01005 PAGE TITLE
FIRST SHUNT MUST

BE A CAPACITOR.
NP0-C0G
1
RADIO_LB_PAD
L6202 1
RADIO_LB_PAD
L6203
CELL: LB PAD DRAWING NUMBER SIZE
3.3PF 3.3PF 051-0301 D
2 +/-0.1PF
+/-0.1PF
2 16V
Apple Inc. REVISION
NP0-C0G
16V NP0-C0G R
01005 01005
CELL
BRANCH B.0.0
CELL NOTICE OF PROPRIETARY PROPERTY:
62 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C1510
MID BAND PAD (B1, B25, B3, B4, B34, B39)
R1500
L4409_RF
U1501
D D
CELL
RADIO_WFR CELL
C6316 L6306
100PF 1.2NH+/-0.1NH-0.550A
1 2 50_B3_MATCH_1 1 2 50_B3_PRX_WFR_IN 43
01005 CELL
5% RADIO_WFR CELL RADIO_WFR
16V
NP0-C0G
01005 L6307 C6319
3.3NH+/-0.1NH-290MA 33PF
1 2 1 2
01005 50_B3_MATCH_1_MATCH
5%
RADIO_WFR 16V
NP0-C0G-CERM
01005
CELL
RADIO_WFR
CELL VPA_ET
RADIO_MB_PAD
37 44 46 47 49
L6304
1.2NH+/-0.1NH-0.550A
C6308 RADIO_MB_PAD
1 47PF C6310
1 2 50_B1_B4_PRX_WFR_IN 43
5% CELL
01005 RADIO_WFR
16V 1 47PF
16V RADIO_MB_PAD
2 CERM 5%
01005
2 CERM
L6309 L6305
01005 3.6NH+/-0.1NH-180MA 3.0NH+/-0.1NH-0.360A
NOSTUFF 1 2 1 2
01005
01005
MB_ET_RC_FILT NOSTUFF
CELL CELL
1 RADIO_MB_PAD RADIO_WFR
C 49 47 46 44 VPA_BATT
CELL
RADIO_MB_PAD
R6302
0.00
RADIO_WFR
C6317 L6308 C
0% 100PF 1.8NH+/-0.1%-0.380A
1 C6309 1/32W
MF 1 2 50_B25_MATCH_1 1 2 50_B25_PRX_WFR_IN
1UF 2 01005
43
20% 01005
10V
2 X5R NOSTUFF 5% 1
0201 16V
NP0-C0G CELL
01005
L6303
26
CELL 2.7NH+/-0.1NH-0.370A
36
27
RADIO_MB_PAD 01005
RADIO_WFR CELL
VBATT
VCC1
VCC2
C6304 C6318
100PF CELL B3RX 12 50_B3_PAD_RX
2 33PF
RADIO_WFR
50_B3_B4_WTR_TX_OUT 1 2 35
50_B3_B4_PAD_IN B3/4IN 1 2
B1/4RX 10 50_B1_B4_PAD_RX
41
RADIO_MB_PAD CELL
RADIO_MB_PAD 50_B25_MATCH_2
5%
16V
U6301 B25RX 5 50_B25_PAD_RX U6302
5%
16V
NP0-C0G
RADIO_MB_PAD
01005 RADIO_MB_PAD AFEM-8020-AP1 CELL BAND34-39 NP0-C0G-CERM
01005 CELL
C6302 C6307 LGA RADIO_MB_PAD LFL151G95TCSD734 RADIO_MB_PAD
1 18PF 1 18PF B1/3/4ANT 16 50_B1_B3_B4_PAD_ANT
8
R6301 0402 R6303
2% 34 B1/25/34/39IN
50_B1_B25_B34_B39_PAD_IN B25ANT 50_B25_PAD_ANT 2.2NH+/-0.1NH-0.380A 1.4NH+/-0.1NH-0.4A
16V 01005 24 50_B34_B39_PAD_ANT
2 CERM
01005 2 B34_39_OUT 1 2 4 IN OUT 2 50_B34_B39_LPF_OUT1 2 50_B34_B39_HB_SWITCH_IN 51
CERM
NOSTUFF NOSTUFF VIO 01005 50_B34_B39_LPF_IN 01005
16V 1 RFFE_VIO 40 45 46 47 49 50
CELL RFFE1_CLK 51 53 GND
2%
SCLK 2 35 40 44 45 46 47
1 C6301 C6313
RADIO_MB_PAD 49
0.5PF
SDATA 3
1
3
RFFE1_DATA 35 40 44 45 46 47
+/-0.05PF 1 12PF
49
C6305 16V
2 C0G-CERM 5%
100PF 16V
EPAD
EPAD
EPAD
EPAD
EPAD
EPAD
EPAD
EPAD
EPAD
EPAD
EPAD
EPAD
01005
2 CERM
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
41 50_B1_B25_B34_B39_WTR_TX_OUT 1 2 RADIO_MB_PAD 01005
CELL NOSTUFF
5% RADIO_MB_PAD
4
6
7
9
11
14
13
15
17
18
19
20
21
22
23
25
28
29
30
31
32
33
37
38
39
40
41
42
43
44
45
46
47
48
16V CELL
NP0-C0G RADIO_MB_PAD
RADIO_MB_PAD RADIO_MB_PAD
01005 L6302
B 1
C6303
18PF 1
C6306
18PF
3.0NH+/-0.1NH-0.6A
1 2
B
2% 0201 50_B1_B3_B4_ASM_TRX 50
16V
2 CERM
01005 2 2%
16V 1 C6312 1 C6314
NOSTUFF CERM
NOSTUFF
01005 0.5PF 15PF
+/-0.05PF 5%
2 25V
COG-CERM 2 25V
NPO
0201 0201
CELL NOSTUFF
CELL CELL
L6301 C6315
6.8NH-3%-0.4A-0.3OHM 6.8NH-3%-0.4A-0.3OHM
1 2 50_B25_ANT_MATCH 1 2 50_B25_ASM_TRX 50
0201
NOSTUFF 0201
1 C6311 1 C6320
1.2PF
+/-0.1PF 1.2PF
25V +/-0.1PF
2 C0G-CERM
0201 2 16V
NP0-C0G
01005-1
RADIO_MB_PAD
CELL
RADIO_MB_PAD
A A
PAGE TITLE
CELL: MB PAD DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
63 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C1614
HIGH BAND PAD (B7, B38, B40, B41, XGP)
R1600
L1616
U1601
CELL
RADIO_WTR CELL
C6419 L6414
100PF 3.3NH+/-0.1NH-290MA
D 1 2 50_B7_MATCH_11
01005
2 50_B7_PRX_WTR_IN 41
CELL
D
RADIO_WTR
5%
16V
NP0-C0G C6420
01005 1.8PF
VPA_ET 37 44 46 47 48
1 2
RADIO_HB_PAD
CELL C6409 CELL 16V

+/-0.1PF
RADIO_HB_PAD NP0-C0G
RADIO_HB_PAD 1
5%
47PF L6410
01005
C6406 16V 3.9PF
1 47PF 2 CERM
01005 1
5% 2 50_B7_ASM_TRX 50
16V NOSTUFF
2 CERM
01005 +/-0.1PF
HB_ET_RC_FILT 1 25V RADIO_HB_PAD
C0G-CERM
CELL 0201 1 C6417
RADIO_HB_PAD
C6413 10PF
1 5%
CELL CELL R6401 5.6NH+/-3%-0.4A 2 25V
CER
RADIO_HB_PAD RADIO_HB_PAD 0.00 0201
0201
0% RADIO_HB_PAD
L6406 C6404 1/32W NOSTUFF
1.6NH+/-0.1NH-0.390A 100PF MF
CELL
2 01005 2
RADIO_HB_PAD
41 50_B7_WTR_TX_OUT 1 2 50_B7_PAD_MTCH 1 2 NOSTUFF
01005
5%
L6413
16V 10PF
CELL NP0-C0G
RADIO_HB_PAD 01005
1 2 50_B41B_FILTER_IN 49
C6402 48 47 46 44 VPA_BATT VPA_APT 37 44 45
CELL 5%
1 1.0PF 1
RADIO_HB_PAD RADIO_HB_PAD
C6408 1
RADIO_HB_PAD 25V
CER
1
+/-0.1PF
16V
C6407 C6411 0201
2 NP0-C0G
01005 1UF 1 1000PF 10PF RADIO_HB_PAD
20%
10V
2 X5R
10%
10V 2
5%
25V L6409
0201
X5R
2 01005 CER 0201 3.9NH+/-0.1NH-0.5A
NOSTUFF 0201
NOSTUFF CELL
C C
VBATT 24
VCC1 21
VCC2 20
VAPT 19
2
CELL
CELL
RADIO_HB_PAD CELL B7RX 11 50_B7_RX_PAD OMIT_TABLE
FL6403
CELL RADIO_HB_PAD TX-BAND40-LTE CELL
50_B7_PAD_IN 25 B7IN
RADIO_HB_PAD
B7ANT 15 50_B7_ANT_PAD SAFEA2G35MB0F57 RADIO_HB_PAD
L6401 C6403 U6401 L6402 LGA
0.7NH+/-0.1NH-0.63A 100PF TQF6430 B41B 7 50_B41B_TX_PAD 1.0NH+/-0.1NH-0.75A L6415
50_B40_B38_B41_WTR_TX_OUT 1 2 50_B38_B40_B41_PAD_MTCH1 2 50_B38_B40_B41_PAD_IN 26 LGA 3 50_B40_TX_PAD 1 2 50_B40_TX_MATCH 1 UNB_PORT1 50_B40_TX_FILT_OUT 0
41
01005 B38_40_41 B40B 0201 UNB_PORT2 4 1 2 50_B40_TX_HB_SWITCH_IN 51
5
5% B41C 50_B41C_TX_PAD GND 5%
RADIO_HB_PAD RADIO_HB_PAD 1/20W
16V RADIO_HB_PAD B40A/B41A 9 50_B40A_B41A_TX_PAD RADIO_HB_PAD MF 1
NP0-C0G 1 C6422 201
RADIO_HB_PAD
01005 C6405 RFFE_VIO 1 C6421
2
3
5
10PF RADIO_HB_PAD
1 C6401 1 2.7PF VIO 27 40 45 46 47 48 50 51 53
1.1PF 5% C6424
1PF +/-0.1PF SCLK 28 RFFE1_CLK +/-0.1PF 2 25V
+/-0.1PF 16V 35 40 44 45 46 47 48
2 25V CER 3.9NH+/-0.1NH-0.5A
2 16V
NP0-C0G 2 NP0-C0G
01005-1
SDATA 1 RFFE1_DATA 35 40 44 45 46 47 48
CERM
0201
0201 0201
CELL
01005 NOSTUFF
NOSTUFF OMIT_TABLE
CELL
EPAD
2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
CELL
RADIO_HB_PAD CELL
1 RADIO_HB_PAD
C6425
2
4
6
8
10
13
12
14
16
17
18
22
23
29
5%
10PF C6414
25V 1
0 2 50_B41C_FILTER_IN
2 CER 49
0201 5%
1/20W
1 CELL MF RADIO_HB_PAD
201
RADIO_HB_PAD
1 L6405 50_B40A_TX_HB_SWITCH_IN 51
C6410 10PF
5% 1 CELL
6.2NH-3%-0.4A 25V
2 CER 0201
0201 RADIO_HB_PAD
NOSTUFF
L6407
B 2 4.3NH+/-3%-0.5A
0201
B
CELL
CELL FL6402 2
RADIO_HB_PAD SAW-BAND-40A-41A-TDD-LX
C6415 7
885058
4
1.1PF ANT_B40A B40A_PORT
LGA 1
50_B41B_TX_HB_SWITCH_IN 51 1 2 50_B40A_B41A_FILTER_IN 8 ANT_B41A B41A_PORT 50_B41A_TX_HB_SWITCH_IN 51
+/-0.1PF
GND
GND
GND
GND
GND
GND
CELL 1 25V 1
RADIO_HB_PAD CERM CELL
CELL 1 0201
FL6401 RADIO_HB_PAD 1 RADIO_HB_PAD
10
9
6
5
2
3
SAW-BAND-41B-41C-TDD-TX L6411 RADIO_HB_PAD
RADIO_HB_PAD
L6408
SAWEN2G58QA0F57 6.2NH-3%-0.4A C6412 7.5NH+/-0.3%-0.4A
49
1 RF1/
50_B41B_FILTER_INB41BIN
RF2/
B41BOUT
9 0201
3.3NH+/-0.1NH-0.5A L6404 0201
4 RF3/ LGA RF4/ 6 0201 1.5NH+/-0.1NH-1.0A
B41CIN B41COUT
2 0201 2
GND
GND
GND
GND
GND
GND
CELL
2 CELL
2
2
3
5
7
8
10
49 50_B41C_FILTER_IN
50_B41C_HB_SWITCH_IN 51
1
1
RADIO_HB_PAD
RADIO_HB_PAD
C6416 L6412
7.5NH+/-0.3%-0.4A
0201 5.1NH-3%-0.4A
CELL 0201
CELL
A 2
2 A
PAGE TITLE
CELL: HB PAD DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
64 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C1702
ANTENNA SWITCH
R1700
L4608_RF
U1702
D D
CELL
R6524
73 PP_BATT_VCC_QPOET_ASM 1
0.00 2 PP_BATT_VCC_QPOET 44 45 51 73
0%
1/32W
MF
01005
RADIO_ASM
CELL
RADIO_ASM
C6501
1 47PF
5%
16V
2 CERM
01005
51 50_HB_SWITCH_TX
C RADIO_ASM C
L6505
29
RADIO_ASM
50_HB_SWITCH_RX 1
0.00 250_HB_SW_RX_ASM_MCH
51
VDD CELL
0% CELL
CELL FL6501 1/32W
1 U6501 R6502
RADIO_ASM BAND34-39 MF
01005
RF1
0.00
L6501 SAWFD1G90LC0F57
LGA
CELL 2 RF3 RF5159
LGA
FWD/REV 32 50_FWD_REV_CPL_OUT 1
0%
2 50_FWD_OR_REV_RF 41
2.7NH+/-0.1NH-0.370A 49 50_B7_ASM_TRX 3 RF7
1 INPUT CELL RADIO_ASM
41 50_B34_B39_PRX_WTR_IN 1
01005
2 50_B34_B39_FILT_RX RADIO_ASM OUT_FIL1 9 4
1
R6501 1/32W
MF
1
50_B39_RX_ASM_OUT
22
RX1
105
01005 R6503
1 OUT_FIL2 6 50_B34_RX_ASM_OUT TRX6 1% RADIO_ASM 105
50_B1_B3_B4_ASM_TRX 23 21 1/32W 1%
CELL 48 TRX7 A2 NC MF 1/32W
RADIO_ASM GND 50_B25_ASM_TRX 24 TRX8 2 01005
RADIO_ASM
MF
01005
L6502 48
NOSTUFF 2RADIO_ASM
2
3
4
5
7
8
10
3.0NH+/-0.1NH-0.360A 12 HBTX NOSTUFF

45 50_HB_2G_ASM_IN
01005
RADIO_ASM
50_DCS_PCS_ASM_OUT 20 HBRF2
2 8
46 50_B17_ASM_TRX TRX2
47 50_B8_ASM_TRX 18 TRX3
46 50_B28A_ASM_TRX 9 TRX0
46 50_B28B_ASM_TRX 10 TRX1
47 50_B26_ASM_TRX 16 5 50_ANT_CONN
TRX4 A1 55
46 50_B13_ASM_TRX 17 TRX5
50_B20_ASM_TRX 11 1
47 TRX11
50_B29_ASM_TRX 7 26 RFFE_VIO_ASM
46 RX2 VIO
SCLK 28 RFFE2_CLK L6506
45 50_LB_2G_ASM_IN 14 LBTX 35 40 51 53
SDATA 27 RFFE2_DATA 35 40 51 53
33NH-5%-120MA-2.95OHM
0201
1 1 19 LBRF2 NOSTUFF
NC
B RADIO_ASM RADIO_ASM GND CELL
RADIO_ASM 2
B
L6503 L6504 1 C6525
13
15
25
30
6
31
33
1.0NH+/-0.1NH-0.22A-0.9OHM 1.0NH+/-0.1NH-0.22A-0.9OHM RADIO_ASM
01005 01005 RADIO_ASM
47PF
NOSTUFF NOSTUFF 5%
2
16V CELL
CERM
01005
RADIO_ASM
2
RADIO_ASM
2 R6526
1
0.00
2 RFFE_VIO 40 45 46 47 48 49 51 53
0%
FL6502 1/32W
SAWFD1G84KC0F57 MF
01005
CELL FILTER RADIO_ASM
C6504 LGA
CELL
0.00 2 1 COMBINE OUT RADIO_ASM
1 50_DCS_PCS_FILT_MATCH PCS IN 6 50_PCS_FILT_OUT 52
0% DCS IN 9 50_DCS_FILT_OUT 52
1/32W
MF 1
01005
CELL GND
L6508
10
8
7
5
3
2
4
4.3NH-3%-0.270A
01005
A A
PAGE TITLE
CELL: ANTENNA SWITCH DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
65 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
HIGH BAND SWITCH

D D
L6603
0.3NH+/-0.1NH-0.990A
41 50_B40A_PRX_WTR_IN 1 2 50_B40A_PRX_FILTER CELL
01005
RADIO_HBSWITCH R6627
CELL 1
73 PP_BATT_VCC_QPOET_HBS 1
0.00
2 PP_BATT_VCC_QPOET 44 45 50 73
RADIO_HBSWITCH 0%
L6605 CELL
RADIO_HBSWITCH
CELL
RADIO_HBSWITCH
1/32W
MF
1.8NH+/-0.1%-0.380A RADIO_HBSWITCH 01005
01005
CELL
FL6602 C6607
SAW-BAND-40A-41A-TDD-RX 1 47PF RADIO_ASM
885055
9 RX_B40A
C6606 5%
16V
2 0.00 2
6 RX_B41A LGA ANT 2 50_B40A_B41A_RX_MATCH 1 2 CERM
01005
0%
1/32W
1
GND
GND
GND
GND
GND
GND
GND
MF
01005 CELL
1 VBATT
RADIO_HBSWITCH
CELL
U6601 C
10
8
7
5
4
3
1
C RADIO_HBSWITCH
RADIO_HBSWITCH
RADIO_HBSWITCH
L6607 49 50_B40_TX_HB_SWITCH_IN 11 TX1 CXM3652UR RAIO_HBSWITCH
C6602 2.5NH+/-0.1NH-0.370A 50_B34_B39_HB_SWITCH_IN 12 UQFN
L6602 3.3NH+/-0.1NH-290MA
48
7
TX2
L6609
10PF CELL
01005 49 50_B40A_TX_HB_SWITCH_IN TX3
50_B41A_TX_HB_SWITCH_IN 8 0
41 50_B41A_PRX_WTR_IN 1 2 50_B41A_PRX_MATCH1 1 2 50_B41A_PRX_FILTER 49 TX4 TX RF1 5 50_HB_SWITCH_TX_OUT 1 2 50_HB_SWITCH_TX 50
2
01005 49 50_B41B_TX_HB_SWITCH_IN 9 TX5 5%
5% 1/20W
16V 1 49 50_B41C_HB_SWITCH_IN 10 TX6 MF
CERM RADIO_HBSWITCH 201
01005
CELL RADIO_HBSWITCH CELL
L6601 CELL C6605 14 RX1
3.3NH+/-0.1NH-290MA 100PF 50_B40A_B41A_RX
01005 50_B40B_RX_MATCH 1 2 50_B40B_RX 13 RX2 RX RF1 16 50_HB_SWITCH_RX 50
CELL 15 RX3
5% 1
50_B38X_RX
2 10V
NP0-C0G RADIO_HBSWITCH 53 50 49 48 47 46 45 40 RFFE_VIO 4 VIO
50_B41A_PRX_MATCH2 01005
CELL L6608 53 50 40 35 RFFE2_CLK 3 SCLK
1
C6601 8.2NH-3%-0.19A-1.6OHM 53 50 40 35 RFFE2_DATA 2 SDATA
01005
0.00 CELL THRM
0% GND PAD
1/32W
MF 2
17
2 01005
RADIO_HBSWITCH
CELL CELL
RADIO_HBSWITCH
CELL
RADIO_HBSWITCH RADIO_HBSWITCH FL6601 RADIO_HBSWITCH
C6608 C6603 SAW-BAND-40B-38X-TDD-RX
1.8NH+/-0.1%-0.380A 1.5NH+/-0.1NH-0.400A 885056
9
C6604
50_B40B_B38X_PRX_WTR_IN 1 2 50_B40B_B38X_PRX_MATCH2 1 2 2 RF1/ANTRF3/RX_B40B 100PF
LGA
RF2/RX_B38X 6
41
50_B38X_RX_MATCH 1 2
01005 01005 50_B40B_B38X_PRX_FILTER
GND
GND
GND
GND
GND
GND
GND
5% 1
10V
RADIO_HBSWITCH NP0-C0G RADIO_HBSWITCH
B CELL
1 L6604
1PF
01005
L6606 B
1
3
4
5
7
8
10
CELL
+/-0.1PF 2.7NH+/-0.1NH-0.370A
16V RADIO_HBSWITCH
NP0-C0G 01005
2 CELL
CELL
01005
2
A A
PAGE TITLE
CELL: HB SWITCH DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C4826_RF
RX DIVERSITY (1 OF 2)
R1800
L1829
U1801
MIDBAND
MIDBAND DIVERSITY - WFR HIGHBAND DIVERSITY - WTR LOWBAND DIVERSITY - WTR D
D CELL
RADIO_WFR
CELL
CELL CELL
RADIO_WTR
L6706 L6711 RADIO_WTR OMIT_TABLE RADIO_WTR
2.0NH+/-0.1NH-0.380A C6711 L6720
3.0NH+/-0.1NH-0.360A 100PF C6717
43 50_B1_B4_DRX_WFR_IN 1 2 50_B1_B4_DRX_DSM 53
22NH-3%-0.12A-3.2OHM 100PF
41
1
50_B7_DRX_WTR_IN 2 1
50_B7_DRX_WTR_MCH 2 50_B7_DRX_DSM 53
01005 41 50_B8_B28B_DRX_WTR_IN 1 2 50_B8_B28B_DRX_WTR_MCH 1 2 50_B8_B28B_DRX_DSM 53
CELL CELL 01005
CELL 5% 16V01005 01005
RADIO_WFR RADIO_WTR RADIO_WTR NP0-C0G RADIO_WTR 5%
CELL 16V
L6703 C6707
NP0-C0G
01005
2.5NH+/-0.1NH-0.370A 1.1PF R6704 RADIO_WTR
1 2 1 2 50_B7_DRX_MATCH 1
0.00 2 1 C6716
0.5PF
01005 0% +/-0.05PF
+/-0.1PF 1/32W 16V
2 C0G-CERM
16V MF
NP0-C0G 01005 01005
01005
CELL CELL
CELL CELL CELL
RADIO_WFR RADIO_WFR RADIO_WTR
RADIO_WTR RADIO_WTR
L6705 C6704 R6702 L6719
2.5NH+/-0.1NH-0.370A 100PF 0.5NH-+/-0.1NH-0.73-0.1OHM C6718
22NH-3%-0.12A-3.2OHM 100PF
43 50_B3_DRX_WFR_IN 1 2 1 2 50_B3_DRX_DSM 53 41 50_B38X_DRX_WTR_IN1 2 50_B38X_DRX_DSM 53
CELL 41 50_B13_B17_DRX_WTR_IN 1 2 1 2 50_B13_B17_DRX_DSM 53
0100550_B3_DRX_WFR_MCH
5% 16V01005
01005
01005
RADIO_WFR CELL 50_B13_B17_DRX_WTR_MCH
CELL NP0-C0G RADIO_WTR 5%
C6719 L6701 CELL
10V
NP0-C0G
33PF2.7NH+/-0.1NH-0.370A L6712 1 C6720
01005
1 2 1 2 2.0NH+/-0.1NH-0.380A
0.5PF
01005 1 2 +/-0.05PF
C 5%
16V 50_B3_DRX_WFR_MCH_MATCH
NP0-C0G-CERM
01005
16V
2 C0G-CERM
01005
C
01005
CELL
CELL CELL CELL CELL
RADIO_WFR RADIO_WTR
RADIO_WFR RADIO_WTR RADIO_WTR
L6704 C6703 R6703 L6721
2.0NH+/-0.1NH-0.380A 100PF 0.5NH-+/-0.1NH-0.73-0.1OHM C6701
22NH-3%-0.12A-3.2OHM 100PF
43 50_B25_DRX_WFR_IN 1 2 1 2 50_B25_DRX_DSM 53 41 50_B40_DRX_WTR_IN 1 2 50_B40_DRX_FILTER 53 50_B20_B29_DRX_DSM
41 50_B20_B29_DRX_WTR_IN 1 2 1 2 53
CELL 01005
CELL 50_B25_DRX_WFR_MCH
5% 16V01005
01005
01005
50_B20_B29_DRX_WTR_MCH
RADIO_WFR RADIO_WFR NP0-C0G 5%
CELL 10V
C6702 L6702 RADIO_WTR
CELL NP0-C0G
01005
33PF 2.7NH+/-0.1NH-0.370A 1 C6721
1 2 1 2
L6713 0.8PF
1.8NH+/-0.1%-0.380A +/-0.05PF
5%
01005 2 16V
C0G-CERM
16V 50_B25_DRX_MATCH 1 2
01005
NP0-C0G-CERM 01005
01005
CELL CELL
CELL
CELL RADIO_WTR RADIO_WTR
RADIO_WTR RADIO_WTR
C6712 C6715 L6722
R6701 100PF 100PF 6.8NH-3%-0.210A
0.00 2 50_B26_B28A_DRX_DSM
MIDBAND DIVERSITY - WTR 41 50_B41A_DRX_WTR_IN
CELL 0%
1/32W
1
CELL
1
50_B41A_DRX_WTR_MCH
2
5% 16V01005
50_B41A_DRX_FILTER 53 41 50_B26_B28A_DRX_WTR_IN 1
5%
2
50_B26_B28A_DRX_WTR_MCH
1
01005
2 53
CELL RADIO_WTR01005
MF RADIO_WTR NP0-C0G 16V
NP0-C0G 1 CELL
B RADIO_WTR
L6707
C6708
15PF 2.0NH+/-0.1NH-0.380A
L6714 01005
RADIO_WTR B
2.0NH+/-0.1NH-0.380A 1 2 1 2 L6723
10NH-3%-0.14A-2.1OHM
41 50_B34_DRX_WTR_IN1 2 50_B34_DRX_DSM 53
5%
01005 01005
01005 16V 50_B41A_DRX_WTR_MCH_MATCH
NP0-C0G-CERM
RADIO_WTR 01005 2
L6708
3.6NH+/-0.1NH-180MA
1 2
01005
NOSTUFF CELL
CELL
RADIO_WTR
RADIO_WTR
L6715 C6713
CELL 1.7NH+/-0.1NH-0.380A 100PF
CELL 1 2
RADIO_WTR 41 50_PCS_WTR_IN 1 2 50_PCS_FILT_OUT 50
RADIO_WTR 01005 50_PCS_WTR_RX_MCH
L6709 C6706 5% 16V01005
2.0NH+/-0.1NH-0.380A 100PF CELL CELL NP0-C0G
41 50_B39_DRX_WTR_IN 1 2 50_B39_DRX_WTR_MCH1 1 2 50_B39_DRX_DSM 53 RADIO_WTR RADIO_WTR
CELL 01005
CELL 5% 16V01005 C6709 L6716
RADIO_WTR RADIO_WTR NP0-C0G 47PF 2.7NH+/-0.1NH-0.370A
C6705 L6710 1 2 1 2
33PF 4.7NH-3%-0.270A 5% 50-PCS_DRX_WTR_MCH2

01005
1 2 1 2 16V
CERM
01005 01005
5% 50_B39_DRX_WTR_MCH2
16V CELL
NP0-C0G-CERM CELL
01005 RADIO_WTR
RADIO_WTR
L6718
A 1.6NH+/-0.1NH-0.390A C6714
100PF A
50_DCS_WTR_IN 1 2 1 2 50_DCS_FILT_OUT PAGE TITLE
CELL
41
01005
CELL
50_DCS_WTR_RX_MCH
5% 16V01005
NP0-C0G
50
CELL: RX DIV (1/2) DRAWING NUMBER SIZE

RADIO_WTR RADIO_WTR
L6717 Apple Inc. 051-0301 D
C6710
47PF 2.2NH+/-0.1NH-0.380A R
REVISION
1 2 1 2 B.0.0
5% 50_DCS_DRX_WTR_MCH2
01005
16V THE INFORMATION CONTAINED HEREIN IS THE
CERM PROPRIETARY PROPERTY OF APPLE INC.
01005 THE POSESSOR AGREES TO THE FOLLOWING: PAGE
67 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
C1900
RX DIVERSITY (2 OF 2)
R1900
L1900
U1901
D D
R6801
150OHM-25%-200MA-0.7DCR
73 PP_BATT_VCC_DSM 1 2 PP_BATT_VCC 35 44 68 73
01005
C RADIO_DSM
C6801 CELL C
47PF
5%
1 16V
CERM
01005
CELL
2
2
VDD
VIO 3 RFFE_VIO 40 45 46 47 48 49 50 51
52 50_B1_B4_DRX_DSM 32 RX_BAND_1_4 35 40 50 51
52 50_B3_DRX_DSM 33 RX_BAND_3
U6801 SDATA 4 RFFE2_DATA
16 B30684D5223X940
52 50_B7_DRX_DSM RX_BAND_7 SCLK 5 RFFE2_CLK 35 40 50 51
LGA
52 50_B8_B28B_DRX_DSM 19 RX_BAND_8+28B
CELL ANT_LB 7 50_LB_DIVERSITY 55
52 50_B13_B17_DRX_DSM 25 RX_BAND_13+17
34 RADIO_DSM 55
52 50_B25_DRX_DSM RX_BAND_25 ANT_HB 9 50_HB_DIVERSITY
52 50_B26_B28A_DRX_DSM21
50_B20_B29_DRX_DSM RX_BAND_26+28A
23 NC 29 NC
52 RX_BAND_29+20
CELL 50_B34_DRX_DSM 12 RX_BAND_34 NC 30
52
NC
FL6801 52 50_B39_DRX_DSM 13 RX_BAND_39
SAW-2-1-BAND-40-41A-DRX 50_B38X_DRX_DSM 17
B39252B9920P810 52 RX_BAND_38X
52 50_B40_DRX_FILTER 6 B40OUT B40IN 4 50_B40_DRX_DSM 14 RX_BAND_40
52 50_B41A_DRX_FILTER 9 B41AOUT
LGA B41AIN
1 50_B41A_DRX_DSM 15 RX_BAND_41A
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
THRM
PAD
10
8
7
5
3
2
1
6
8
10
11
18
20
22
24
26
27
28
31
35
36
37
38
39
40
B 1 1 1 1
B
L6801 L6802 L6803 L6804
5.6NH-3%-0.23A-1.3OHM 5.6NH-3%-0.23A-1.3OHM 2.7NH+/-0.1NH-0.370A 5.1NH-3%-0.250A
01005 01005 01005 01005
CELL CELL CELL CELL
RADIO_DSM RADIO_DSM RADIO_DSM RADIO_DSM
2 2 2 2
A A
PAGE TITLE
CELL: RX DIV (2/2) DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
68 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
GPS
D D
C C
CELL
L6904
5.6NH-3%-0.23A-1.3OHM
100_GPS_FILT_OUT_N 1 2 100_GPS_WTR_IN_N 41
01005
CELL
FL6901
LNA-GNSS-BAL 2
CELL
B8821
C6901 LGA L6903
56PF BAL_PORT 3 6.2NH-3%-0.22A-1.3OHM
55 50_GPS_LNA_OUT 1 2 50_GPS_FILT_IN 1 UNBAL_PORT BAL_PORT 4 01005
2 GND
5 GND
5% CELL
25V
1 NP0-C0G-CERM 1 CELL
01005
L6902
L6901 5.6NH-3%-0.23A-1.3OHM
4.7NH-3%-160MA 100_GPS_FILT_OUT_P 1 2 100_GPS_WTR_IN_P 41
01005
NOSTUFF 01005
B B
A A
PAGE TITLE
CELL: GPS
DRAWING NUMBER SIZE

REVISION
R
BRANCH
B.0.0
SHEET
54 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
ANTENNA FEEDS AND GPS (J82)

D D
PRI_ANT COAX CRITICAL
CELL
J7001
MM5829-2700
F-ST-SM
50_ANT_CONN
1 50
2
3
4
50_WIFI_G1 56
C R7003
150OHM-25%-200MA-0.7DCR
C
73 PP_LDO13_GPS 1 2 PP_LDO13 IN 36 38 69 73
CELL 01005
CELL OLD: LDO6
1 C7005 NEW: LDO13
33PF
2 01005 NP0-
C0G-CERM 16V
5%
CELL CELL
FL7002 J7004 BYPASS INTEGRATED INTO MODULE
885060 MM8830-2600B
8
CELL
DIPLEXER-CELL-WIFI
F-RT-SM
R7001 LGA CELL CELL VDD
CELL
50_GPS_HB_WIFI_G0 1
0 2 50_GPS_DRX_WIFI_G0_NOTCHPLEXER 9 RF1 RF3 1 R7002 R7004 U7001
6.8PF 1.8NH+/-0.1NH-0.8A LNA-CELL-GPS
5% GPS_OUT 10 50_GPS_LNA_OUT
1/20W
MF
L7003 7 SMD2_RF1/SMD4_GND RF2 4 50_GPS_DRX_NOTCHPLEXER 1 2 50_NOTCHPLEXER_MATCH 2
R C
1 50_GPS_DRX_SW_CONN 1 0201
2 50_GPS_EXTRACT_ANT 5 ANT TBD OUT 54
201 3.2NH+/-0.1NH-0.5A 6 LGA CELL_OUT 1

50_NOTCHPLEXER_SMD1 +/-0.1PF
13 EPAD
GND SMD1_RF2
GND
GND
GND
GND
GND
GND
GND
GND
1 2 50_NOTCHPLEXER_SMD2 25V CELL
1 C7001 0201
C0G
0201 GND
0.2PF CELL R7005
10
8
5
3
2
+/-0.1PF
3
0
2
3
4
6
7
9
11
12
2 25V
COG-CERM
1
1
50_EXTRACT_DRX 1 2 50_HB_DIVERSITY 53
201 CELL NOSTUFF 5%
NOSTUFF 1 1/20W
C7002 1 CELL 1 L7004 L7005 MF
201
7.5NH+/-0.3%-0.4A
0201 5.6NH+/-3%-0.4A
C7004 0.3PF 5.6NH-3%-0.35A
NOSTUFF L7002 0201 +/-0.1PF
2 25V C0G-
0201 1 C7006
3.6NH+/-0.1NH-0.5A CERM 0.2PF
0201 201 +/-0.1PF
2
2 25V
B CELL
2
2 COG-CERM
201 B
2 NOSTUFF
CELL
DPX162690DT-8049C1SJ
GPS_DRX_ANT
CELL
FL7003
SM
CRITICAL 6 LOW_BAND
50_LB_DIVERSITY
J7410 53
MM4829-2702
F-ST-SM 4 HIGH_BAND
1 50_GPS_DRX_WIFI_G0_ANT_COAX 2 COMMON
GND
J82 HW_ID (MAPPING PG 52)
2
3
4
EVT
1
3
5
RADIO_PMIC
73 38 37 36 IN
PP_LDO3
RADIO_PMIC
1
R7010
HW_REV_ID R7010 R7011 J82 REV J97 REV J99 REV 1%
102K
1/32W
0.10V 887K 51.1K N/A PROTO0 PROTO0 MF

2 01005
CELL
A 0.20V 422K 51.1K PROTO0 PROTO0B PROTO1 HW_REV_ID 37

SYNC_DATE=09/29/2014 A
0.30V 255K 51.1K PROTO1 PROTO1 PROTO2 1
RADIO_PMIC
R7011
PART NUMBER ALTERNATE FOR
PART NUMBER
TABLE_ALT_HEAD PAGE TITLE
CELL: ANT FEEDS & GPS (J82)

0.40V 178K 51.1K PROTO2 1%
51.1K
1/32W
197S0565 197S0598 Y5201 KDS XTAL, 19.2MHZ
TABLE_ALT_ITEM
Apple Inc.
DRAWING NUMBER
051-0301
REVISION
SIZE
D
0.50V 255K 100K PRE-EVT MF TABLE_ALT_ITEM
2 01005 197S0593 197S0598 Y5201 NDK XTAL, 19.2MHZ

R
CELL BRANCH B.0.0
0.60V 102K 51.1K EVT NOTICE OF PROPRIETARY PROPERTY:
0.70V 82.5K 51.1K DVT THE POSESSOR AGREES TO THE FOLLOWING:
PAGE 70 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
WIFI/BT (2 OF 5)
WIFI/BT FRONT END FOR J82
D D
R7412
1.0NH+/-0.1NH-0.580A
RF_G_0_LOWER_DIPLEXER 1 2 RF_G_0_LOWER
01005
CRITICAL
1
1 L7413 L7415
0.5PF 8.2NH-5NH%-140MA
+/-0.05PF 01005
16V
2 C0G-CERM NOSTUFF
01005
CRITICAL 2
CRITICAL PP_3V3_S2R_WIFI_PA 57 68
U7412
DPX205950DT-9057B1SJ CRITICAL
0603 C7424 1 C7428
0.9NH+/-0.1NH-0.75A 5%
RF_A_1_MATCH_MOD
10PF
4 HI COM 2 RF_A_1_DIPLEXER 1 2 57
0201
2 01005
1
6
C LO
GND 1
CRITICAL
C7425
CRITICAL
1
NOSTUFF
C7423 VDD
CERM
16V C
0.2PF
0.2PF
25V
+/-0.05PF
U7413
CXA4011GC
1
3
5
+/-0.05PF 2 COG-CERM
2 25V 56 RF_G_0_BAW_MATCH 7 RF XFLGA RF1 5
COG-CERM 0201
0201
NOSTUFF WIFI_G0_ANT_SEL
57 2 VC1 RF2 4
LOWER ANTENNA CONNECTOR GND

CRITICAL
3
6
8
CRITICAL
J7420 1
MM4829-2702 CRITICAL C7429
F-ST-SM R7420 CRITICAL 100K
0.00 2 5%
1 RF_1_ANT 1 RF_1_ANT_MATCH_T FL7401 1/32W
WLAN-BT-LTE MF
1% NOSTUFF 2 01005
1 C7426 885079
1 C7427 1/20W LGA
2
3
4
MF CRITICAL
0.3PF 0201 0.2PF C7431
+/-0.05PF 25V 0.00 2 C7411
25V 2 +/-0.1PF
COG-CERM RF_G_0_BAW_MATCH 1 RF_G_0_BAW_OUT
4 OUT/ANT 1
2 C0G-CERM 56 IN
0201 201
0% GND RF_G_0_MATCH_MOD
CRITICAL 1/32W RF_G_0_BAW_MOD 1 2 57
MF
01005 1 2.5NH+/-0.1NH-0.6A CRITICAL
5
3
2
1
CRITICAL
1 C7410
+/-0.05PF
C7430 0201
0.5PF
25V
4.7NH-3%-0.270A L7410 2 0201
01005 8.2NH+/-3%-0.25A-0.7OHM COG-CERM
0201
NEW PART WITH UPDATED PIN OUT WILL GO INTO BUILD
CRITICAL
2
NOSTUFF
2
CRITICAL
R7411
2.4NH+/-0.1NH-0.370A
U7410
B DPX205950DT-9057B1SJ
0603
RF_G_0_UPPER_DIPLEXER 1
01005
2 RF_G_0_UPPER
B
CRITICAL 1
4 HI COM 2 1 L7432 L7411
6 LO 1PF
+/-0.1PF 8.2NH-5NH%-140MA
16V 01005
GND 2 NP0-C0G
01005 NOSTUFF
1
3
5
2
CRITICAL
CRITICAL
L7414
RF_A_0_DIPLEXER 1
0.00 2 RF_A_0_MATCH_MOD 57
UPPER ANTENNA CONNECTOR 1%

1/20W CRITICAL
NOSTUFF MF
CRITICAL 1 C7415 0201 1 C7413
J7002 0.2PF
+/-0.1PF 0.2PF
+/-0.05PF
MM4829-2702 R7410 25V 25V COG-
2 CERM 0201
F-ST-SM 1.1NH+/-0.1NH 2 201
COG-CERM
1 RF_0_ANT RF_0_ANT_MATCH_T
NOSTUFF
1 2
0201
NOSTUFF
1 C7417 1 C7416
2
3
4
0.2PF
+/-0.1PF 0.4PF
25V +/-0.05PF
2 201
COG-CERM 25V
2 C0G
201
CONNECTION TO WIFI-CELL DIPLEXER
CRITICAL
C7421
A 55 50_WIFI_G1 1
0.00 2
RF_G_1_MATCH_MOD 57 A
1% PAGE TITLE
1 1/20W CRITICAL
MF
0201 1 C7420 WIFI/BT: J82 ANT INTERFACE
1.0PF DRAWING NUMBER SIZE
L7412 +/-0.05PF
25V 051-0301 D
6.2NH-3%-0.4A 2 C0G-CERM Apple Inc. REVISION
0201 0201
R
CRITICAL NOSTUFF BRANCH B.0.0
2 NOTICE OF PROPRIETARY PROPERTY:
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
WIFI/BT (3 OF 5) PP_VCC_MAIN_WLAN 68
1 C7583 1 C7584
TABLE_5_HEAD 4.7UF 4.7UF
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 20% 20%
6.3V 6.3V
TABLE_5_ITEM
2 X5R-CERM1 2 X5R-CERM1
402 402
339S0251 1 MODULE, WIFI/BT, STELLA CIDRE U7500 CRITICAL MLB_A
D 339S0241 1 MODULE, WIFI/BT, STELLA U7500 CRITICAL MLB_B

TABLE_5_ITEM
R7513
D
0.00 2
TABLE_ALT_HEAD
73 68 57 PP_1V8_S2R_VDDIO_WLAN_BT 1 73 PP_WL_VDDIO PP_3V3_S2R_WIFI_PA 56 68

PART NUMBER 0%
1/32W
TABLE_ALT_ITEM
MF
01005
1 C7501 1 C7500 1 C7580 1 C7581 1 C7582
339S0250 339S0251 MLB_A U7500 STELLA CIDRE ALT 27PF 0.01UF 4.7UF
5% 10% 20% 10UF 10UF
TABLE_ALT_ITEM
20% 20%
339S0229 339S0241 MLB_B U7500 STELLA ALT 2 16V
NP0-C0G 2 6.3V
X5R 2 6.3V
X5R-CERM1 6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
01005 01005 402 0402-2 0402-2
11
58
25
35
VDDIO_1P8
BATT_VCC
BATT_RF_VCC
BATT_RF_VCC
BT_GPIO4 10 NC
70 69 68 62 IN CLK_PMU2WLAN_32K 68 CLK32K_AP
70 68 6 UART_SOC2WLAN_TX 48 FAST_UART_RX
IN
68 OUT UART_WLAN2SOC_RX 54 FAST_UART_TX
70 57 WLAN_GPIO_8 53 WL_GPIO_8
BT_WAKE 16 GPIO_SOC2BT_WAKE IN 9 68 70
68 OUT UART_WLAN2SOC_CTS_L 46 FAST_RTS_OUT
NOTE* PIN5 SHOULD BE NC FOR J81/J96/J97/J98/J99 BT_USB_DP 3 NC
70 69 68 62 57 IN GPIO_PMU2WLAN_REG_ON 60 WLAN_REG_ON U7500 BT_USB_DN 4 NC
LBEE5UAZLC-670
70 69 68 62 IN GPIO_PMU2BT_REG_ON 56 BT_REG_ON LGA BT_UART_RXD 13 UART_SOC2BT_TX IN 6 68 70
339S0229
SYM 1 OF 2 BT_UART_TXD 12 UART_BT2SOC_RX 68
OUT
70 JTAG_WLAN_SEL 45 JTAG_SEL CRITICAL BT_UART_CTS* 9 UART_SOC2BT_RTS_L 6 68 70
IN
1 MODULE_INST BT_UART_RTS* 8 UART_BT2SOC_CTS_L 68
R7500 OUT
2 ANT_SWITCH_CORE1
C 5%
10K
1/32W 56 WIFI_G0_ANT_SEL
NC
5 ANT_SWITCH_CORE0
OMIT_TABLE
BT_PCM_CLK 6 I2S_SOC2BT_BCLK IN 6 68 70
C
MF 70 57 WLAN_GPIO_10 BT_PCM_SYNC 18 I2S_SOC2BT_LRCK 6 68 70
IN
114 2 01005 68 IN GPIO_SOC2WLAN_PCIE_DEV_WAKE 66 14 I2S_BT2SOC_DIN
THRM_PAD NC HSIC_WLAN_DATA BT_PCM_OUT OUT 68
THRM_PAD 115 65 HSIC_WLAN_STROBE BT_PCM_IN 7 I2S_SOC2BT_DOUT

15 116
R7592 NC IN 6 68 70
47
19
GND U7500 THRM_PAD
117 70 68 6 IN UART_SOC2WLAN_RTS_L 1
0.00
2 UART_SOC2WLAN_RTS_L_RES
61
HSIC_DEV_RDY
GND LBEE5UAZLC-670 THRM_PAD HSIC_HOST_READY_PCIE_DEV_WAKE
0%
23 118 62 WL_GPIO_9 52
24
GND LGA THRM_PAD
119
1/32W
MF
HSIC_RESUME_FAST_CTS_IN_JTAG_TCK WLAN_GPIO_9 57
OSCAR_CONTEXT_A
GND SYM 2 OF 2 THRM_PAD 01005
26 OMIT_TABLE 120
GND THRM_PAD
27 GND THRM_PAD 121 68 JTAG_WLAN_TMS 63 JTAG_TMS WL_GPIO_13 51 OSCAR2RADIO_CONTEXT_B 68 70
IN IN
29 GND THRM_PAD 122 68 57 JTAG_WLAN_TRST 44 JTAG_TRST
IN
30 GND THRM_PAD 123 70 WLAN_SECI_IN 43 SEC_IN/JTAG_TDI WL_HOST_WAKE 55 GPIO_WLAN2PMU_HOST_WAKE OUT 62 68 70
32 GND THRM_PAD 124 71 70 40 UART_WLAN2BB_COEX_TX 42 SEC_OUT/JTAG_TDO
OUT
33 GND THRM_PAD 125 WLAN_PCIE_PME 79 PCIE_WLAN2PMU_WAKE_L OUT 62 68
34 GND THRM_PAD 126 WLAN_PCIE_CLKREQ 80 PCIE_WLAN2SOC_CLKREQ 68
BI
36 GND THRM_PAD 127 70 68 62
GPIO_BT2PMU_HOST_WAKE 17 HOST_WAKE_BT WLAN_PERST 1 PCIE_SOC2WLAN_PERST 68
OUT IN
37 GND THRM_PAD 128
38 GND THRM_PAD 129 C7589
40 130 22 2G_CORE0_ANT 77 0.1UF
GND THRM_PAD 56 RF_G_0_MATCH_MOD WLAN_PCIE_RDP0 PCIE_SOC2WLAN_TX_P IN 9 68 70
1 2
57 131
PCIE_WLAN2SOC_RX_P OUT 68
GND THRM_PAD 56 RF_G_1_MATCH_MOD 31 2G_CORE1_ANT WLAN_PCIE_RDN0 76 PCIE_SOC2WLAN_TX_N IN 9 68 70
59 GND THRM_PAD 132 WLAN_PCIE_TDP0
68 73 PCIE_TX_P 20%
6.3V
64 GND THRM_PAD 133 56 RF_A_0_MATCH_MOD 28 5G_CORE0_ANT WLAN_PCIE_TDN0
68 74 PCIE_TX_N X5R-CERM
01005
67 GND THRM_PAD 134 56 RF_A_1_MATCH_MOD 39 5G_CORE1_ANT WLAN_PCIE_REFCLKP 71 PCIE_SOC2WLAN_CLK_P 9 68 70
IN
69 GND THRM_PAD 135 WLAN_PCIE_REFCLKN 70 PCIE_SOC2WLAN_CLK_N 9 68 70
IN
72 GND THRM_PAD 136 68 IN BT_EXT_SYNC 20 BT_GPIO3 WL_UART_RX
68 50 WL_UART_RX C7590
75 137 21 BT_GPIO5 49 0.1UF
GND THRM_PAD 68 BT_EXT_CLK WL_UART_TX
B 78 GND THRM_PAD 138
139
IN
NC
41 NC
PP7590
P4MM SM PP
1
1
20%
2 PCIE_WLAN2SOC_RX_N OUT 68
B
81 THRM_PAD 6.3V
THRM_PAD 140 X5R-CERM
82 THRM_PAD 01005
THRM_PAD 141
83 THRM_PAD
THRM_PAD 142
84 THRM_PAD
THRM_PAD 143
85 THRM_PAD
THRM_PAD PP7591 68 1 WL_UART_TX
86 THRM_PAD
THRM_PAD 144
R7589 P4MM SM PP C7592
THRM_PAD 145 0.00 2 0.01UF
87 THRM_PAD UART_BB2WLAN_COEX_RX 1 JTAG_WLAN_TRST
146 71 70 40 IN 57 68 PP_1V8_S2R_VDDIO_WLAN_BT 1 2
88 THRM_PAD
THRM_PAD
147
0%
1/32W
BOOTSTRAP CONFIGURATION 73 68 57
89 THRM_PAD 10%
THRM_PAD MF 6.3V
THRM_PAD 148 01005 X5R
90 THRM_PAD 01005
THRM_PAD 149
91 THRM_PAD 150 73 68 57 PP_1V8_S2R_VDDIO_WLAN_BT U7503
92 THRM_PAD A2 74AUC1G126
THRM_PAD 151 BGA-YZP
93 THRM_PAD B1 C2
THRM_PAD 152 1 1 70 68 IN OSCAR2RADIO_CONTEXT_A A 126 OE Y
WLAN_GPIO_9 57
94 THRM_PAD
THRM_PAD
153
R7586 R7587 A1
95 THRM_PAD 10K 10K
THRM_PAD 154 5% 5%
96 THRM_PAD 1/32W 1/32W C1
THRM_PAD 155 MF MF
97 THRM_PAD
THRM_PAD
156
2 01005 2 01005 R7590
98 THRM_PAD
1
10K 2
THRM_PAD 157 70 69 68 62 57 WLAN_REG_RC
99 THRM_PAD
THRM_PAD 158 GPIO_PMU2WLAN_REG_ON 5%
THRM_PAD WLAN_GPIO_10 1/32W
100 THRM_PAD
THRM_PAD 159 GPIO 10 70 57 MF
01005
1 C7588
101 THRM_PAD WLAN_GPIO_9 4.7UF
102 THRM_PAD 160 GPIO 09 57
20%
6.3V
THRM_PAD 161 WLAN_GPIO_8 2 X5R-CERM1
103 THRM_PAD
THRM_PAD GPIO 08 70 57
402
THRM_PAD 162
104 THRM_PAD 163 LAST UPDATED: 11/6/2013
A 105
106
THRM_PAD
THRM_PAD
THRM_PAD
THRM_PAD 164 SYNC_MASTER=WIFI SYNC_DATE=09/29/2014 A
165 1 PAGE TITLE
107 THRM_PAD R7585
108
THRM_PAD
THRM_PAD
THRM_PAD 166
167 GPIO [10:8] = 011 FOR PCIE 5%
10K WIFI/BT: WIFI/BT MODULE
109 THRM_PAD 1/32W DRAWING NUMBER SIZE
THRM_PAD MF
110 THRM_PAD
THRM_PAD 168
2 01005 Apple Inc. 051-0301 D
THRM_PAD 169 REVISION
111 THRM_PAD R
112 THRM_PAD
THRM_PAD 170 B.0.0
113 NOTICE OF PROPRIETARY PROPERTY: BRANCH
THRM_PAD
75 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
L7800
120-OHM-25%-250MA-0.5DCR
VOLTAGE=3.0V
72 =PP3V0_S2R_PROX
2 1 69 PP3V0_SENSOR_PROX_FILT
01005
C7806 1
C7800 1 C7801 1
68PF
2.2UF 0.1UF 5%
10% 20% 6.3V
6.3V 6.3V NP0-C0G 2
402 2 01005 2
X5R-CERM 01005
X5R
R7801
240 VOLTAGE=1.8V
72 58 =PP1V8_S2R_PROX 1 2 PP1V8_PROX_FILT
C R7800 1
1%
1/32W
MF C7804 1 C7805 1
C
2.2K 01005 0.1UF 68PF APN: 353S00018
5% 20% 5% I2C ADDRESS: 0B0101000X
C1
C2
1/32W 6.3V 6.3V
MF X5R-CERM 2 NP0-C0G 2
01005 2 01005 01005
SVDD VDD CRITICAL APN: 516S0872
J7800 FLEX: 516S0865
U7800 503548-0620
SX9305AICS CRITICAL CRITICAL F-ST-SM
WLCSP
FL7801 L7811 8 7
70 58 17 BI I2C_OSCAR2PROX_SDA_1V8 A1 SDA CRITICAL CS0 C4 NC FERR-1800-OHM-0.2A 120NH-2%-310MA
70 58 17 I2C_OSCAR2PROX_SCL_1V8 B1 SCL
IN 1 2 1 2
CS2 B4 NC_PROX_CS2 NO_TEST=TRUE
58 PROX_ACSHIELD 0402 PROX_ACSHIELD_F 0402 PROX_ACSHIELD_CONN 2 1
NC
NO_TEST=TRUE 4 3
17 OUT GPIO_PROX2OSCAR_IRQ_L A2 IRQ* CS3 A4 58
NC NC
PROX_CS3 CRITICAL 6 5
CRITICAL NC
FL7800 L7810
120NH-2%-310MA
10 9
CSG C3 PROX_ACSHIELD NO_TEST=TRUE FERR-1800-OHM-0.2A
58
0402
GND 58 PROX_CS3 1
0402
2 PROX_CS3_F 1 2 PROX_CS3_CONN
CS3 - SENSOR ELECTRODE
B3
A3
B2
PCB: ENSURE ACSHIELD PLANE UNDER U7800
NO GND PLANE NEAR PROX_CS NETS.
PCB: ACSHIELD NEEDS TO BE A PLANE UNDER

PROX_CS NETS AND ALSO TIE TO CONNECTOR.
B B
72 58 =PP1V8_S2R_PROX
R78901 R78911
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF
01005 2 01005 2
A 70 58 17 I2C_OSCAR2PROX_SDA_1V8 SYNC_MASTER=N/A SYNC_DATE=N/A A

BI PAGE TITLE
I2C_OSCAR2PROX_SCL_1V8
70 58 17 IN
SENSOR: HAMMERHEAD
DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1
TABLE_5_HEAD

TABLE_5_ITEM
155S00018 1 FERRITE,80OHM,25%,500MA,0.18DCR L7900 CRITICAL
SIM CARD AND ANTENNA SWITCH FILTERS
D D
OMIT_TABLE
L7900
VOLTAGE=2.85V
80-OHM-25%-500MA
69 PP_LDO5_FILT 1 2 PP_LDO5 36 38 73
0201
1
NC R7900 1 C7901 1 C7902 1 C7903 1 DZ7900
15.00K 1.0UF 4.7UF 4.7UF 12V-33PF
1% 20% 20% 20% 01005-1
1/32W 6.3V 6.3V 6.3V
5
MF 2 X5R 2 X5R 2 X5R 2
VCC VPP 2 01005
0201-1 402 402
CRITICAL
J7900
SIM-CARD-X193
F-RT-SM
71 69 59 SIMCRD_RST_CONN_FILT 2 RESET I/O 6 SIMCRD_IO_CONN_FILT 59 69 71
DETGND
71 69 59 SIMCRD_CLK_CONN_FILT 3 CLK DETECT 7 SIMCRD_DETECT_FILT 59 69 71
GND
GND
GND
GND
GND
1 C7905
9
10
11
12
4
8
100PF
5%
6.3V
2 CERM
01005
C C
ANTENNA SWITCH FILTERS

FL7960
0.00 2
68 IN GPIO_BB2ANT_SW0 1 GPIO_BB2ANT_SW0_FILT 23
0%
1/32W
MF
FL7920 01005
1
150OHM-25%-200MA-0.7DCR C7960
27PF
68 SIMCRD_RST 1 2 SIMCRD_RST_CONN_FILT 59 69 71
5%
2 16V
IN
01005 NP0-C0G
01005
FL7921
150OHM-25%-200MA-0.7DCR FL7961
SIMCRD_CLK 1 2 SIMCRD_CLK_CONN_FILT 20K
68 IN 59 69 71
68 GPIO_BB2ANT_SW1 1 2 GPIO_BB2ANT_SW1_FILT 23
B 01005
IN
1%
1/32W
B
MF
FL7922 01005
1
150OHM-25%-200MA-0.7DCR C7961
27PF
68 SIMCRD_IO 1 2 SIMCRD_IO_CONN_FILT 59 69 71
5%
BI
01005 2 16V
NP0-C0G
01005
FL7923 FL7962
150OHM-25%-200MA-0.7DCR 70-OHM-300MA
VOLTAGE=3.0V
68 SIMCRD_DETECT 1 2 SIMCRD_DETECT_FILT 59 69 71 72 =PP3V0_S2R_ANT_SW 1 2 PP3V0_S2R_ANT_SW_FILT 23
OUT
01005 CRITICAL 01005-1
U7900
ESDAVLC5-4BX4-TPD4E101DPWR 1 C7962
LGA-COMBO 27PF
1 4 5%
2 16V
NP0-C0G
01005
5 GND
2 3
PAGE TITLE
CELL: SIM AND ANT SW FILT

DRAWING NUMBER SIZE

REVISION
R
B.0.0
79 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
L8100 CRITICAL
0.82UH-20%-4.5A-0.034OHM ADDITIONAL DISTRIBUTED
91UF (NO DERATING)
BUCK0_LX0 VOLTAGE=4.7V 1 2 PPVDD_CPU 69 72
MIN_LINE_WIDTH=0.60MM DIDT=TRUE
PILE32251D-SM CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
NET_SPACING_TYPE=PWR L8101
1 C8100 1 C8101 1 C8102 1 C8103 1 C8104
MAX_NECK_LENGTH=0.5 MM
CRITICAL 15UF 15UF 15UF 15UF 15UF
SWITCH_NODE=TRUE 0.82UH-20%-4.5A-0.034OHM 20% 20% 20% 20% 20%
4V 4V 4V 4V 4V
2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
BUCK0_LX1 VOLTAGE=4.7V 1 2
0402 0402 0402 0402 0402
MIN_NECK_WIDTH=0.20MM PILE32251D-SM
NET_SPACING_TYPE=PWR
L8102 CRITICAL
SWITCH_NODE=TRUE 0.82UH-20%-4.5A-0.034OHM CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
1 C8105 1 C8106 1 C8107 1 C8108 1 C8109
15UF 15UF 15UF 15UF 15UF
MIN_NECK_WIDTH=0.20MM PILE32251D-SM 20% 20% 20% 20% 20%
2 4V 2 4V 2 4V 2 4V 2 4V
D
SWITCH_NODE=TRUE
L8103
0.82UH-20%-4.5A-0.034OHM
CRITICAL CERM
0402
CERM
0402
CERM
0402
CERM
0402
CERM
0402 D
MIN_NECK_WIDTH=0.20MM PILE32251D-SM CRITICAL CRITICAL
1 C8110 1 C8111 1 C81F0
SWITCH_NODE=TRUE 15UF 15UF 100PF
XW8101 20% 20% 5%
BUCK0_FB VOLTAGE=1.1V 1 2 4V 4V 16V
2 CERM 2 CERM 2 NP0-C0G
SM 0402 0402 01005
U8100 MIN_NECK_WIDTH=0.20MM
D2207A0 L8104 CRITICAL

BGA 1.0UH-3.51A-0.036OHM ADDITIONAL DISTRIBUTED
OMIT_TABLE 65UF (NO DERATING)
SYM 1 OF 4 BUCK1_LX0 VOLTAGE=4.7V 1 2 PPVDD_GPU 69 72
65 PMU_CHG_LX0 G19 CHG_LX0 J1 MIN_LINE_WIDTH=0.60MM DIDT=TRUE
PILE25201D CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
REPURPOSED CAPS TO BE PLACED NEAR BB VBATT 65 PMU_CHG_LX1 H19 CHG_LX1 BUCK0_LX0 J2 NET_SPACING_TYPE=PWR L8105 CRITICAL 1 C8112 1 C8113 1 C8114 1 C8115 1 C8116 1 C811F
J19 L1
MAX_NECK_LENGTH=0.5 MM 1.0UH-3.51A-0.036OHM 15UF 15UF 15UF 15UF 15UF 15UF
72 69 65 60 PPBATT_VCC 65 PMU_CHG_LX2 CHG_LX2 SWITCH_NODE=TRUE
20% 20% 20% 20% 20% 20%
BUCK1_LX1 VOLTAGE=4.7V 1 2 4V 4V 4V 4V 4V 4V
CRITICAL CRITICAL CRITICAL 65 PMU_CHG_LX3 K19 CHG_LX3 BUCK0_LX1 L2 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM 2 CERM
1 C81FF 1 C8175 1 C8176 1 C8159 N1
MIN_NECK_WIDTH=0.20MM PILE25201D 0402 0402 0402 0402 0402 0402
18PF 22UF 22UF 22UF 65 PMU_VBAT P16 VBAT NET_SPACING_TYPE=PWR L8106 CRITICAL
5% 20% 20% 20% BUCK0_LX2 N2 MAX_NECK_LENGTH=0.5 MM
2 25V 2 6.3V 6.3V 6.3V PMU_IBAT_S P17 IBAT_S SWITCH_NODE=TRUE 1.0UH-3.51A-0.036OHM
C0G-CERM X5R-CERM-1 2 X5R-CERM-1 2 X5R-CERM-1 65
R1
0201 603 603 603 CRITICAL CRITICAL CRITICAL CRITICAL
BUCK0_LX3 BUCK1_LX2 VOLTAGE=4.7V 1 2 1 C8117 1 C8118 1 C8119 1 C8120 1 C81F1
65 PMU_IBAT0 M19 IBAT0 R2 MIN_LINE_WIDTH=0.60MM DIDT=TRUE
PILE25201D
N19 MIN_NECK_WIDTH=0.20MM 15UF 15UF 15UF 15UF 100PF
65 PMU_IBAT1 IBAT1 BUCK0_FB M4 NET_SPACING_TYPE=PWR 20% 20% 20% 20% 5%
65 PMU_IBAT2 P19 IBAT2
SWITCH_NODE=TRUE
2 4V
CERM 2 4V
CERM 2 4V
CERM 2 4V
CERM 2 16V
NP0-C0G
G1 XW8102 0402 0402 0402 0402 01005
65 PMU_IBAT3 R19 IBAT3 BUCK1_LX0 G2 BUCK1_FB VOLTAGE=1.1V 1 2
PLACE NEAR CODEC MIN_LINE_WIDTH=0.25MM
SM
PPBATT_VCC 65 PMU_ACT_DIO N17 ACT_DIO E1 MIN_NECK_WIDTH=0.20MM
ADDITIONAL DISTRIBUTED
72 69 65 60
BUCK1_LX1 E2 L8107 CRITICAL 31UF (NO DERATING)
PP0V95_SOC
PLACE_NEAR=U3000.G1:50MM PLACE_NEAR=U3000.G1:50MM
65 PMU_VCEN_01 F18 1.0UH-3.51A-0.036OHM 69 72
C81B0 1 1 C81B1 PMU_VCEN_02 F19
C1 CRITICAL CRITICAL CRITICAL CRITICAL
33PF
5% 5%
82PF 65
BUCK1_LX2 C2 BUCK2_LX0 VOLTAGE=4.7V 1 2 1 C8121 1 C8122 1 C8123 1 C812F
65 PMU_VCEN_03 G18 MIN_LINE_WIDTH=0.60MM DIDT=TRUE
PILE25201D 15UF 15UF 15UF 15UF
16V 25V
NP0-C0G-CERM 2 2 NP0-C0G BUCK1_FB F4 MIN_NECK_WIDTH=0.20MM
20% 20% 20% 20%
PMU_VCEN_04 H18 L8150 CRITICAL
USB/BAT
BUCK
2 4V 2 4V 2 4V 2 4V
C 01005 0201 65
65 PMU_VCEN_05 J18 VCENTER

BUCK2_LX0
Y5
SWITCH_NODE=TRUE 1.0UH-3.51A-0.036OHM CERM
0402
CERM
0402
CERM
0402
CERM
0402 C
65 PMU_VCEN_06 K18 W5 BUCK2_LX1 VOLTAGE=4.7V 1 2
65 PMU_VCEN_07 L18 Y7 MIN_NECK_WIDTH=0.20MM PILE25201D
L19 BUCK2_LX1 W7 NET_SPACING_TYPE=PWR CRITICAL CRITICAL CRITICAL
65 PMU_VCEN_08 MAX_NECK_LENGTH=0.5 MM 1 C81C0 1 C81C1 1 C81C2 1 C81B7
SWITCH_NODE=TRUE
F16 BUCK2_FB U7 XW8103 15UF 15UF 15UF 100PF
65 PMU_VBUS_01 BUCK2_FB VOLTAGE=0.95V 1 2 20% 20% 20% 5%
4V 4V 4V 16V
65 PMU_VBUS_02 F17 Y9 MIN_LINE_WIDTH=0.25MM
SM 2 CERM 2 CERM 2 CERM 2 NP0-C0G
0402 0402 0402 01005
65 PMU_VBUS_03 G16 BUCK3_LX0 W9 L8108 CRITICAL
G17 1.0UH-3.51A-0.036OHM ADDITIONAL DISTRIBUTED
65 PMU_VBUS_04 BUCK3_FB U8 40UF (NO DERATING)
65 PMU_VBUS_05 H16 BUCK3_LX0 VOLTAGE=4.7V 1 2 PP1V8_S2R 60 61 69 72
W1 MIN_LINE_WIDTH=0.60MM DIDT=TRUE
65 PMU_VBUS_06 H17 VBUS MIN_NECK_WIDTH=0.20MM
PILE25201D CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
BUCK4_LX0 W2 NET_SPACING_TYPE=PWR
1 C8124 1 C8125 1 C8126 1 C81B5 1 C81B6 1 C81F2
65 PMU_VBUS_07 J17 MAX_NECK_LENGTH=0.5 MM
U1 SWITCH_NODE=TRUE
15UF 15UF 15UF 15UF 15UF 100PF
65 PMU_VBUS_08 K16 XW8104 20% 20% 20% 20% 20% 5%
BUCK4_LX1 U2 2 4V 2 4V 2 4V 2 4V 2 4V 2 16V
65 PMU_VBUS_09 K17 BUCK3_FB VOLTAGE=1.8V 1 2 CERM CERM CERM CERM CERM NP0-C0G
0402 0402 0402 0402 0402 01005
BUCK4_FB U4 MIN_LINE_WIDTH=0.25MM
SM
65 PMU_VBUS_10 L16 MIN_NECK_WIDTH=0.20MM
PMU_VBUS_11 L17 A4 L8109CRITICAL

65 1.0UH-3.33A-66MOHM ADDITIONAL DISTRIBUTED
65 PMU_VBUS_12 J16 BUCK5_LX0 B4 94UF (NO DERATING)
A6
BUCK4_LX0 VOLTAGE=4.7V 1 2 PP1V2_S2R 60 61 69
72 =PPVCC_MAIN_CPU D14 MIN_LINE_WIDTH=0.60MM DIDT=TRUE
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
72
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL 65 PMU_OVP_OFF VBUS_OVP_OFF BUCK5_LX1 B6 MIN_NECK_WIDTH=0.20MM PILE20161D-SM
1 C8177 1 C8178 1 C8179 1 C8180 1 C8181 NET_SPACING_TYPE=PWR L8151CRITICAL 1 C8127 1 C8128 1 C8129 1 C81C3 1 C81C4 1 C81C5 1 C81F3
NC_PMU_HV_CHG NO_TEST=TRUE D17 HV_CHG_DIS BUCK5_FB D6
SWITCH_NODE=TRUE 1.0UH-3.33A-66MOHM 15UF 15UF 15UF 15UF 15UF 15UF 100PF
10UF 10UF 10UF 10UF 10UF 20% 20% 20% 20% 20% 20% 5%
20% 20% 20% 20% 20%
BUCK4_LX1 VOLTAGE=4.7V 1 2 2 4V 2 4V 2 4V 2 4V 2 4V 2 4V 2 16V
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R
(=PPVCC_MAIN_CPU) K1 A8
CERM
0402
CERM
0402
CERM
0402
CERM
0402
CERM
0402
CERM
0402
NP0-C0G
01005
0402-10 0402-10 0402-10 0402-10 0402-10 K2 VDD_BUCK0_01 BUCK6_LX0 B8 MIN_NECK_WIDTH=0.20MM PILE20161D-SM
P1 BUCK6_FB D8 MAX_NECK_LENGTH=0.5 MM
SWITCH_NODE=TRUE
P2 VDD_BUCK0_23 BUCK6_BYP0 A11 XW8105
72 =PPVCC_MAIN_GPU BUCK4_FB VOLTAGE=1.2V 1 2
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL BUCK6_BYP1 B11 MIN_LINE_WIDTH=0.25MM
1 C8182 1 C8183 1 C8184 1 C8185 1 C8186 (=PPVCC_MAIN_GPU) F1 MIN_NECK_WIDTH=0.20MM
SM
10UF 10UF 10UF 10UF 10UF F2 VDD_BUCK1_01 L8110CRITICAL

B 20%
6.3V
2 X5R
20%
6.3V
2 X5R
20%
6.3V
2 X5R
20%
6.3V
2 X5R
20%
6.3V
2 X5R B1
1.0UH-3.33A-66MOHM ADDITIONAL DISTRIBUTED
26UF (NO DERATING) B
0402-10 0402-10 0402-10 0402-10 0402-10 B2 VDD_BUCK1_2 BUCK5_LX0 VOLTAGE=4.7V 1 2 PPVDD_SRAM 69 72
W11 MIN_NECK_WIDTH=0.20MM PILE20161D-SM CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
NET_SPACING_TYPE=PWR L8152CRITICAL 1 C8130 1 C8131 1 C8132 1 C81G0 1 C81G1 1 C81B2 1 C1450 1 C81F4
W12 MAX_NECK_LENGTH=0.5 MM
15UF 15UF 15UF 15UF 15UF 15UF 15UF 100PF
72 =PPVCC_MAIN_SOC (=PPVCC_MAIN_SOC) W6 VBUCK3 SWITCH_NODE=TRUE 1.0UH-3.33A-66MOHM 20% 20% 20% 20% 20% 20% 20% 5%
V11
2 4V
(PP1V8_S2R)
CRITICAL CRITICAL Y6 VDD_BUCK2 BUCK5_LX1 VOLTAGE=4.7V 1 2 2 4V
CERM 2 4V
CERM 2 4V
CERM 2 4V
CERM 2 4V
CERM 2 4V
CERM CERM 2 16V
NP0-C0G
1 C8187 1 C8188 V12 MIN_LINE_WIDTH=0.60MM DIDT=TRUE 0402 0402 0402 0402 0402 0402 0402 01005
PILE20161D-SM
10UF 10UF MIN_NECK_WIDTH=0.20MM
SWITCHED POWER
W10 V13
VCC-MAIN
20% 20% MAX_NECK_LENGTH=0.5 MM
6.3V 6.3V Y10 VDD_BUCK3 BUCK3_SW1 W13
2 X5R 2 X5R SWITCH_NODE=TRUE
0402-10 0402-10 Y13 (PP1V8_SW1)
XW8106 ADDITIONAL DISTRIBUTED
V1 BUCK5_FB VOLTAGE=3.3V 1 2 25UF (NO DERATING)
V2 VDD_BUCK4 BUCK3_SW2 Y12 (PP1V8_SW2) MIN_LINE_WIDTH=0.25MM
SM PP3V3_S2R 69 72
BUCK3_SW3 Y11 (PP1V8_S2R_SW3) L8111 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
72 69 65 64 61 PPVCC_MAIN (PPVCC_MAIN)
A5 2.2UH-2.35A-0.073OHM 1 C81A0 1 C81A1 1 C81A2 1 C81A4 1 C81A5 1 C81A6 1 C81F5
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL W14 20UF 20UF 20UF 20UF 20UF 20UF 100PF
1CRITICAL B5 VDD_BUCK5 BUCK6_LX0 VOLTAGE=4.7V 1 2 20% 20% 20% 20% 20% 20% 5%
1
C8190 1
C8140 C8141 1 C8170 1 C8171 1 C8172 1 C8144 1 C8142 1 C8143 W15 MIN_LINE_WIDTH=0.60MM DIDT=TRUE
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
6.3V
2 CERM-X5R
16V
2 NP0-C0G
100UF 100UF 100UF 10UF 10UF 10UF 1.0UF 82PF 18PF VBUCK4 MIN_NECK_WIDTH=0.20MM
PILE25201D
20% 20% 20% 20% 5% 5% A9 V14 (PP1V2_S2R)
0402 0402 0402 0402 0402 0402 01005
20% 20% 20%
6.3V 6.3V 6.3V 6.3V 25V 25V MAX_NECK_LENGTH=0.5 MM
2 6.3V 2 6.3V 2 6.3V 2 X5R 2 X5R 2 X5R 2 X5R 2 NP0-C0G 2 C0G-CERM B9 VDD_BUCK6 V15 SWITCH_NODE=TRUE
TANT-POLY TANT-POLY TANT-POLY
B1G-1 B1G-1 B1G-1 0402-10 0402-10 0402-10 0201-1 0201 0201
V16 XW8107
A10 BUCK6_FB VOLTAGE=3.3V 1 2
BUCK4_SW1 W16 MIN_LINE_WIDTH=0.25MM
SM
B10 VDD_BYP6 MIN_NECK_WIDTH=0.20MM
Y16 (PP1V2_SW1)
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL R17 VCC_MAIN_S BUCK4_SW2 Y15 (PP1V2_S2R_SW2)
1 C8150 1 C8151 1 C8152 1 C8153 1 C8154 1 C8155 1 C8156 1 C8157 1 C8158 PP1V8_S2R 60 61 69 72
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF M18 VPUMP Y14
20% 20% 20% 20% 20% 20% 20% 20% 20% N18
PP1V8_SW1 67 69 72
6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V 6.3V
2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R 2 X5R
P18 VCC_MAIN
PP1V8_SW2 69 72
0402-10 0402-10 0402-10 0402-10 0402-10 0402-10 0402-10 0402-10 0402-10
R18
PP1V8_S2R_SW3 69 72
PP1V2_S2R 60 61 69 72
PP1V2_SW1 69 72
A 1
CRITICAL
C8160 1
CRITICAL
C8161 1 C8162
CRITICAL
1
CRITICAL
C8163 1
CRITICAL
C8164 1
CRITICAL
C8165 1
CRITICAL
C8166 1
CRITICAL
C8167 1
CRITICAL
C8168 1
CRITICAL
C8169
PP1V2_S2R_SW2 69 72
10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF 10UF PMU_VPUMP PAGE TITLE
20%
2 6.3V
X5R
20%
2 6.3V
X5R
20%
2 6.3V
X5R
20%
2 6.3V
X5R
20%
2 6.3V
X5R
20%
2 6.3V
X5R
20%
2 6.3V
X5R
20%
2 6.3V
X5R
20%
2 6.3V
X5R
20%
2 6.3V
X5R
VCC_MAIN BYPASS
PLACE TWO 10UF CAP AT EACH VDD INPUT
MAX_NECK_LENGTH=3 MM
1 C81A9
1.0UF
1 C8139
1UF
1 C8138
1.0UF
1 C81A8
1.0UF
1 C8137
1.0UF
1 C8136
1UF
1 C8135
1.0UF
PMU: ARABELA (1/3)
0402-10 0402-10 0402-10 0402-10 0402-10 0402-10 0402-10 0402-10 0402-10 0402-10 20% 10% 20% 20% 20% 10% 20% DRAWING NUMBER SIZE
VOLTAGE=4.6V
C8196 1 2 6.3V
X5R 2 6.3V
CERM 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 6.3V
CERM 2 6.3V
X5R 051-0301 D
0.22UF 0201-1 402 0201-1 0201-1 0201-1 402 0201-1 Apple Inc. REVISION
20% R
6.3V
X5R 2 B.0.0
0201 NOTICE OF PROPRIETARY PROPERTY: BRANCH
C8137 0201 OKAY IF GRAPE HAS EXT FET PROPRIETARY PROPERTY OF APPLE INC.
81 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
U8100
LDO INPUTS D2207A0
BGA OMIT_TABLE
SYM 2 OF 4
LDO OUTPUTS
72 69 65 64 61 60 PPVCC_MAIN V17 VDD_LDO1_3_4 VLDO1 U18 (50MA; 2.5-3.3V) PP3V0_S2R_HALL 61 69 72
PP1V8_S2R C13 C12 (100MA; 1.65-1.805V) PP1V7_VA_VCP

D
72 69 60
1 CAP PER PIN 1 C8200 1 C8203 72 69 65 64 61 60 PPVCC_MAIN B13

VDD_LDO2
VDD_LDO5
VLDO2
VLDO3 V18 (50MA; 2.5-3.3V) PP3V0_S2R_SENSOR
61 69 72
61 69 72
D
B12 T19 PP3V0_ALS
LDO INPUT
1UF 1UF VDD_LDO6 VLDO4 (50MA; 2.5-3.3V)
61 69 72
10% 10% B14 A13
2 6.3V 2 6.3V VDD_LDO7 VLDO5 (1000MA; 2.5-3.6V) PP3V1_S2R_MESA 61 69 72
LDO
402 402 W18 VDD_LDO8 VLDO6 A12 (150MA; 2.5-3.6V) PP3V3_ACC 61 69 72
CERM CERM B16 A14
VDD_LDO9 VLDO7 (300MA; 1.7-3.0V)
PP3V0_S2R_TRISTAR 61 69 72
PP1V2_S2R B17 Y18 PP3V0_MISC

PCB: ADD A VIA PER PIN FOR ALL 72 69 60 VDD_LDO10 VLDO8 (300MA; 1.7-3.0V)
(300MA; 1.2-3.0V)
61 69 72
VSS_* AND VSSA_* PINS PPVCC_MAIN C15 VDD_LDO11 VLDO9 A16 PP1V25_CAM
1 C8201 72 69 65 64 61 60 61 69 72
1UF W17 VDD_LDO13 VLDO10 A17 (150MA; 0.6-1.3V) PP1V0_SOC 61 69 72

10% C16 VLDO11 B15
6.3V
2 CERM VDD_LDO14 P 6 _AF 61 69 72
402
C18 VLDO13 Y17P 61 69 72
U8100 WLED_LXA0
VLDO14 A15
(300MA; 1.7-3.0V)
(300MA; 1.2-3.0V) PP1V8_SPARE
WLED_LX_A C19 2 61 69 72
D2207A0 70 63 WLED_LXA1 ON_BUF T13
(300MA; 1.7-3.0V)
(10MA; 1.8V; ON_BUFF) P 1 8_ALWAYS
BGA =PPLED_PMU_OUT_A D16 V 61 69 72
63 VOUT_WLED_A
SYM 4 OF 4 E14 9
63 IN LED_PMU_1_A WLED1_A VDD_LCM_SW C17 (NOTE: 2MHZ) 72
OMIT_TABLE _
LCD BACKLIGHT
H1 J9 63 LED_PMU_2_A F14 WLED2_A VDD_BOOST_LCM 63 70
IN
A18 C
LCM/GRAPE
H2 VSS_BUCK01 J10 63 LED_PMU_3_A G14 WLED3_A BOOST_LCM_LX B19 VOLTAGE=6.0V LCM_LX 63
IN
J11 63 IN LED_PMU_4_A H14 WLED4_A LCM_FBD15 A
VOLTAGE=6.0V PP6V0_LCM_VBOOST 63 69
D1 VSS_BUCK1_12 M
D2
J12 63 IN LED_PMU_5_A J14 WLED5_A VDD_LCM U17
J13 63 IN LED_PMU_6_A J15 WLED6_A VLCM1 T16 (100MA; 5.0-6.0V) PP5V25_GRAPE 69 72
M1 K3 VLCM2 T18 (100MA; 5.0-6.0V) NO_TEST=TRUE NC_VLCM2
E18 WLED_LXB0 =
M2 VSS_BUCK0_12 K7 LCM2_EN D7 P
1 C8212
70 63 WLED_LX_B E19 WLED_LXB1 T17 P 10UF
K8 VLCM3 V
(5MA; 5.0-6.0V) NO_TEST=TRUENC_VLCM3 20%
W4 63 =PPLED_PMU_OUT_B E16 VOUT_WLED_B CC_MAIN_VDD_LCM 2 25V
K9 X5R-CERM
Y4 VSS_BUCK2 63 LED_PMU_1_B K14 WLED1_B VOLTAGE=6.0V PP6V0_LCM_HI 0603
K10 IN
XTAL
63 IN LED_PMU_2_B L14 WLED2_B
Y1 K11 XTAL1 W19 PMU_XTAL
63 LED_PMU_3_B M14 WLED3_B
Y2 VSS_BUCK4 K12 IN
M15 XTAL2 V19 PMU_EXTAL
Y3 K13 63 IN LED_PMU_4_B WLED4_B
C A3
K15
63
IN
IN
LED_PMU_5_B
LED_PMU_6_B
N14
P14
WLED5_B
WLED6_B
C
VSS_BUCK5 L3
B3 63
L7
W8 L8 CRITICAL
Y8
VSS_BUCK23
L9 Y8200
L10 32.768K-20PPM-12.5PF
A7 2 1
L11 CRITICAL CRITICAL
B7 VSS_BUCK56 2012-1
L12 C8215 1 1 C8216
T1 L13 18PF 18PF
5% 5%
T2 VSS_BUCK04 L15 25V 2 25V
C0G-CERM 2 C0G-CERM
M3 0201 0201
D18 VSS_WLED TABLE_ALT_HEAD
M7 PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

D19 PART NUMBER
M8 TABLE_ALT_ITEM
B18 M9 197S0399 197S0392 Y8200 RDAR://PROBLEM/9936684
VSS_LCM M10 TABLE_ALT_ITEM
A1 138S0703 138S0648 C8235 AND ~15X MORE REFDES

M11
A2
M12
A19
M13
C3
C4
M16
N3
LDO BYPASS
C5 72 69 61 PP3V0_S2R_HALL
N7
C6 72 69 61 PP1V7_VA_VCP
N8
C8
VSS N9 72 69 61 PP3V0_S2R_SENSOR
C11
N10 72 69 61 PP3V0_ALS
C14
N11 PP3V1_S2R_MESA
D3 72 69 61
N12
D12 PP3V3_ACC
B D13
N13
N15
72 69 61
72 69 61 PP3V0_S2R_TRISTAR
B
E3
P3 CRITICAL CRITICAL
E15 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
P7 C8232 1 C8235 1 C8233 1 C8234 1
E17 C82A3
2.2UF 1 C8237 1 C8231 1 C8230 1
P8 10UF
6.3V 4.7UF 20UF 4.7UF 10% 2.2UF 10UF
6.3V 2.2UF
F3 X5R
20% 6.3V 20% 20% 10% 20% 10%
P9 0402-10 2 6.3V 2 6.3V 2 X5R
20%
402 2 0402 X5R 6.3V
402 2 6.3V
X5R 2 0402-10 6.3V
X5R 2
F7 CERM-X5R
402
2
402
P10 X5R 402 X5R
F8
P11
F9
VSS P12
F10
P13
F11
P15 72 69 61 PP3V0_MISC
F12 PP1V25_CAM
R3 72 69 61
F13
R7 72 69 61 PP1V0_SOC
F15
R8 PP2V6_CAM_AF
G3 72 69 61
R9
G7 72 69 61 PP2V9_CAM
R10
G8 PP1V8_SPARE
R11 72 69 61
G9 PP1V8_ALWAYS
R12 72 69 61
G10
R13
G11 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
R15
G12 C8242 1 C8270 1 C8241 1 C8240 1 C8239 1 C82A9 1 C8238 1 C8271 1
T3 0.22UF 4.7UF 10UF
6.3V 10UF
6.3V 4.7UF 100PF 4.7UF 10UF
6.3V
G13 20% 20% 20%
X5R 20%
X5R 20% 5% 20% 20%
X5R
T8 6.3V
X5R 2 6.3V 0402-10 2 0402-10 2 6.3V 16V 6.3V 0402-10 2
G15 0201 402 2
X5R X5R 2 0 -C G 2
NP 402 2
T10 402
H3 10 X5R
U3 0
H7 5
U9
H8
U19
A H9
H10
V3
V5
PAGE TITLE
H11
H12
V6
V7
PMU: ARABELA (2/3)
H13 DRAWING NUMBER SIZE
V9
H15
W3 Apple Inc. 051-0301
REVISION
D
J3
Y19 R
J7 BRANCH B.0.0
J8 NOTICE OF PROPRIETARY PROPERTY:
VOLTAGE=0V THE INFORMATION CONTAINED HEREIN IS THE
82 OF 155
8 7 6 5 4 3 2 1 61 OF 73
8 7 6 5 4 3 2 1
1
R8303
I2C ADDRESS: 0111100X (0X78) 1 C8305 200K
0.1UF 0.5%
10% 1/20W
6.3V MF
2 CERM-X5R 2 0201
0201
U8100 OMIT_TABLE
D2207A0
BGA
D SYM 3 OF 4
1 C8306 1
PLACE_NEAR=U8100.U14:8MM
C8307
PLACE_NEAR=U8100.M17:8MM
1 C8308
D
33 6 5 GPIO_BTN_HOME_L C9 BUTTON1 IREF U13 PMU_IREF
IN NET_SPACING_TYPE=ANLG 0.1UF 1UF 1UF
ANALOG
GPIO_BTN_ONOFF_L C10 U16 PMU_VREF 10% 10% 20%
32K REFRENCES
BUTTON2 VREF
INPUT
69 23 6 5 IN NET_SPACING_TYPE=ANLG
2 6.3V
CERM-X5R 2 10V
X5R 2 10V
X5R
NC_PMU_BTN3 NO_TEST=TRUE E8
BUTTON3 VDD_REF M17 PMU_VDD_REF
NET_SPACING_TYPE=ANLG
0201
402-1 0201
NC_PMU_BTN4 NO_TEST=TRUE E9
BUTTON4 VDD_REF_A U14
R4 ACC_DET VDD_RTC U15 PMU_VDD_RTC
R8399
DIGITAL
0.00 2
CLK
INPUT
25 IN PMU_USB_BRICKID 1 PMU_USB_BRICKID_R R16 OUT_32K T9 NC_PMU_OUT_32K NO_TEST=TRUE
1% ADC_IN7 N16 BRICK_ID

ADC_IN7 U6
1/20W
R14 GPIO1 CLK_PMU2OSCAR_32K_AND_RESET_L OUT 17 69 70
MF ADC_IN31
0201 C8302 1 GPIO2 U5 CLK_PMU2WLAN_32K
C8301 1 OUT 57 68 69 70
0.01UF
WDOG
D9 T7 57 68 69 70
0.01UF 10% 6 IN GPIO_SOC2PMU_KEEPACT KEEPACT GPIO3 GPIO_PMU2BT_REG_ON OUT
1 10%
6.3V 6.3V 2
X5R 67 IN PMU_SHDWN (INTERNAL PD) U12
SHDN GPIO4 M6 GPIO_PMU2WLAN_REG_ON OUT 57 68
R8330
X5R 2 01005
69 70 1.00K
CRITICAL PLACE_NEAR=U8100.V10:10MM 01005 (INTERNAL PD)
GPIO5 T5 GPIO_PMU2BBPMU_RESET_R_L 1 2 GPIO_PMU2BBPMU_RESET_L OUT 68 69 70 71
R8328
1 C8328 4 IN WDOG_SOC2PMU_RESET_IN N6 RESET_IN1 T4 UART_BATT_HDQ 1/32W
5%
100PF GPIO_TS2PMU_RESET GPIO6 IN 6 66
70 BOARD_TEMP2_P 25 IN
P6 RESET_IN2
10KOHM-1%-0.31MA
RESET
5% GPIO7 R5 GPIO_BT2PMU_HOST_WAKE 01005
MF
16V
2 NP0-C0G
BOARD_TEMP2_N 6 SOCHOT1_L
RESET_SOC_L R6 RESET_IN3 IN 57 68 70
0201 IN P4 GPIO_WLAN2PMU_HOST_WAKE
01005 D10 GPIO8 IN 57 68 70
NO_XNET_CONNECTION=TRUE 70 69 68 25 10 5 4 OUT =I2C RESET*
GPIO
NO_XNET_CONNECTION=TRUE 2 N5 GPIO_BB2PMU_HOST_WAKE_L
GPIO__ PMU22 SOC__ IRQ_L E4 GPIO9 IN 68 69 70
(TEMP2 - NEAR SPEAKER AMPS) 6 OUT SOC (PU IN SOC)
IRQ* M5 GPIO_CODEC2PMU_HS_IRQ_L
GPIO10 IN 22 69 70
PMU E12
IN SCL GPIO11 L4 GPIO_HALL2PMU_IRQ0
TS2SOC2PMU_IRQ IN 19 69
SCL_1V8 E13
I2C & DWI

4
BI SDA GPIO12 K5 IN
1 4 =I2C_SOC2PMU_SDA_1V8 J6 GPIO_HALL2PMU_IRQ1
(INTERNAL PD) D11
GPIO13 IN 6
30 25
CRITICAL PLACE_NEAR=U8100.T11:13MM 70 6 IN D W I _ S O C 2CLK
PMU_ DWI_CK H4 PCIE_WLAN2PMU_WAKE_L
1 C8321 PLACE XW AND CAP (INTERNAL PD) E11
GPIO14 IN 57 68
R8321 100PF CLOSE TO PMU 70 6 IN DO DWI_DI
GPIO15 G5 GPIO_PMU2CODEC_RESET_L (USE INTERNAL PU)
10KOHM-1%-0.31MA 5%
70 BOARD_TEMP3_P NC_PMU_DWI_DO NO_TEST=TRUE E10 DWI_DO OUT 22
BOARD_TEMP3_N XW8328 GPIO16 F5 GPIO_OSCAR2PMU_HOST_WAKE

0201 2 16V
NP0-C0G
PLACE_NEAR=U8100.V10:10MM IN 6 17
1 2 V4 GPIO17 E5
01005
70 68 PA_NTC_P NET_SPACING_TYPE=BOARD_TEMP
TDEV1 GPIO_PMU2BB_VBUS_DET OUT 68 69 71
2 SM
C NO_XNET_CONNECTION=TRUE
(TEMP3 - NEAR WIFI)
NET_SPACING_TYPE=BOARD_TEMP
NET_SPACING_TYPE=BOARD_TEMP
V10
T11
TDEV2
TDEV3
GPIO18
GPIO19
E6
E7
GPIO_PMU2LCD_PWREN
NC_PMU_GPIO19 NO_TEST=TRUE
OUT 32
C
XW8321 PLACE_NEAR=U8100.T11:12MM NET_SPACING_TYPE=BOARD_TEMP T12 TDEV4 GPIO20 D5 GPIO_DEVBRD2PMU_WAKE_L
TEMPERATURE
IN 69
1 2
NET_SPACING_TYPE=BOARD_TEMP L5 TDEV5 GPIO21 D4 NC_PMU_GPIO21 NO_TEST=TRUE
1 SM
PLACE_NEAR=U8100.T12:12MM
NET_SPACING_TYPE=BOARD_TEMP T6 TDEV6
CRITICAL AMUX_A0 G6 PPVDD_CPU_SOC_SENSE
1 C8322 NET_SPACING_TYPE=BOARD_TEMP N4 TDEV7
13 70
R8322 100PF 70 BOARD_TEMP4_P AMUX_A1 F6 PPVDD_GPU_SOC_SENSE 13 70
5% XW8322 PLACE_NEAR=U8100.T12:12MM NET_SPACING_TYPE=BOARD_TEMP P5 TDEV8 PPVDD_SRAM_SOC_SENSE
10KOHM-1%-0.31MA 16V BOARD_TEMP4_N 1 2 AMUX_A2 H6 13 70
2 NP0-C0G BATT_NTC T15 TBAT
ANALOG MUX
69 66
0201 01005
NO_XNET_CONNECTION=TRUE SM AMUX_A3 J5 ADC_BB2PMU_IMEAS_RADIO 68
PLACE_NEAR=J2701.13:10MM 70 PMU_TCAL T14 TCAL
2 AMUX_AY G4 TP_AMUX_AY 70
(TEMP4 - NEAR REAR CAM) 2 CRITICAL =PP1V8_ALWAYS 6 11 72
1 R8340 AMUX_B0 L6 NC_PMU_AMUX_B0 NO_TEST=TRUE
XW8323 PLACE_NEAR=U8100.L5:10MM C8340 =PP1V8_SOC 4 5 6 72
1 2 100PF 3.92K AMUX_B1 J4 NC_PMU_AMUX_B1 NO_TEST=TRUE
5% 0.1%
SM 16V 0201 AMUX_B2 K6 PPVDD_SOC_SOC_SENSE 12 70
NP0-C0G 2 1/20W NOSTUFF
1 01005 1 MF AMUX_B3 K4 ADC_BB2PMU_IMEAS_QPOET
TP_AMUX_BY 68 R83701 1
R8372
PLACE_NEAR=U8100.L5:10MM
CRITICAL 1 C8323 70 BOARD_TEMP5_P XW8324 PLACE_NEAR=U8100.T6:10MM
AMUX_BY H5 70 10K 100K
5% 5%
R8323 5%
100PF BOARD_TEMP5_N 1 2 RESISTOR FOR TEMP CALIBRATION 1/32W
MF
1/32W
MF
10KOHM-1%-0.31MA 2 16V SM BUCK_LDO_UOV U10 TP_BUCK_LDO_UOV 70 01005 2 2 01005
NP0-C0G
0201 01005
BUCK_SLPD_MUX U11 TP_BUCK_SLPD_MUX 70
2 XW8325
R8371
NO_XNET_CONNECTION=TRUE PLACE_NEAR=U8100.N4:10MM
V8 0.00 2
(TEMP5 - NEAR NAND 1 2 PRE_UVLO 70 SOCHOT0_L_R 1 MF SOCHOT0_L OUT 6 69
01005 0% 1/32W
SM SYS_ALIVE* C7 (SYS_ALIVE) SYS_ALIVE 70
OUT
1 XW8326 PLACE_NEAR=U8100.P5:11MM
1 2
PLACE_NEAR=U8100.T6:11MM
CRITICAL
R8324 1 C8324 70 BOARD_TEMP6_P SM
100PF BOARD_TEMP6_N
10KOHM-1%-0.31MA 5%
0201 2 16V
NP0-C0G
B PLACE_NEAR=J3100.11:10MM
(TEMP6 - NEAR FRONT CAM)
2
01005
B
1
CRITICAL PLACE_NEAR=U8100.N4:10MM
R8325 1 C8325 70 BOARD_TEMP7_P
10KOHM-1%-0.31MA 100PF BOARD_TEMP7_N
5%
0201
PLACE_NEAR=U8100.H9:10MM
2 16V
NP0-C0G
NO_XNET_CONNECTION=TRUE 2 01005
(TEMP7 - NEAR PMU)
1
PLACE_NEAR=U8100.P5:11MM
CRITICAL
R8326
1 C8326
100PF 70 BOARD_TEMP8_P
10KOHM-1%-0.31MA 5%
16V BOARD_TEMP8_N
0201 2 NP0-C0G
PLACE_NEAR=U0600.Y22:13MM 01005
NO_XNET_CONNECTION=TRUE 2
(TEMP8 - NEAR SOC)
PAGE TITLE

TABLE_ALT_HEAD PMU: ARABELA (3/3)
PART NUMBER DRAWING NUMBER SIZE
TABLE_ALT_ITEM
Apple Inc. 051-0301

REVISION
D
138S0706 138S0739 C8308
R
118S0764 118S0717 R8340
TABLE_ALT_ITEM
BRANCH B.0.0
TABLE_ALT_ITEM NOTICE OF PROPRIETARY PROPERTY:
R8321-R8328
107S0150 107S0208 THE INFORMATION CONTAINED HEREIN IS THE
83 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
152S1837 152S1789 L8425,L8455 RDAR://PROBLEM/13487208
D D
BACKLIGHT CIRCUIT MOVED HERE TO PERMIT SYNCING WITH DESIGNS USING BEACON
CRITICAL
PLACE_NEAR=U8100.C19:11MM CRITICAL
L8425 D8428 72 69 63 PPLED_OUT_A MAKE_BASE=TRUE =PPLED_PMU_OUT_A 61
4.7UH-4A-86MOHM PMEG4010BEA
72 63 =PPVCC_MAIN_LED 1 2 PPLED_OUT_A 63 69 72
69 31 LED_IO_1_A MAKE_BASE=TRUE LED_PMU_1_A 61
PILE051D-SM-COMBO-J72 A K
31 LED_IO_2_A LED_PMU_2_A
MAKE_BASE=TRUE
69 61
CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
SOD-323 MAKE_BASE=TRUE
CRITICAL 1 C8451 1 C8452 1 C8453 1 C8454 1 C8455 1 C8456 69 61
4.7UF 4.7UF 4.7UF 4.7UF 4.7UF 56PF 31 LED_IO_4_A LED_PMU_4_A

MAKE_BASE=TRUE
C8450 1
10% 10% 10% 10% 10% 2%
69 61
10UF 31 LED_IO_5_A LED_PMU_5_A

35V 35V 35V 35V 35V 50V MAKE_BASE=TRUE
69 61
20% 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 NP0-C0G-CERM
6.3V 2 0603 0603 0603 0603 0603 0201 MAKE_BASE=TRUE
69 61
X5R
0402-10
VOLTAGE=20.4V
70 61 WLED_LX_A
CRITICAL CRITICAL
C PLACE_NEAR=U8100.E19:6MM
L8455
4.7UH-4A-86MOHM
D8458 72 69 63 PPLED_OUT_B MAKE_BASE=TRUE =PPLED_PMU_OUT_B 61
C
PMEG4010BEA
72 63 =PPVCC_MAIN_LED 1 2
A K
PPLED_OUT_B 63 69 72 69 31 LED_IO_1_B MAKE_BASE=TRUE LED_PMU_1_B 61
PILE051D-SM-COMBO-J72 31 LED_IO_2_B LED_PMU_2_B
MAKE_BASE=TRUE
69 61
SOD-323 CRITICAL CRITICAL CRITICAL CRITICAL CRITICAL
31 LED_IO_3_B LED_PMU_3_B
MAKE_BASE=TRUE
CRITICAL 1 C8461 1 C8462 1 C8463 1 C8464 1 C8465 1 C8466 69 61
C8460 1
10%
4.7UF 4.7UF
10%
4.7UF
10%
4.7UF
10%
4.7UF
10%
56PF
2%
69 31 LED_IO_4_B
MAKE_BASE=TRUE LED_PMU_4_B 61
10UF 35V 35V 35V 35V 35V 50V 69 31 LED_IO_5_B
20% 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 NP0-C0G-CERM
6.3V 2 0603 0603 0603 0603 0603 0201 69 31 LED_IO_6_B
X5R
0402-10
VOLTAGE=20.4V
70 61 WLED_LX_B
B B
LCM BOOST MOVED HERE TO PERMIT SYNCING WITH DESIGNS USING KONA
MAKE_BASE=TRUE VOLTAGE=6.0V
VOLTAGE=6.0V
CRITICAL MAKE_BASE=TRUE
CRITICAL
L8429 D8430
NET_SPACING_TYPE=PWR 2.2UH-1.05A-0.195OHM PMEG2005AEL MIN_NECK_WIDTH=0.2MM
MAX_NECK_LENGTH=3 MM MIN_LINE_WIDTH=0.4MM
70 61 PP6V0_LCM_HI 1 2 PP6V0_LCM_VBOOST 61 69
A K
VLS201612E-SM CRITICAL CRITICAL
C8410 1 SOD882 1 C8411 1 C8490
2.2UF 4.7UF 4.7UF
20% 20% 20%
10V 10V 10V
X5R-CERM 2 2 X5R-CERM 2 X5R-CERM
402 0402 0402
61 LCM_LX PAGE TITLE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
POWER: J82 SPECIFIC
DIDT=TRUE DRAWING NUMBER SIZE
(NOTE: 2MHZ)
REVISION
R
BRANCH
B.0.0
SHEET
63 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D 72 =PP1V2_EXTERNAL_SW
D
72 69 65 64 61 60 PPVCC_MAIN 1 C8671
1.0UF
20%
CRITICAL 6.3V
1
2 X5R
1 C8670 0201-1
0.1UF VDD
10%
2 16V
X5R-CERM
U8670
0201 SLG5AP1443V
EXT_SW_1V2_RAMP 7 TDFN 3
CAP D
72 =PP1V2_EXT_SW_ON 2 ON S 5 PP1V2_EXT_SW 69 72
1 GND CRITICAL
R8670 CRITICAL 1 C8672
1 C8673
8
100K 10UF
5% 4700PF 20%
1/32W 10%
MF 2 10V 2 6.3V
X5R
2 01005
X7R 0402-10
201
72 =PP1V8_S2R_EXTERNAL_SW
72 69 65 64 61 60 PPVCC_MAIN 1 C8681
C CRITICAL
1.0UF
20%
6.3V C
1
2 X5R
1 C8680 0201-1
0.1UF VDD
10%
16V
2 X5R-CERM U8680
0201 SLG5AP1443V
EXT_SW_1V8_RAMP 7 TDFN 3
CAP D
72 =PP1V8_SW1_EXT_SW_ON 2 ON S 5 PP1V8_EXT_SW 69 72
1 CRITICAL
GND CRITICAL
R8680 1 C8683 1 C8682
8
100K 10UF
5% 4700PF 20%
1/32W 10%
MF 10V
2 X7R 2 6.3V
X5R
2 01005 201 0402-10
BUCK6 POWER IS ON IN HIBERNATE DUE TO WIFI PAS

SWITCH NEEDED TO GATE POWER TO NAND AND SOC
72 =PP3V3_S2R_EXTERNAL_SW
72 69 65 64 61 60 PPVCC_MAIN
1 C8655
1.0UF
20%
B 1 C8650
1
CRITICAL 2 6.3V
X5R
0201-1
B
0.1UF VDD
10%
16V
2 X5R-CERM U8650
0201 SLG5AP1443V
7
VCC_MAIN_PP3V3SW_RAMP TDFN 3
CAP D
72 =PP1V8_NAND_EXT_SW_ON 2 ON S 5 PP3V3_EXT_SW 69 72
1 CRITICAL
GND CRITICAL
R8652 1 1 C8656
C8652
8
100K 10UF
5% 4700PF 20%
1/32W 10%
MF 10V
2 X7R 2 6.3V
X5R
2 01005 201 0402-10
PAGE TITLE
POWER: EXTERNAL SWITCHES

DRAWING NUMBER SIZE

REVISION
R
BRANCH
B.0.0
SHEET
64 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
TABLE_ALT_HEAD

PART NUMBER
TABLE_ALT_ITEM
376S1192 376S0929 ? Q8823 RDAR://PROBLEM/16073848
CRITICAL
D L8812
2.2UH-20%-9A-35MOHM D
60 PPVCC_MAIN
1 2 70 SW_CHGA MAKE_BASE=TRUE
72 69 64 61 PILE101D-SM
NOSTUFF CRITICAL K MIN_NECK_WIDTH=0.10 MM
R8870 D8800 NET_SPACING_TYPE=PWR
4.7K 2 SOD-123W
DIDT=TRUE
65 25 OVP_SW_EN_L 1
PMEG4030ER
SWITCH_NODE=TRUE
5% 1 2 3 DCR=54MOHM MAX
1/20W A PMU_CHG_LX0 60
MF S
201
CRITICAL
PMU_CHG_LX1 60
4 G
Q8804 PMU_CHG_LX2 60
60
PLACE_NEAR=U8100.R17:7MM
FDMC6683 R8872 PMU_CHG_LX3
MLP3.3X3.3 0 BATT_SNS_R
69 66 BATT_SNS 1 2 MAKE_BASE=TRUE PMU_VBAT
5%
D 1/20W PLACE_NEAR=U8100.R17:10MM
1 NOSTUFF 1 PLACE_NEAR=U8100.R17:10MM
PMU_IBAT_S 60
MF
RDSON=0.0136@VGS=-2.5V 5 201
C8849 R8873 PMU_IBAT0 60
ID=12.0A LAYOUT NOTE - 0.022UF 499
R8172- PLACE NEAR PMU 2 10% PMU_IBAT1 60
C8149- PLACE NEAR PMU 25V
R8173- PLACE NEAR PMU X7R 2
201 PMU_IBAT2 60
0402 MF
72 69 65 60 PPBATT_VCC MAKE_BASE=TRUE PMU_IBAT3 60
1/20W
1%
ACT_DIO MAKE_BASE=TRUE PMU_ACT_DIO 60
MIN_NECK_WIDTH=0.1 MM
NET_SPACING_TYPE=ANLG PMU_VCEN_01 60
XW8814 LAYOUT NOTE: PLACE PMU_VCEN_02 60

MOSFET FDMC6676BZ SHORT-0201 RIGHT AT THE PIN MAKE_BASE=TRUE PMU_VCEN_03 60
5 USB_VBUS_DETECT 2 1 PMU_VCENTER
CHANNEL P-TYPE MIN_LINE_WIDTH=0.20MM PLACE_NEAR=U8100.F18:2MM
PLACE_NEAR=U8100.L18:2MM MIN_LINE_WIDTH=0.60MM
PMU_VCEN_04 60
27 MOHM @-4.5V MIN_NECK_WIDTH=0.10MM
CRITICAL CRITICAL MIN_NECK_WIDTH=0.20MM PMU_VCEN_05 60
RDS(ON) NET_
MAX_SPACING_TYPE=PWR NET_SPACING_TYPE=PWR
NECK_LENGTH=3
VOLTAGE=5.0V MM
1 C8848 1 C8847 MAX_NECK_LENGTH=3 MM
VOLTAGE=6.0V PMU_VCEN_06 60
IMAX 6.9 A 4.7UF 4.7UF PMU_VCEN_07 60

10% 10%
35V 35V PMU_VCEN_08
2 X5R-CERM 2 X5R-CERM
C VGS MAX +/- 25V 0603 0603
PMU_VBUS_01
60
60
C
PMU_VBUS_02 60
69 25 PPVBUS_PROT MAKE_BASE=TRUE
CRITICAL MIN_LINE_WIDTH=0.20MM
PLACE_NEAR=U8100.F16:14MM PMU_VBUS_03 60
NOSTUFF
K
DZ8820 MIN_NECK_WIDTH=0.15MM CRITICAL PMU_VBUS_04

3
2
1
60
R88161 CRITICAL
BZT52C10LP
MAX_NECK_LENGTH=3 MM C8845 1
PMU_VBUS_05
470K Q8823 VOLTAGE=15V 2.2UF LAYOUT NOTE: PLACE
60
1% FDMC6676BZ S LLP
10% PMU_VBUS_06 60
1/20W 25V RIGHT AT THE PIN
MLP3.3X3.3 NOTE: 10V ZENER PMU_VBUS_07
A
MF X5R-CERM 2 60
201 G 4 603
2 PMU_VBUS_08
VBUS_PROT_G 69
60
PMU_VBUS_09
10 60
60
D R88301 PMU_VBUS_11 60
5
220K
1% R8846 PMU_VBUS_12 60
72 69 PPVBUS_USB_DCIN 1/20W
MF
201 4.7K 2 PMU_OVP_OFF
2 65 25 OVP_SW_EN_L 1 OVP_SW_EN_L_R MAKE_BASE=TRUE
60
5% NOSTUFF
USB REVERSE VOLTAGE PROTECTION 1/20W
MF
1 C8846
201 0.01UF
LAYOUT NOTE: 10%
R8146, C8146 CAN BE 2 25V
X5R-CERM
ANYWHERE BET.TRISTAR 0201
AND PMU
B NOTE: FOR NO BATTERY SITUATION

B
PPBATT_VCC
72 69 65 60
CRITICAL CRITICAL
1 C8893 1 C8894
10UF
6.3V 10UF
6.3V
20%
X5R 20%
X5R
2 0402-10 2 0402-10
69 PPBATT_POS_RC
R88001 MIN_LINE_WIDTH=0.30MM
0.5 NET_SPACING_TYPE=PWR
1% VOLTAGE=4.7V
1/16W
MF
402 2
PAGE TITLE
PMU: CHARGER BUCK

DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
88 OF 155
8 7 6 5 4 3 2 1 65 OF 73
8 7 6 5 4 3 2 1
D D
C C
72 67 9 6 =PP1V8_S2R_MISC
1
R8900
4.7K
1
1% DESENSE: OK TO REMOVE FERRITE (NOW RES) IF CAP IS CLOSE TO CONNECTOR.
G
1/32W
MF
2 01005 R8901
0.00 2 APN: 516-0425
62 6 BI UART_BATT_HDQ UART_BATT_HDQ_FL 1
J8900
D
3
S
0%
1/32W RCPT-BATT-SHORT-J82
MF C8923 1
F-ST-TH
01005 82PF
Q8900 5% CRITICAL
25V
CEDM7001 2 6
SOT883L 0201
NP0-C0G
69 BATT_SWI_CONN 1 HDQ
69 62 BI BATT_NTC 2 THERM
3 PACK_NEG
C8922 1
4 PACK_POS
82PF
5% 5 SENSE
25V
NP0-C0G 2
0201
7
72 =PPBATT_POS_CONN
B B
1 C8925 1 C8929 1 C8927
33PF 15PF 82PF
5% 5% 5%
16V 16V 25V
2 NP0-C0G-CERM 2 NP0-C0G-CERM 2 NP0-C0G
01005 01005 0201
69 65 BATT_SNS
PAGE TITLE
POWER: BATTERY CONN

DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
TABLE_ALT_HEAD
BRANCH B.0.0
PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: NOTICE OF PROPRIETARY PROPERTY:
PART NUMBER
TABLE_ALT_ITEM

155S0644 155S0823 FL8900 RDAR://PROBLEM/11282371 THE POSESSOR AGREES TO THE FOLLOWING: PAGE89 OF 155
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
DEBUG RESET ACCESS

72 69 60 PP1V8_SW1 72 66 9 6 =PP1V8_S2R_MISC
1 NOSTUFF
1 NOSTUFF
R9001 R9000
1K
1K 5%
5% 1/16W
1/16W MF-LF
MF-LF 2 402
2 402
PLACE_SIDE=TOP
C 62 OUT PMU_SHDWN TP9001

1
A 69 6 OUT GPIO_FORCE_DFU 1
PLACE_SIDE=TOP
PP PP9000
SM
P4MM
C
TP-P55
B B
PAGE TITLE
SOC: DEBUG
DRAWING NUMBER SIZE

REVISION
R
BRANCH
B.0.0
SHEET
67 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CELLULAR AND WLAN/BT ALIASES

WLAN/BT
GPIO
D 70 69 68 62 57 IN CLK_PMU2WLAN_32K MAKE_BASE=TRUE CLK_PMU2WLAN_32K OUT 57 62 68 69 70
D
BASEBAND
GPIO
70 69 68 62 57
70 69 68 62 57
70 68 57 9
IN
IN
IN
GPIO_PMU2BT_REG_ON
GPIO_PMU2WLAN_REG_ON
GPIO_SOC2BT_WAKE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
GPIO_PMU2BT_REG_ON
GPIO_SOC2BT_WAKE
OUT
OUT
OUT
57 62 68 69 70
57 62 68 69 70
9 57 68 70
70 9 IN GPIO_SOC2WLAN_WAKE MAKE_BASE=TRUE GPIO_SOC2WLAN_PCIE_DEV_WAKE OUT 57

71 69 6 IN GPIO_SOC2BB_RADIO_ON_L MAKE_BASE=TRUE RADIO_ON_L OUT 35 37
69 6 IN GPIO_SOC2BB_RESET_L MAKE_BASE=TRUE BB_RST_L OUT 35 37

70 68 62 57 GPIO_BT2PMU_HOST_WAKE MAKE_BASE=TRUE GPIO_BT2PMU_HOST_WAKE 57 62 68 70
OUT IN
69 6 OUT GPIO_BB2SOC_RESET_DET_L MAKE_BASE=TRUE BB_RESET_DET_L IN 70 68 62 57 GPIO_WLAN2PMU_HOST_WAKE MAKE_BASE=TRUE GPIO_WLAN2PMU_HOST_WAKE 57 62 68 70
70 69 62 OUT IN
71 IN GPIO_PMU2BBPMU_RESET_L MAKE_BASE=TRUE RF_PMIC_RESET_L OUT 35
35 40
37
71 6
70 69 62 25 10 5 4
IN
OUT
GPIO_SOC2BB_WAKE_MODEM
RESET_SOC_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
AP_WAKE_MODEM
RESET_1V8_L
OUT
IN
40
35
70 9
PCIE
PCIE_SOC2WLAN_RESET_L MAKE_BASE=TRUE PCIE_SOC2WLAN_PERST 57
IN OUT
71 6 IN GPIO_SOC2BB_COREDUMP MAKE_BASE=TRUE BB_CORE_DUMP OUT 40
70 9 PCIE_WLAN2SOC_CLKREQ_L MAKE_BASE=TRUE PCIE_WLAN2SOC_CLKREQ 57
OUT IN
6 BI GPIO_BB_IPC MAKE_BASE=TRUE BB_IPC_GPIO BI 40
68 62 57 PCIE_WLAN2PMU_WAKE_L MAKE_BASE=TRUE PCIE_WLAN2PMU_WAKE_L 57 62 68
OUT IN
71 6 OUT GPIO_BB2SOC_GPS_SYNC MAKE_BASE=TRUE BB_GPS_SYNC IN 40
70 69 62 OUT GPIO_BB2PMU_HOST_WAKE_L MAKE_BASE=TRUE BB_WAKE_HOST IN 35 40 70 68 57 9 IN PCIE_SOC2WLAN_CLK_P MAKE_BASE=TRUE PCIE_SOC2WLAN_CLK_P OUT 9 57 68 70
70 68 57 9 IN PCIE_SOC2WLAN_CLK_N MAKE_BASE=TRUE PCIE_SOC2WLAN_CLK_N OUT 9 57 68 70
71 25 6
UART
UART_BB2SOC_TX MAKE_BASE=TRUE BB_UART_TXD 35 40
70 68 57 9 IN PCIE_SOC2WLAN_TX_P MAKE_BASE=TRUE PCIE_SOC2WLAN_TX_P OUT 9 57 68 70
OUT IN PCIE_SOC2WLAN_TX_N MAKE_BASE=TRUE PCIE_SOC2WLAN_TX_N
70 68 57 9 IN OUT 9 57 68 70
71 25 6 IN UART_SOC2BB_TX MAKE_BASE=TRUE BB_UART_RXD OUT 35 40
71 6 OUT UART_BB2SOC_RTS_L MAKE_BASE=TRUE BB_UART_RTS_L IN 40

70 9 PCIE_WLAN2SOC_TX_P MAKE_BASE=TRUE PCIE_WLAN2SOC_RX_P 57
OUT IN
71 6 IN UART_SOC2BB_RTS_L MAKE_BASE=TRUE BB_UART_CTS_L OUT 40
70 9 PCIE_WLAN2SOC_TX_N MAKE_BASE=TRUE PCIE_WLAN2SOC_RX_N 57
OUT IN
70 PCIE_WLAN2SOC_TX_C_P MAKE_BASE=TRUE PCIE_TX_P 57
71 17 IN UART_OSCAR2BB_TX MAKE_BASE=TRUE BB_OTHER_RXD OUT 40 TO KEEP PP NAMING CONSISTENT 70 PCIE_WLAN2SOC_TX_C_N MAKE_BASE=TRUE PCIE_TX_N 57
71 17 OUT UART_BB2OSCAR_TX MAKE_BASE=TRUE BB_OTHER_TXD IN 40
C HSIC UART C
70 68 57 6 IN UART_SOC2BT_TX MAKE_BASE=TRUE UART_SOC2BT_TX OUT 6 57 68 70
69 6 IN HSIC_SOC2BB_HOST_RDY MAKE_BASE=TRUE BB_HOST_RDY OUT 35 40
70 68 57 6 IN UART_SOC2BT_RTS_L MAKE_BASE=TRUE UART_SOC2BT_RTS_L OUT 6 57 68 70
69 6 OUT HSIC_BB2SOC_DEVICE_RDY MAKE_BASE=TRUE BB_DEVICE_RDY IN 35 40
70 6 OUT UART_BT2SOC_TX MAKE_BASE=TRUE UART_BT2SOC_RX IN 57
70 6 OUT UART_BT2SOC_RTS_L MAKE_BASE=TRUE UART_BT2SOC_CTS_L IN 57

71 5 BI HSIC_BB_DATA MAKE_BASE=TRUE 50_BB_HSIC_DATA BI 35 39
71 5 BI HSIC_BB_STB MAKE_BASE=TRUE 50_BB_HSIC_STROBE BI 35 39

70 68 57 6 IN UART_SOC2WLAN_TX MAKE_BASE=TRUE UART_SOC2WLAN_TX OUT 6 57 68 70
UART_SOC2WLAN_RTS_L UART_SOC2WLAN_RTS_L
USB
GPIO_PMU2BB_VBUS_DET MAKE_BASE=TRUE BB_USB_VBUS
70 68 57 6
70 6
IN
OUT UART_WLAN2SOC_TX
MAKE_BASE=TRUE
MAKE_BASE=TRUE UART_WLAN2SOC_RX
OUT
IN
6 57 68 70
57
71 69 62 IN OUT 35 39
70 6 OUT UART_WLAN2SOC_RTS_L MAKE_BASE=TRUE UART_WLAN2SOC_CTS_L IN 57
71 25 BI USB_BB_P MAKE_BASE=TRUE 90_BB_USB_P BI 35
71 25 BI USB_BB_N MAKE_BASE=TRUE 90_BB_USB_N BI 35 TP_WL_UART_RX MAKE_BASE=TRUE WL_UART_RX 57

RESOLVES CKPLUS ERROR IN NAME TP_WL_UART_TX WL_UART_TX
SIM CARD MAKE_BASE=TRUE
57
59
59
IN
OUT
SIMCRD_DETECT
SIMCRD_RST
MAKE_BASE=TRUE
MAKE_BASE=TRUE
BB_SIM_DETECT
BB_SIM_RESET
OUT
IN
39 40
40
70 6 OUT
I2S
I2S_BT2SOC_DOUT MAKE_BASE=TRUE I2S_BT2SOC_DIN IN 57
59 OUT SIMCRD_CLK MAKE_BASE=TRUE BB_SIM_CLK IN 40
70 68 57 6 I2S_SOC2BT_DOUT MAKE_BASE=TRUE I2S_SOC2BT_DOUT 6 57 68 70
IN OUT
BI SIMCRD_IO MAKE_BASE=TRUE BB_SIM_DATA BI 40
70 68 57 6 I2S_SOC2BT_BCLK MAKE_BASE=TRUE I2S_SOC2BT_BCLK 6 57 68 70
IN OUT
59
70 68 57 6 IN I2S_SOC2BT_LRCK MAKE_BASE=TRUE I2S_SOC2BT_LRCK OUT 6 57 68 70
17 IN
OSCAR CONTEXT
GPIO_OSCAR2WLAN_CONTEXT_A MAKE_BASE=TRUE OSCAR2RADIO_CONTEXT_A OUT 57 70
62
ADC
ADC_BB2PMU_IMEAS_RADIO MAKE_BASE=TRUE RADIO_TO_PMU_ADC_IMEAS_RADIO 35
17 IN GPIO_OSCAR2WLAN_CONTEXT_B MAKE_BASE=TRUE OSCAR2RADIO_CONTEXT_B OUT 57 70
OUT IN
B
62 OUT ADC_BB2PMU_IMEAS_QPOET MAKE_BASE=TRUE RADIO_TO_PMU_ADC_IMEAS_QPOET IN 44
70 OUT
JTAG
TP_JTAG_WLAN_TMS MAKE_BASE=TRUE JTAG_WLAN_TMS IN 57 B
POWER
=PPBATT_VCC_BB PP_BATT_VCC
70 OUT TP_JTAG_WLAN_TRST MAKE_BASE=TRUE JTAG_WLAN_TRST IN 57
72 35 44 53 73
POWER
=PPVCC_MAIN_WLAN PP_VCC_MAIN_WLAN
59 OUT
LOWER ANT CTRL
GPIO_BB2ANT_SW0 MAKE_BASE=TRUE BB_ANTSW_GPIO0 IN 40
72
72 =PP3V3_S2R_WIFI_PA
=PP1V8_S2R_VDDIO_WLAN_BT
PP_3V3_S2R_WIFI_PA
57
56 57
59 GPIO_BB2ANT_SW1 MAKE_BASE=TRUE BB_ANTSW_GPIO1 40

72 PP_1V8_S2R_VDDIO_WLAN_BT 57 73
OUT IN
NO CONNECT
NC_WLAN_GPIO3 NO_TEST=TRUE MAKE_BASE=TRUE BT_EXT_SYNC 57
OUT
NC_WLAN_GPIO5 NO_TEST=TRUE MAKE_BASE=TRUE BT_EXT_CLK OUT 57
NTC FOR BB
SLOTS FOR RADIO FENCE
SL9110 1
TH-NSP PLACE_NEAR=U8100.V4:11MM
1 CRITICAL 1
SL9111
TH-NSP R9127 C9127 PA_NTC_P 62 70
SL-1.1X0.4-1.4X0.7 100PF
1 XW9127
A SL-1.1X0.4-1.4X0.7
10KOHM-1%-0.31MA
0201
5%
16V
2 NP0-C0G
01005
PA_NTC_N 1
SM
2
PLACE_NEAR=U8100.V4:11MM
NO_XNET_CONNECTION=TRUE 2 NO_XNET_CONNECTION=TRUE PAGE TITLE
(TEMP1 - NEAR BB) ALIASES: BB/WLAN/BT
DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SMT TEST FIXTURE TP PLATED THROUGH HOLES
DRILL SIZE: 1.1MM X 0.4MM
POWER - BUCKS SOC - JTAG/RESET BASEBAND PLATING SIZE: 1.4MM X 0.7MM
PPVDD_CPU FUNC_TEST=TRUE 60 72 JTAG_SOC_SEL FUNC_TEST=TRUE 4 5
BOUNDARY_SCAN_EN FUNC_TEST=TRUE
35 39
PPVDD_GPU FUNC_TEST=TRUE 60 72 JTAG_SOC_TCK FUNC_TEST=TRUE 5 25

GPIO_PMU2BBPMU_RESET_L FUNC_TEST=TRUE 62 68 70 71
GPIO_SOC2BB_RADIO_ON_L FUNC_TEST=TRUE
MUST HAVE
PP0V95_SOC FUNC_TEST=TRUE 60 72 JTAG_SOC_TDI FUNC_TEST=TRUE 5
6 68 71
PP1V8_S2R FUNC_TEST=TRUE 60 61 72 JTAG_SOC_TMS FUNC_TEST=TRUE 5 25

HSIC_SOC2BB_HOST_RDY FUNC_TEST=TRUE 6 68
SL9300 APN: 998-2691
PP1V8_SW1 FUNC_TEST=TRUE TP_JTAG_SOC_TRST_L FUNC_TEST=TRUE GPIO_BB2SOC_RESET_DET_L FUNC_TEST=TRUE 6 68 TH-NSP
MUST HAVE
60 67 72 4 5
PP1V8_SW1_FOREHEAD FUNC_TEST=TRUE 72 TP_JTAG_SOC_TDO FUNC_TEST=TRUE 5 HSIC_BB2SOC_DEVICE_RDY FUNC_TEST=TRUE 6 68 1
SL9301
PP1V8_EXT_SW FUNC_TEST=TRUE
64 72 SOC_TESTMODE FUNC_TEST=TRUE
4 5
GPIO_SOC2BB_RESET_L FUNC_TEST=TRUE 6 68
SL-1.1X0.4-1.4X0.7 TH-NSP
PP1V8_SW2 FUNC_TEST=TRUE 60 72 RESET_SOC_L FUNC_TEST=TRUE 4 5 10 25 62 68 70
GPIO_PMU2BB_VBUS_DET FUNC_TEST=TRUE 62 68 71 1
PP1V8_GRAPE_EXT_SW FUNC_TEST=TRUE GPIO_FORCE_DFU FUNC_TEST=TRUE GPIO_BB2PMU_HOST_WAKE_L FUNC_TEST=TRUE 62 68 70
SL9302
MUST HAVE
30 72 6 67 SL-1.1X0.4-1.4X0.7
PP1V8_S2R_SW3 FUNC_TEST=TRUE 60 72
TH-NSP
D PP1V2_S2R
PP1V2_SW1
FUNC_TEST=TRUE
FUNC_TEST=TRUE
60 61 72
60 72
SOC - UART
UART_SOC2DEBUG_TX FUNC_TEST=TRUE 6 25
1
SL-1.1X0.4-1.4X0.7
D
PP1V2_EXT_SW FUNC_TEST=TRUE 64 72 UART_DEBUG2SOC_TX FUNC_TEST=TRUE
PP1V2_S2R_SW2 FUNC_TEST=TRUE 60 72
6 25
BASEBAND - POWER
PPVDD_SRAM FUNC_TEST=TRUE 60 72 SOC - USB PP_LDO6 FUNC_TEST=TRUE 35 36 71 73 SL9320
PP3V3_S2R FUNC_TEST=TRUE USB_SOC_N FUNC_TEST=TRUE PP_LDO13 FUNC_TEST=TRUE 36 38 55 73
TH-NSP
60 72 5 25 1
PP3V3_EXT_SW FUNC_TEST=TRUE 64 72 USB_SOC_P FUNC_TEST=TRUE 5 25
VREG_SMPS1_0V90 FUNC_TEST=TRUE 36 38 SL9321
VREG_SMPS3_0V95 FUNC_TEST=TRUE 36 73 SL-1.1X0.4-1.4X0.7 TH-NSP
1
POWER - LDOS BASEBAND - SIM CARD
PP1V7_VA_VCP FUNC_TEST=TRUE 61 72 SL-1.1X0.4-1.4X0.7
PP3V0_S2R_SENSOR FUNC_TEST=TRUE 61 72
PP_LDO5_FILT FUNC_TEST=TRUE 59
PP3V0_ALS FUNC_TEST=TRUE
61 72
SIMCRD_RST_CONN_FILT FUNC_TEST=TRUE 59 71
PP3V3_ACC FUNC_TEST=TRUE SIMCRD_CLK_CONN_FILT FUNC_TEST=TRUE
MUST HAVE
59 71
61 72 E75_ACC_DET_CONN_L FUNC_TEST=TRUE 25 27 SIMCRD_IO_CONN_FILT FUNC_TEST=TRUE
PP3V0_S2R_TRISTAR FUNC_TEST=TRUE
61 72 PPVBUS_E75_USB_CONN FUNC_TEST=TRUE 59 71
FOREHEAD B2B STANDOFFS
PP3V1_S2R_MESA FUNC_TEST=TRUE 26 27 69 SIMCRD_DETECT_FILT FUNC_TEST=TRUE 59 71
61 72
E75 PPOUT_E75_ACC_ID1_CONN FUNC_TEST=TRUE 26 27
STD9300 APN: 860-8373
PP1V0_SOC FUNC_TEST=TRUE 61 72 PPOUT_E75_ACC_ID2_CONN FUNC_TEST=TRUE
PP1V8_SPARE FUNC_TEST=TRUE 61 72 E75_DPAIR1_CONN_N FUNC_TEST=TRUE
26 27
WIFI/BT STDOFF-3.3X1.8R1.05H-SM
PP3V0_S2R_HALL FUNC_TEST=TRUE 25 27
25 27 GPIO_PMU2BT_REG_ON FUNC_TEST=TRUE 57 62 68 70
61 72 E75_DPAIR1_CONN_P FUNC_TEST=TRUE
GPIO_PMU2WLAN_REG_ON FUNC_TEST=TRUE 1
PP3V0_MISC FUNC_TEST=TRUE 61 72 E75_DPAIR2_CONN_N FUNC_TEST=TRUE 57 62 68 70
PP1V25_CAM FUNC_TEST=TRUE 25 27 CLK_PMU2WLAN_32K FUNC_TEST=TRUE 57 62 68 70

61 72 E75_DPAIR2_CONN_P FUNC_TEST=TRUE
25 27
PP2V6_CAM_AF FUNC_TEST=TRUE 61 72
PP2V9_CAM FUNC_TEST=TRUE 61 72
STD9301 APN: 860-8373
C9301
AUDIO - HEADPHONE CAMERA - REAR 0.01UF STDOFF-3.3X1.8R1.05H-SM
POWER - OTHER CONN_HP_HEADSET_DET_FILT FUNC_TEST=TRUE ISP_CAM_REAR_CLK_F FUNC_TEST=TRUE 1 2 STD9301_AC_R 1
MUST HAVE
MUST HAVE
22 23 20 21
PP1V8_ALWAYS FUNC_TEST=TRUE 61 72 CONN_HP_HS3_FILT FUNC_TEST=TRUE 22 23 ISP_CAM_REAR_SCL_F FUNC_TEST=TRUE 20 21
PPBATT_VCC FUNC_TEST=TRUE 60 65 69 72 CONN_HP_HS3_REF_FILT FUNC_TEST=TRUE
22 23 ISP_CAM_REAR_SDA_F FUNC_TEST=TRUE
20 21 10%
PPLED_OUT_A FUNC_TEST=TRUE 63 72 CONN_HP_HS4_FILT FUNC_TEST=TRUE 22 23 ISP_CAM_REAR_SHUTDOWN_L_F FUNC_TEST=TRUE 20 21
6.3V 09/17/13 AC CAP RDAR://PROBLEM//14999426
PPLED_OUT_B FUNC_TEST=TRUE X5R
63 72 CONN_HP_HS4_REF_FILT FUNC_TEST=TRUE 22 23 01005
PP5V25_GRAPE FUNC_TEST=TRUE 61 72 CONN_HP_LEFT_FILT FUNC_TEST=TRUE 22 23 CAMERA - FRONT STD9303 APN: 860-00013
PP1V8_XTAL FUNC_TEST=TRUE 11 CONN_HP_RIGHT_FILT FUNC_TEST=TRUE
22 23 ISP_CAM_FRONT_CLK_F FUNC_TEST=TRUE
20 21 STDOFF-3.3X1.8R0.84H-TH
PPVCC_MAIN FUNC_TEST=TRUE 60 61 64 65 72 GPIO_SOC2AJ_HS3_SHUNT_EN_FILT FUNC_TEST=TRUE 23 ISP_CAM_FRONT_SCL_F FUNC_TEST=TRUE 20 21
PPBATT_POS_RC FUNC_TEST=TRUE 65 GPIO_SOC2AJ_HS4_SHUNT_EN_FILT FUNC_TEST=TRUE 23 ISP_CAM_FRONT_SDA_F FUNC_TEST=TRUE 20 21
1
PP6V0_LCM_VBOOST FUNC_TEST=TRUE 61 63 ISP_CAM_FRONT_SHUTDOWN_L_F FUNC_TEST=TRUE 20 21
PPVBUS_USB_DCIN FUNC_TEST=TRUE 65 72
PPVBUS_PROT FUNC_TEST=TRUE 25 65
VBUS_PROT_G FUNC_TEST=TRUE
C 65
AUDIO - SPEAKER AMPS
SPKRAMP_L_OUT_N FUNC_TEST=TRUE 24 27 70
MESA
GPIO_MESA2SOC_IRQ_FILT FUNC_TEST=TRUE 31 33
BUTTON FLEX B2B STANDOFFS C
SPKRAMP_L_OUT_P FUNC_TEST=TRUE 24 27 70 MUST HAVE MESA_BOOST_ENABLE_FILT FUNC_TEST=TRUE APN: 860-8373
POWER - CAMERA (FRONT) SPKRAMP_R_OUT_N FUNC_TEST=TRUE 24 27 70 SPI_MESA_MISO_FILT FUNC_TEST=TRUE
31 33
31 33
STD9302
PP1V2_CAM_FRONT_FILT FUNC_TEST=TRUE 20 21 SPKRAMP_R_OUT_P FUNC_TEST=TRUE 24 27 70 SPI_MESA_MOSI_FILT FUNC_TEST=TRUE STDOFF-3.3X1.8R1.05H-SM
31 33
PP1V8_CAM_FRONT_FILT FUNC_TEST=TRUE 20 21 SPI_MESA_SCLK_FILT FUNC_TEST=TRUE 31 33 1
PP2V9_AVDD_CAM_FRONT_FILT FUNC_TEST=TRUE 20 21
AUDIO - CODEC
MUST HAVE
AIN3P FUNC_TEST=TRUE 22
POWER - CAMERA (REAR) AIN3N FUNC_TEST=TRUE
22
HALL EFFECT
PP1V25_CAM_REAR_FILT FUNC_TEST=TRUE 20 21 GPIO_CODEC2PMU_HS_IRQ_L FUNC_TEST=TRUE
PP1V8_CAM_REAR_FILT FUNC_TEST=TRUE 22 62 70 GPIO_HALL2PMU_IRQ0 FUNC_TEST=TRUE 19 62
GRAPE AND DISPLAY B2B STANDOFFS
20 21 GND_AUDIO_CODEC FUNC_TEST=TRUE 22 GPIO_HALL2PMU_IRQ1_FILT FUNC_TEST=TRUE
PP2V6_CAM_REAR_AF_FILT FUNC_TEST=TRUE 20 21 MIKEY_TS_P FUNC_TEST=TRUE 29 30
PP2V9_AVDD_CAM_REAR_FILT FUNC_TEST=TRUE 22 25 PP3V0_S2R_GRAPE_HALL_FILT FUNC_TEST=TRUE 29 30

STD9305 APN: 860-8373
20 21 MIKEY_TS_N FUNC_TEST=TRUE
MUST HAVE
22 25
STDOFF-3.3X1.8R1.05H-SM
POWER - AUDIO 1
PP1V8_DMIC_MIC_FILT FUNC_TEST=TRUE 23
PP1V8_DMIC_BTN_FILT FUNC_TEST=TRUE 28
AUDIO - DIGITAL MICS ALS
PP1V7_VCP FUNC_TEST=TRUE
22
DMIC_MIC_SCLK FUNC_TEST=TRUE 22 23 PP3V0_MIC_ALS_FILT FUNC_TEST=TRUE 23 STD9306
PPVBOOST_R FUNC_TEST=TRUE 24
DMIC_BTN_SCLK FUNC_TEST=TRUE 22 28 PP3V0_HP_ALS_FILT FUNC_TEST=TRUE 23
PPVBOOST_L FUNC_TEST=TRUE
24 GPIO_HP_ALS2SOC_IRQ_L_FILT FUNC_TEST=TRUE 23 1
GPIO_MIC_ALS2SOC_IRQ_L_F FUNC_TEST=TRUE 23
POWER - SENSORS STD9307

PP1V8_COMPASS FUNC_TEST=TRUE 18
BUTTONS I2C_HP_ALS_SCL_1V8_FILT FUNC_TEST=TRUE 23 70
PP1V8_PHOS_FILT FUNC_TEST=TRUE 18
GPIO_BTN_HOME_CONN_L FUNC_TEST=TRUE 31 33 I2C_HP_ALS_SDA_1V8_FILT FUNC_TEST=TRUE 23 70
GPIO_BTN_ONOFF_L FUNC_TEST=TRUE 1
PP1V8_OSCAR_FILT FUNC_TEST=TRUE 17
5 6 23 62
I2C_MIC_ALS_SCL_1V8_F FUNC_TEST=TRUE
PP1V2_OSCAR_FILT FUNC_TEST=TRUE GPIO_BTN_VOL_UP_L_FILT FUNC_TEST=TRUE
28
23 70
17
GPIO_BTN_VOL_DOWN_L_FILT FUNC_TEST=TRUE I2C_MIC_ALS_SDA_1V8_F FUNC_TEST=TRUE 23 70
PP3V0_GYRO_FILT FUNC_TEST=TRUE 18
28
PP3V0_SENSOR_PROX_FILT FUNC_TEST=TRUE 58
POWER - DISPLAY
PPVCC_MAIN_LCD_SW_CONN FUNC_TEST=TRUE 31 32 DISPLAY
PPVCC_MAIN_LCD_SW FUNC_TEST=TRUE
NANDANC0_CE0_L EDP_HPD_EMI FUNC_TEST=TRUE
MUST HAVE
32 32
FUNC_TEST=TRUE 7 16 70
MUST HAVE
POWER - MESA ANC1_CE0_L FUNC_TEST=TRUE 7 16 70
B PP1V825_S2R_MESA_FILT
PP3V1_S2R_MESA_FILT
FUNC_TEST=TRUE
FUNC_TEST=TRUE
31 33 OSCAR
CLK_PMU2OSCAR_32K_AND_RESET_L FUNC_TEST=TRUE B
MUST HAVE
31 33 17 62 70
31 33
PP11V3_MESA_FILT FUNC_TEST=TRUE
BATTERY
POWER - GRAPE BATT_SWI_CONN FUNC_TEST=TRUE 66
PPVDD_STINGER_BOOST FUNC_TEST=TRUE BATT_NTC FUNC_TEST=TRUE 62 66

29
BATT_SNS FUNC_TEST=TRUE 65 66
SOCHOT0_L FUNC_TEST=TRUE
6 62
GRAPE FID9300
CLK_SOC2GRAPE_32K FUNC_TEST=TRUE 9 30 70
FID
POWER - BACKLIGHT 0P5SM1P0SQ-NSP FID9301
PPLED_BACK_REG_A FUNC_TEST=TRUE 31 32
1 FID
LED_IO_1_A FUNC_TEST=TRUE 31 63 0P5SM1P0SQ-NSP
LED_IO_2_A FUNC_TEST=TRUE 31 63 1
LED_IO_3_A FUNC_TEST=TRUE
MUST HAVE
31 63
LED_IO_4_A FUNC_TEST=TRUE 31 63
FID9302
LED_IO_5_A FUNC_TEST=TRUE 31 63
FID
LED_IO_6_A FUNC_TEST=TRUE 31 63 0P5SM1P0SQ-NSP FID9303
PPLED_BACK_REG_B FUNC_TEST=TRUE 31 32
1 FID
LED_IO_1_B FUNC_TEST=TRUE 31 63
0P5SM1P0SQ-NSP
1
FID9304
FID
0P5SM1P0SQ-NSP
1
FID9305
FID
0P5SM1P0SQ-NSP
1
A 1 SYNC_MASTER=N/A SYNC_DATE=N/A A
TP9310A
TP-1P0-TOP
1 PLACE_NEAR=J3700.9:20MM TP9300A
TP-1P0-TOP
1 PLACE_NEAR=J8900.4:20MM
DEV BOARD NET TERMINATION
NC_SOC_GPIO09 NO_TEST=TRUE MAKE_BASE=TRUE GPIO_ALS2SOC_DEVBRD_IRQ_L
PAGE TITLE
TEST: TPS/HOLES/FIDUCUALS
TP9311 1 PLACE_NEAR=J3700.9:20MM
A TP9301 A
6
TP-1P0-TOP NC_PMU_GPIO20 NO_TEST=TRUE MAKE_BASE=TRUE GPIO_DEVBRD2PMU_WAKE_L 62 DRAWING NUMBER SIZE

TP-1P0-TOP
TP9312A 1 PLACE_NEAR=J3700.9:20MM PPVBUS_E75_USB_CONN 26 27 TP9302A 1 PLACE_NEAR=J8900.4:20MM PPBATT_VCC 60 65 69 72
NC_ULPI_STP NO_TEST=TRUE MAKE_BASE=TRUE GPIO_SOC2DEVBRD_S3E_WAKE 9
Apple Inc. 051-0301
REVISION
D
69
TP-1P0-TOP TP-1P0-TOP NC_ULPI_DATA3 NO_TEST=TRUE MAKE_BASE=TRUE GPIO_SOC2DEVBRD_S3E_RESET2_L 9
R
TP9315 1 PLACE_NEAR=J3700.9:30MM
A TP9305 1 PLACE_NEAR=J8900.3:20MM
A
NC_PCIE_CLKREQ2 NO_TEST=TRUE MAKE_BASE=TRUE PCIE_DEVBRD2SOC_CLKREQ_L 9 BRANCH B.0.0
TP-1P0-TOP TP-1P0-TOP NC_PCIE_PERST2 NO_TEST=TRUE MAKE_BASE=TRUE PCIE_SOC2DEVBRD_RESET_L 9 NOTICE OF PROPRIETARY PROPERTY:
TP9316A 1 PLACE_NEAR=J3700.9:30MM
TP9306A 1 PLACE_NEAR=J8900.3:20MM NC_NAND_SYS_CLK NO_TEST=TRUE MAKE_BASE=TRUE CLK_SOC2DEVBRD_PCIE_24MHZ 9 THE INFORMATION CONTAINED HEREIN IS THE
TP-1P0-TOP
1 PLACE_NEAR=J3700.9:30MM
TP-1P0-TOP NC_I2S4_MCK NO_TEST=TRUE MAKE_BASE=TRUE GPIO_DISPLAY_ID0 6 THE POSESSOR AGREES TO THE FOLLOWING: PAGE93 OF 155
TP9317 A TP9307A 1 PLACE_NEAR=J8900.3:20MM NC_I2S1_MCK NO_TEST=TRUE MAKE_BASE=TRUE GPIO_DISPLAY_ID1 6
SHEET69 OF 73
TP-1P0-TOP II NOT TO REPRODUCE OR COPY IT
TP-1P0-TOP III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
HIGH SPEED, NO TEST
EE CHARACTERIZATION TP CAMERA - FRONT
PP9520
P4MM SM
PP9521
PP
PP
1
1
MIPI_CAM_FRONT_CLK_P
MIPI_CAM_FRONT_CLK_N
PLACE_NEAR=U0600.AV36:3MM
PLACE_NEAR=U0600.AW36:3MM
8 21 70
8 21 70
I2CI2C_OSCAR2PROX_SDA_1V8
I2C_OSCAR2PROX_SCL_1V8
FUNC_TEST=TRUE
FUNC_TEST=TRUE
17 58
17 58
DDR0_CA<0..9>
DDR0_CK_P
DDR0_CK_N
DDR0_CA<0..9>
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE
10 14 70
10 14 70
10 14 70
10 14 70
P4MM SM NO_XNET_CONNECTION=TRUE I2C0_SCL_1V8 FUNC_TEST=TRUE 4 6 DDR0_CKE<0..1> NO_TEST=TRUE
10 14 70
PP9522 1 MIPI_CAM_FRONT_DATA_P<0> PLACE_NEAR=U0600.AV37:3MM

8 21 70
I2C0_SDA_1V8 FUNC_TEST=TRUE 4 6 DDR0_CSN<0..1> NO_TEST=TRUE
10 14 70
PP I2C1_SCL_1V8 FUNC_TEST=TRUE DDR0_DM<0..3>
P4MM SM NO_XNET_CONNECTION=TRUE 4 6
NO_TEST=TRUE
10 14
PP9523 1 MIPI_CAM_FRONT_DATA_N<0> PLACE_NEAR=U0600.AW37:3MM

8 21 70
I2C1_SDA_1V8 FUNC_TEST=TRUE 4 6 DDR0_DQ<0..31> NO_TEST=TRUE
10 14 70
PP I2C2_SCL_1V8 FUNC_TEST=TRUE DDR0_DQS_P<0..3>
P4MM SM NO_XNET_CONNECTION=TRUE 4 6
NO_TEST=TRUE
10 14 70
SOC CAMERA - REAR

I2C2_SDA_1V8 FUNC_TEST=TRUE 4 6 DDR0_DQS_N<0..3>
DDR1_CA<0..9>
NO_TEST=TRUE
NO_TEST=TRUE
10 14 70
PP9524 1 MIPI_CAM_REAR_CLK_P PLACE_NEAR=U0600.AV31:3MM

8 21 70
PP95F4
P4MM SM PP
1 =I2C3_SDA_1V8 4
DDR1_CK_P NO_TEST=TRUE
10 14 70
P4MM SM NO_XNET_CONNECTION=TRUE
10 14
D PP9501
P4MM SM PP
PP9503
1
1
RESET_SOC_L
SOCHOT0_L_R
PLACE_SIDE=TOP
4 5 10 25 62 68 69
PP9525
P4MM SM PP
1 MIPI_CAM_REAR_CLK_N
PLACE_NEAR=U0600.AW31:3MM
8 21 70
PP95F5
P4MM SM PP
1 =I2C3_SCL_1V8 4
DDR1_CK_N
DDR1_CA<0..9>
NO_TEST=TRUE
NO_TEST=TRUE
10 14
10 14 70
D
P4MM SM PP
62 DDR1_CKE<0..1> NO_TEST=TRUE
10 14
FUNC_TEST=TRUE PP9526 PP
1 MIPI_CAM_REAR_DATA_P<0> PLACE_NEAR=U0600.AV33:3MM
8 21 70 I2C_HP_ALS_SCL_1V8_FILT FUNC_TEST=TRUE 23 69 DDR1_CSN<0..1> NO_TEST=TRUE
6 P4MM SM NO_XNET_CONNECTION=TRUE I2C_HP_ALS_SDA_1V8_FILT FUNC_TEST=TRUE
DDR1_DM<0..3>
10 14
TP_GPIO_DFU_STATUS 23 69 NO_TEST=TRUE
10 14
PP9527
P4MM SM PP
1 MIPI_CAM_REAR_DATA_N<0> PLACE_NEAR=U0600.AW33:3MM
8 21 70 I2C_MIC_ALS_SCL_1V8_F FUNC_TEST=TRUE 23 69 DDR1_DQ<0..31> NO_TEST=TRUE
10 14 70
NO_XNET_CONNECTION=TRUE I2C_MIC_ALS_SDA_1V8_F FUNC_TEST=TRUE 23 69 DDR1_DQS_P<0..3> NO_TEST=TRUE
PP9502
P4MM SM PP
1 TP_ANALOGMUXOUT 5
PP DDR1_DQS_N<0..3> NO_TEST=TRUE
10 14 70
10 14 70
DDR2_CA<0..9>
PP9507 1 PPVDD_CPU_SOC_SENSE PLACE_NEAR=U0600.AB13:1.5MM
OSCAR UART
UART_SOC2ACC_TX FUNC_TEST=TRUE
DDR2_CK_P
NO_TEST=TRUE
NO_TEST=TRUE
10 15 70
10 15 70
P4MM SM PP
13 62 PP95C0 1 TP_OSCAR_P0_05 6 25 DDR2_CK_N NO_TEST=TRUE
PP9508
P4MM SM PP
1 PPVDD_GPU_SOC_SENSE PLACE_NEAR=U0600.N26:1.5MM
13 62
GRAPE
I2C_GRAPE_SDA_1V8 (CUMULUS TDO) FUNC_TEST=TRUE 29 30
PP95C1
P4MM
SM PP
PP
1 TP_OSCAR_P0_06
17
17
UART_ACC2SOC_TX FUNC_TEST=TRUE
6 25 DDR2_CA<0..9>
DDR2_CKE<0..1>
NO_TEST=TRUE
NO_TEST=TRUE
10 15 70
10 15 70
10 15 70
PP9588 1 PPVDD_SRAM_SOC_SENSE PLACE_NEAR=U0600.N25:1.5MM TP_JTAG_CUMULUS_M_TCK FUNC_TEST=TRUE 70 TP_OSCAR_P0_09 UART_SOC2OSCAR_TX FUNC_TEST=TRUE 6 17 DDR2_CSN<0..1> NO_TEST=TRUE
P4MM SM PP
13 62
TP_JTAG_CUMULUS_M_TDI FUNC_TEST=TRUE
30 PP95C2SM
PP
1 17 UART_OSCAR2SOC_TX FUNC_TEST=TRUE
DDR2_DM<0..3>
10 15 70
30 P4MM SM 6 17 NO_TEST=TRUE
10 15
PP9513
P4MM SM PP
1 PPVDD_SOC_SOC_SENSE PLACE_NEAR=U0600.M25:1.5MM
12 62 JTAG_CUMULUS_M_TMS FUNC_TEST=TRUE 30
P4MM
PP95C3 PP
1 TP_OSCAR_P0_17 17 DDR2_DQ<0..31> NO_TEST=TRUE
10 15 70
P4MM SM DDR2_DQS_P<0..3> NO_TEST=TRUE
10 15 70
SPI_GRAPE_SCLK FUNC_TEST=TRUE 6 30 PP95C4 PP
1 TP_OSCAR_P0_21 17
DDR2_DQS_N<0..3> NO_TEST=TRUE
10 15 70
SPI_GRAPE_MISO FUNC_TEST=TRUE 6 30
SPI_GRAPE_MOSI FUNC_TEST=TRUE PP95C8 1 TP_OSCAR_P1_02 DDR3_CA<0..9> NO_TEST=TRUE
10 15 70
PP9509
P4MM SM PP
1 TP_SOC_VSS_SENSE PLACE_NEAR=U0600.M26:1MM
12
SPI_GRAPE_CS_L FUNC_TEST=TRUE
6 30
P4MM SM PP
TP_OSCAR_P1_03
17
DDR3_CK_P NO_TEST=TRUE
10 15
6 30
PP9510 1 TP_SOC_VSS_CPU_SENSE PLACE_NEAR=U0600.AC13:1MM
12
PP95C9
P4MM SM PP
1 17 DDR3_CK_N NO_TEST=TRUE
10 15
P4MM SM PP GPIO_SOC2GRAPE_RESET_L FUNC_TEST=TRUE 6 30
SM DDR3_CA<0..9> NO_TEST=TRUE
10 15 70
GPIO_GRAPE2SOC_IRQ_L FUNC_TEST=TRUE P4MM SWD_OSCAR_IO_1V8 DDR3_CKE<0..1> NO_TEST=TRUE
DISPLAY_SYNC FUNC_TEST=TRUE
6 30 PP95CD
P4MM SM PP
1 9 17
DDR3_CSN<0..1> NO_TEST=TRUE
10 15
6 30 SWD_OSCAR_CLK_1V8 10 15
CLK_SOC2GRAPE_32K FUNC_TEST=TRUE 9 30 69 PP95CF
P4MM SM PP
1 9 17 DDR3_DM<0..3> NO_TEST=TRUE
10 15
DDR3_DQ<0..31> NO_TEST=TRUE
10 15 70
CUMULUS_M2S_CLK FUNC_TEST=TRUE 30 DDR3_DQS_P<0..3> NO_TEST=TRUE
10 15 70
NAND CUMULUS_M2S_SDA FUNC_TEST=TRUE 30 DDR3_DQS_N<0..3> NO_TEST=TRUE
10 15 70
ANC0_AD<1..7> FUNC_TEST=TRUE 7 16
ANC0_CE0_L FUNC_TEST=TRUE 7 16 69 I2C_GRAPE_SDA_1V8 FUNC_TEST=TRUE 29 30 70
ANC0_ALE FUNC_TEST=TRUE 7 16 I2C_GRAPE_SCL_1V8 FUNC_TEST=TRUE 29 30
MIPI_CAM_REAR_CLK_P NO_TEST=TRUE
8 21 70
ANC0_CLE FUNC_TEST=TRUE 7 16
MIPI_CAM_REAR_CLK_N NO_TEST=TRUE
8 21 70
ANC0_WE_L FUNC_TEST=TRUE 7 16
MIPI_CAM_REAR_DATA_P<0..1> NO_TEST=TRUE
8 21 70
ANC0_RE_L FUNC_TEST=TRUE 7 16 PP9514 1 TP_CUMULUS_S_CS_L 30 CHAN 0 NEAR DRAM CHAN 2 NEAR DRAM MIPI_CAM_REAR_DATA_N<0..1> NO_TEST=TRUE
8 21 70
SM PP
PP9534 1 DDR0_CK_P PLACE_NEAR=U1600.W13:1MM
10 PP9548 1 DDR2_CK_P PLACE_NEAR=U1700.W13:1MM
10 15 70
MIPI_CAM_REAR_CLK_FILT_P NO_TEST=TRUE
20 21
P4MM
PP9515 1 TP_CUMULUS_S_GPIO_3 P4MM SM PP 14 70 P4MM SM PP MIPI_CAM_REAR_CLK_FILT_N NO_TEST=TRUE
C ANC1_AD<0>
ANC1_CE0_L
FUNC_TEST=TRUE
FUNC_TEST=TRUE
7 16
PP
SM
30
PP9535
P4MM SM PP
1
DDR0_CK_N
PLACE_NEAR=U1600.W12:1MM
10
14 70
PP9549
P4MM SM PP
1
DDR2_CK_N
PLACE_NEAR=U1700.W12:1MM
10 15 70 MIPI_CAM_REAR_DATA_FILT_P<0..3> NO_TEST=TRUE
MIPI_CAM_REAR_DATA_FILT_N<0..3> NO_TEST=TRUE
20 21
20 21
20 21
C
ANC1_ALE FUNC_TEST=TRUE
7 16 69
P4MM PP9536
P4MM SM PP
1 DDR0_CKE<0> PLACE_NEAR=U1600.W14:1MM
10
14 70
PP9550
P4MM SM PP
1 DDR2_CKE<0> PLACE_NEAR=U1700.W14:1MM
10 15 70 MIPI_CAM_FRONT_CLK_P NO_TEST=TRUE
8 21 70
7 16 NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE
ANC1_CLE FUNC_TEST=TRUE 7 16 PP9537 1 DDR0_CA<0> PLACE_NEAR=U1600.V17:1MM
10 PP9551 1 DDR2_CA<0> PLACE_NEAR=U1700.V17:1MM 10 15 70 MIPI_CAM_FRONT_CLK_N NO_TEST=TRUE
8 21 70
ANC1_WE_L FUNC_TEST=TRUE 7 16
P4MM SM PP NO_XNET_CONNECTION=TRUE 14 70 P4MM SM PP
NO_XNET_CONNECTION=TRUE MIPI_CAM_FRONT_DATA_P<0> NO_TEST=TRUE
8 21 70
ANC1_RE_L FUNC_TEST=TRUE PP9538 1 DDR0_CA<1> PLACE_NEAR=U1600.W17:1MM

10 PP9552 1 DDR2_CA<1> PLACE_NEAR=U1700.W17:1MM
10 15 70 MIPI_CAM_FRONT_DATA_N<0> NO_TEST=TRUE
8 21 70
7 16 P4MM SM PP DDR0_CA<2>
NO_XNET_CONNECTION=TRUE 14 70 P4MM SM PP
NO_XNET_CONNECTION=TRUE MIPI_CAM_FRONT_CLK_FILT_P NO_TEST=TRUE
ANC1_DQS FUNC_TEST=TRUE 7 16 PP9539 1 PLACE_NEAR=U1600.V16:1MM PP9553 1 DDR2_CA<2> PLACE_NEAR=U1700.V16:1MM
20 21
MIPI_CAM_FRONT_CLK_FILT_N
PPVREF_ANC_SOC FUNC_TEST=TRUE
7
AUDIO
DMIC_MIC_SD FUNC_TEST=TRUE
P4MM SM PP
PP9540 1
DDR0_CA<3> PLACE_NEAR=U1600.W16:1MM
10
14 70
10
P4MM SM
PP9554
PP
1
DDR2_CA<3> PLACE_NEAR=U1700.W16:1MM
10 15 70
10 15 70
MIPI_CAM_FRONT_DATA_FILT_P<0>
NO_TEST=TRUE
NO_TEST=TRUE
20 21
20 21
PPVREF_ANC_NAND FUNC_TEST=TRUE 22 23 P4MM SM PP NO_XNET_CONNECTION=TRUE 14 70 P4MM SM PP

NO_XNET_CONNECTION=TRUE MIPI_CAM_FRONT_DATA_FILT_N<0> NO_TEST=TRUE
20 21
16 DMIC_BTN_SD FUNC_TEST=TRUE 22 28 PP9541 1 DDR0_CSN<0> PLACE_NEAR=U1600.Y14:1MM
10 PP9555 1 DDR2_CSN<0> PLACE_NEAR=U1700.Y14:1MM 10 15 70
NAND_SLOT0_RDYBSY_L FUNC_TEST=TRUE
16 GPIO_CODEC2SOC_IRQ_L FUNC_TEST=TRUE
6 22 P4MM SM PP NO_XNET_CONNECTION=TRUE 14 70 P4MM SM PP
10 15 70 EDP_DATA_P<0..3> NO_TEST=TRUE
9 32
PP9505 1 ANC0_AD<0>
PLACE_SIDE=BOTTOM
PLACE_NEAR=U0600.A37:2MM TP9500 A 1 PP9530
P4MM SM PP
1 DDR0_DQS_P<0>
DDR0_DQS_N<0>
PLACE_NEAR=U1600.D15:1MM
10
14 70
PP9545
P4MM SM PP
1 DDR2_DQS_P<0> PLACE_NEAR=U1700.D15:1MM
EDP_DATA_N<0..3> NO_TEST=TRUE
9 32
7 16 NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE
P4MM SM PP NO_XNET_CONNECTION=TRUE TP-P5
PP9531 1 PLACE_NEAR=U1600.D14:1MM
PP9546 1 DDR2_DQS_N<0> PLACE_NEAR=U1700.D14:1MM EDP_DATA_EMI_P<0..3> NO_TEST=TRUE
32
PLACE_SIDE=BOTTOM
TP9501 A 1 SPKRAMP_R_OUT_P FUNC_TEST=TRUE 24 27 69 P4MM SM PP
10
P4MM SM PP 10 15 70
EDP_DATA_EMI_N<0..3> NO_TEST=TRUE
PP9506 1 ANC0_DQS PLACE_NEAR=U0600.C36:2MM
7 16
NO_XNET_CONNECTION=TRUE 14 70 NO_XNET_CONNECTION=TRUE 32
P4MM SM PP NO_XNET_CONNECTION=TRUE TP-P5 PP9532 1 DDR0_DQ<0> PLACE_NEAR=U1600.C17:1MM
10 PP9547 1 DDR2_DQ<0> PLACE_NEAR=U1700.C17:1MM
10 15 70 EDP_DATA_EMI_CONN_P<0..3> NO_TEST=TRUE
31 32
TP9502 A 1 SPKRAMP_R_OUT_N FUNC_TEST=TRUE 24 27 69 P4MM SM PP NO_XNET_CONNECTION=TRUE 14 70 P4MM SM PP
NO_XNET_CONNECTION=TRUE EDP_DATA_EMI_CONN_N<0..3> NO_TEST=TRUE
PP9500 1 GND (PLACE_SIDE=TOP) 31 32
P4MM SM PP ATP-P51
PP9504 1 =PP1V8_NAND (PLACE_SIDE=TOP) 16 72 TP9503 TP-P5 CHAN 0 NEAR SOC CHAN 2 NEAR SOC PCIE_WLAN2SOC_TX_P NO_TEST=TRUE
P4MM SM PP PP9570 1 DDR0_DQS_P<0> PLACE_NEAR=U0600.D7:1MM
10 PP9585 1 DDR2_DQS_P<0> PLACE_NEAR=U0600.AM1:1MM
10 15 70
9 68 70
PP95G0 1 TP_ANC_TCKC_NAND (PLACE_SIDE=TOP) P4MM SM PP 14 70 P4MM SM PP PCIE_WLAN2SOC_TX_N NO_TEST=TRUE

TP9510 ATP-P51
NO_XNET_CONNECTION=TRUE NO_XNET_CONNECTION=TRUE 9 68 70
16
P4MM SM PP PP9571
P4MM SM PP
1 DDR0_DQS_N<0> PLACE_NEAR=U0600.D6:1MM
10 PP9586
P4MM SM PP
1 DDR2_DQS_N<0> PLACE_NEAR=U0600.AL1:1MM
10 15 70 PCIE_SOC2WLAN_TX_P NO_TEST=TRUE
9 57 68 70
PP95G4
P4MM SM PP
1 TP_ANC_TMSC_NAND (PLACE_SIDE=TOP) 16 1 SPKRAMP_L_OUT_P FUNC_TEST=TRUE
PP9572
DDR0_DQ<0>
14 70
PP9587
DDR2_DQ<0>
PCIE_SOC2WLAN_TX_N NO_TEST=TRUE
9 57 68 70
TP9511 ATP-P5 24 27 69
P4MM SM PP
1
10
14 70 P4MM SM PP
1
PLACE_NEAR=U0600.AR3:1MM 10 15 70
PCIE_SOC2WLAN_CLK_P NO_TEST=TRUE
9 57 68 70
1 SPKRAMP_L_OUT_N FUNC_TEST=TRUE PCIE_SOC2WLAN_CLK_N NO_TEST=TRUE
PMUGPIO_PMU2BBPMU_RESET_L FUNC_TEST=TRUE 62 68 69 71
TP9512 A TP-
P5 1
24 27 69
CHAN 1 NEAR DRAM CHAN 3 NEAR DRAM

PCIE_WLAN2SOC_TX_C_P
PCIE_WLAN2SOC_TX_C_N
NO_TEST=TRUE
NO_TEST=TRUE
9 57 68 70
68 70
68 70
GPIO_BT2PMU_HOST_WAKE FUNC_TEST=TRUE 57 62 68 70 TP9513 A PP9542 1 DDR1_DQS_P<0> PLACE_NEAR=U1600.K4:1MM 70 PP9556 PP
1 DDR3_DQS_P<0> PLACE_NEAR=U1700.K4:1MM
10 15 70 PCIE_SOC2WLAN_TX_C_P NO_TEST=TRUE
9
GPIO_BB2PMU_HOST_WAKE_L FUNC_TEST=TRUE 62 68 69 TP-P5 P4MM SM PP NO_XNET_CONNECTION=TRUE

10
14 P4MM SM NO_XNET_CONNECTION=TRUE PCIE_SOC2WLAN_TX_C_N NO_TEST=TRUE
9
GPIO_CODEC2PMU_HS_IRQ_L FUNC_TEST=TRUE 22 62 69 PP9543 1 DDR1_DQS_N<0> PLACE_NEAR=U1600.L4:1MM 70
10
PP9557
P4MM SM PP
1 DDR3_DQS_N<0> PLACE_NEAR=U1700.L4:1MM
10 15 70 PCIE_WLAN2SOC_CLKREQ_L NO_TEST=TRUE
9 68 70
P4MM SM PP NO_XNET_CONNECTION=TRUE 14 NO_XNET_CONNECTION=TRUE
PCIE_SOC2WLAN_RESET_L NO_TEST=TRUE
PMU_TCAL FUNC_TEST=TRUE 62 PP95D0
P4MM SM PP
1 I2S_SOC2SPKRAMP_MCK 6 24 PP9544 1 DDR1_DQ<0> PLACE_NEAR=U1600.H3:1MM
10
PP9558
P4MM SM PP
1 DDR3_DQ<0> PLACE_NEAR=U1700.H3:1MM
10 15 70
P4MM SM PP NO_XNET_CONNECTION=TRUE 14 70 NO_XNET_CONNECTION=TRUE
CLK_PMU2WLAN_32K FUNC_TEST=TRUE 57 62 68 69 70 PP95D1 1 I2S_SOC2SPKRAMP_BCLK 6 24
CLK_PMU2OSCAR_32K_AND_RESET_L
FUNC_TEST=TRUE 17 62 69
P4MM SM PP
PP95D2
P4MM SM PP
1 I2S_SOC2SPKRAMP_LRCK 6 24
CHAN 1 NEAR SOC CHAN 3 NEAR SOC
B PA_NTC_P
BOARD_TEMP2_P
FUNC_TEST=TRUE
FUNC_TEST=TRUE
62 68
62
PP95D3
P4MM SM PP
1 I2S_SOC2SPKRAMP_DOUT 6 24 PP9582
P4MM SM PP
1 DDR1_DQS_P<0>
PLACE_NEAR=U0600.V1:1MM
10
14 70
PP9596
P4MM SM PP
1 DDR3_DQS_P<0>
PLACE_NEAR=U0600.AT10:1MM
10 15 70 B
BOARD_TEMP3_P FUNC_TEST=TRUE 62 PP95D4 1 I2S_SPKRAMP2SOC_DOUT 6 24 PP9583
P4MM SM PP
1 DDR1_DQS_N<0> PLACE_NEAR=U0600.U1:1MM
10 PP9597
P4MM SM PP
1 DDR3_DQS_N<0> PLACE_NEAR=U0600.AT11:1MM
10 15 70
BOARD_TEMP4_P FUNC_TEST=TRUE
62 P4MM SM PP NO_XNET_CONNECTION=TRUE 14 70
DDR3_DQ<0>
BOARD_TEMP5_P FUNC_TEST=TRUE PP9584SM PP

1 DDR1_DQ<0> PLACE_NEAR=U0600.AA3:1MM
10 PP9598 PP
1 PLACE_NEAR=U0600.AP7:1MM
10 15 70
62 P4MM NO_XNET_CONNECTION=TRUE 14 70 P4MM SM NO_XNET_CONNECTION=TRUE
BOARD_TEMP6_P FUNC_TEST=TRUE 62 PP95D7
P4MM SM PP
1 I2S_SOC2CODEC_ASP_MCK 6 22
BOARD_TEMP7_P FUNC_TEST=TRUE 62
BOARD_TEMP8_P FUNC_TEST=TRUE 62
PP95D8
P4MM SM PP
1 I2S_SOC2CODEC_ASP_BCLK 6 22
TP_BUCK_LDO_UOV FUNC_TEST=TRUE 62
PP95D9SM PP 1 I2S_SOC2CODEC_ASP_LRCK 6 22
POWER, NO TEST
PP6V0_LCM_HI NO_TEST=TRUE
TP_BUCK_SLPD_MUX FUNC_TEST=TRUE 62 P4MM
PP95DA 1 I2S_SOC2CODEC_ASP_DOUT 61 63
PP 6 22 SW_CHGA NO_TEST=TRUE
65
TP_AMUX_AY
TP_AMUX_BY
FUNC_TEST=TRUE
FUNC_TEST=TRUE
62
62
PP95DB
P4MM
SM
PP
1 I2S_CODEC2SOC_ASP_DOUT 6 22 WIFI
TP_JTAG_WLAN_TMS FUNC_TEST=TRUE 68
WLED_LX_A
WLED_LX_B
NO_TEST=TRUE
NO_TEST=TRUE
61 63
61 63
PP95DC
P4MM SM PP
1 I2S_SOC2CODEC_XSP_BCLK 6 22 FUNC_TEST=TRUE PP95B5 1 UART_WLAN2SOC_RTS_L 6 68
PP9511 1 DWI_SOC2PMU_CLK NO_TEST=TRUE
6 62
P4MM SM 68 P4MM SM PP
P4MM SM PP PP95DD 1 I2S_SOC2CODEC_XSP_LRCK 6 22 TP_JTAG_WLAN_TRST
JTAG_WLAN_SEL (TDI) FUNC_TEST=TRUE 57 PP95B6 1 UART_BT2SOC_RTS_L 6 68 L81_PVCP NO_TEST=TRUE
22
PP9512 1 DWI_SOC2PMU_DO NO_TEST=TRUE SM 6 57 68 P4MM SM PP L81_NVCP NO_TEST=TRUE

22
P4MM SM PP
6 62 PP95DESM 1 I2S_SOC2CODEC_XSP_DOUT 6 22
(TD0) FUNC_TEST=TRUE
L81_FLYC NO_TEST=TRUE
22
PP95F1 1 SYS_ALIVE P4MM
P4MM
PP95DF 1 I2S_CODEC2SOC_XSP_DOUT 1 WLAN_SE
UART_ CI_IN
OC2WLAN_RTS_L FUNC_TEST=TRUE PP95B7
P4MM SM PP
1 UART_SOC2BT_RTS_L 6 57 68 L81_FLYN NO_TEST=TRUE
P4MM SM
PP 62
PP 6 22 TP95B0 A 57
L81_FLYP NO_TEST=TRUE
22
SM TP-P5 22
PP OSCAR2RADIO_CONTEXT_A FUNC_TEST=TRUE 57 68 SOC SIDE PCIE TPS
P4MM FUNC_TEST=TRUE PCIE_WLAN2SOC_TX_P
OSCAR2RADIO_CONTEXT_B
57 68
PP95A0
P4MM SM PP
1 PLACE_NEAR=U0600.D28:3MM
9 68 70
GRAPE NO_TEST
FUNC_TEST=TRUE UART_BT2SOC_
_TX 6 68 MT_PANEL_IN<0..29> NO_TEST=TRUE
SOC2BT FUNC_TEST=TRUE
UNC_TEST= 6 57
PP95A1
P4MM SM PP
1 PLACE_NEAR=U0600.E28:3MM PCIE_WLAN2SOC_TX_N 9 68 70
MT_PANEL_OUT<0..39> NO_TEST=TRUE
29 30
68 29
TRU
6 57 68
E REMOVED PCIE_SOC2WLAN_TX_C_P PP BECAUSE
WLAN2SOC THE IT BLOCKED THE SHIM RING.
UART_SOC2WLAN_
_TX 6 68
REMOVED PCIE_SOC2WLAN_TX_C_N PP BECASUE
40 57 71 THE *_P VERSION WAS REMOVED
UART_WLAN2BB_COEX_TX FUNC_TEST=TRUE 40 57
PP95A6 1
UART_BB2WLAN_COEX_RX
FUNC_TEST=TRUE 71
PP
PLACE_NEAR=U0600.J40:3MM PCIE_WLAN2SOC_CLKREQ_L 9 68 70
FUNC_TEST=TRUE
P4MM SM
6
6 57
57 68
68
BCL
I2S_SOC2BT_LRCK
K FUNC_TEST=TRUE
FUNC_TEST=TRUE
6 68
A I2S_BT2SOC_DOUT
I2S_SOC2BT_DOUT
FUNC_TEST=TRUE
FUNC_TEST=TRUE
6 57 68
57 62 68 69 70
WLAN SIDE PCIE TPS
PAGE TITLE
PP95A7 1 PCIE_WLAN2SOC_TX_C_P
CLK_PMU2WLAN_32K
FUNC_TEST=TRUE
57
57 62
62 68 69
68 69
P4MM SM PP
68 70
TEST: EE TP/PP
FUNC_TEST=TRUE PP95A8 1 PLACE_NEAR=U7500.74:3MM PCIE_WLAN2SOC_TX_C_N 68 70 DRAWING NUMBER SIZE
FUNC_TEST=TRUE P4MM SM PP
GPIO_PMU2BT_REG_ON
WLAN2PMU_HOST_WAKE
G PIO_BT2PMU_HOST_WAKE FUNC_TEST=TRUE
57 62
68
57 62 PP95A9 1 PLACE_NEAR=U7500.77:3MM PCIE_SOC2WLAN_TX_P 9 57 68 70
Apple Inc. 051-0301
REVISION
D
FUNC_TEST=TRUE 68 70
9 57
68
P4MM SM PP 9 57 68 70
R
GPIO_SOC2WLAN_WAKE FUNC_TEST=TRUE 68
PP95B0
P4MM SM PP
1 PLACE_NEAR=U7500.76:3MM PCIE_SOC2WLAN_TX_N 9 57 68 70 BRANCH B.0.0
GPIO_SOC2BT_WAKE NOTICE OF PROPRIETARY PROPERTY:
OTHER PPS PP95B1 1 PLACE_NEAR=U7500.71:3MM PCIE_SOC2WLAN_CLK_P 9 57 68 70
NO_TEST=TRUE P4MM SM PP THE INFORMATION CONTAINED HEREIN IS THE

PP95B8
P4MM SM PP
1 WLAN_GPIO_8 57
PP95B2 1 PLACE_NEAR=U7500.70:3MM PCIE_SOC2WLAN_CLK_N
9 68 70
P4MM SM PP
PP95B9
P4MM SM PP
1 WLAN_GPIO_10 NO_TEST=TRUE
57
PP95B3 1 PLACE_NEAR=U7500.1:3MM PCIE_SOC2WLAN_RESET_L
95 OF 155
P4MM SM PP SHEET
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D D
RF TEAM REQUESTED TPS

SIMCRD_RST_CONN_FILT FUNC_TEST=TRUE 59 69
SIMCRD_CLK_CONN_FILT FUNC_TEST=TRUE 59 69
SIMCRD_IO_CONN_FILT FUNC_TEST=TRUE 59 69
SIMCRD_DETECT_FILT FUNC_TEST=TRUE 59 69
PP_LDO6 FUNC_TEST=TRUE 35 36 69 73
UART_BB2SOC_TX FUNC_TEST=TRUE 6 25 68
UART_SOC2BB_TX FUNC_TEST=TRUE 6 25 68
UART_BB2SOC_RTS_L FUNC_TEST=TRUE 6 68
UART_SOC2BB_RTS_L FUNC_TEST=TRUE 6 68
UART_OSCAR2BB_TX FUNC_TEST=TRUE 17 68
UART_BB2OSCAR_TX FUNC_TEST=TRUE 17 68
UART_BB2WLAN_COEX_RX FUNC_TEST=TRUE
40 57 70
UART_WLAN2BB_COEX_TX FUNC_TEST=TRUE 40 57 70
C GPIO_SOC2BB_WAKE_MODEM
GPIO_BB2SOC_GPS_SYNC
FUNC_TEST=TRUE
FUNC_TEST=TRUE
6 68
6 68
C
USB_BB_P FUNC_TEST=TRUE 25 68
USB_BB_N FUNC_TEST=TRUE 25 68
GPIO_SOC2BB_COREDUMP FUNC_TEST=TRUE 6 68
GPIO_SOC2BB_RADIO_ON_L FUNC_TEST=TRUE 6 68 69
GPIO_PMU2BBPMU_RESET_L FUNC_TEST=TRUE 62 68 69 70
GPIO_PMU2BB_VBUS_DET FUNC_TEST=TRUE 62 68 69
PP9600
P4MM SM PP
1 HSIC_BB_DATA 5 68
PP9601
P4MM SM PP
1 HSIC_BB_STB 5 68
B B
PAGE TITLE
TEST: CELL EE TP/PP

DRAWING NUMBER SIZE

REVISION
R
BRANCH
B.0.0
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
POWER CONNECTIONS
BUCK0 (DWI DVC)
PPVDD_CPU =PPVDD_CPU
69 60
MAKE_BASE=TRUE
VOLTAGE=1.1V
13
CHARGER MAIN
69 65 64 61 60 PPVCC_MAIN =PPVCC_MAIN_AUDIO 22
MAKE_BASE=TRUE
D BUCK1 (DWI DVC) VOLTAGE=4.7V =PPVCC_MAIN_LED 63

D
69 60 PPVDD_GPU =PPVDD_GPU 13
BUCK5 (DWI DVC) LDO7 =PPVCC_MAIN_CPU
=PPVCC_MAIN_GPU
60
60
MAKE_BASE=TRUE
VOLTAGE=1.1V
69 60 PPVDD_SRAM =PPVDD_SRAM 13 69 61 PP3V0_S2R_TRISTAR =PP3V0_S2R_TRISTAR 25
=PPVCC_MAIN_SOC 60
MAKE_BASE=TRUE MAKE_BASE=TRUE
=PP3V0_S2R_ANT_SW 59 =PPVCC_MAIN_GRAPE 29 30
BUCK2 =PPVCC_MAIN_LCD 32
69 60 PP0V95_SOC =PP0V95_SOC 12 =PPVCC_MAIN_VDD_LCM 61

MAKE_BASE=TRUE
VOLTAGE=0.95V =PP0V95_PCIE_SOC 9
=PPVCC_MAIN_WLAN 68
=PP0V95_USB_SOC 5
BUCK6 =PPVCC_MAIN_MESA
=PPVCC_MAIN_ROTTERDAM
33
34
PP3V3_S2R =PP3V3_S2R_EXTERNAL_SW
BUCK3 69 60
MAKE_BASE=TRUE
VOLTAGE=3.3V =PP3V3_S2R_WIFI_PA
64
68
LDO8
69 61 60 PP1V8_S2R =PP1V8_S2R_DDR 14 15
MAKE_BASE=TRUE
VOLTAGE=1.8V =PP1V8_S2R_GRAPE_EXTERNAL_SW 30
69 64 PP3V3_EXT_SW =PP3V3_NAND 16 72 69 61 PP3V0_MISC PP3V0_MISC 61 69 72
=PP1V8_S2R_TRISTAR 25
MAKE_BASE=TRUE MAKE_BASE=TRUE
VOLTAGE=3.3V =PP3V3_USB_SOC 5
VOLTAGE=3.0V
=PP1V8_S2R_VDDIO_WLAN_BT 68
=PP1V8_S2R_MISC 6 9 66 67
=PP1V8_S2R_EXTERNAL_SW 64 BATTERY
=PP1V8_S2R_ROTTERDAM 34
69 65 60 PPBATT_VCC =PPBATT_POS_CONN 66
MAKE_BASE=TRUE
VOLTAGE=4.7V =PPBATT_VCC_BB 68
=PPBATT_AUDIO 24
LDO9
BUCK3_SW PP1V25_CAM =PP1V25_CAM_REAR
C
69 61
MAKE_BASE=TRUE
21
C
BUCK3_SW1
LDO1 VOLTAGE=1.25V
PP1V8_SW1 =PP1V8_AUDIO PP3V0_S2R_HALL =PP3V0_S2R_HALL

69 67 60
MAKE_BASE=TRUE
VOLTAGE=1.8V =PP1V8_SW1_EXT_SW_ON
22 24
64
69 61
MAKE_BASE=TRUE
VOLTAGE=3.0V
19 30
USB POWER INPUT
XWC130 69 65 PPVBUS_USB_DCIN =PPVBUS_USB_EMI 26
MAKE_BASE=TRUE
SM VOLTAGE=16V
PP1V8_SW1_FOREHEAD
72 69 PP1V8_SW1_FOREHEAD
1 2
=PP1V8_CAM_FRONT
69 72
21
LDO10
MAKE_BASE=TRUE
VOLTAGE=1.8V =PP1V8_CAM_REAR 21
69 61 PP1V0_SOC =PP1V0_MIPI_SOC 8
MAKE_BASE=TRUE
=PP1V8_DMIC VOLTAGE=1.0V =PP1V0_LPDP_SOC
23 28
LDO2 9
BUCK3_SW1_EXT 69 61 PP1V7_VA_VCP =PP1V7_VA_VCP 22
69 64 PP1V8_EXT_SW =PP1V8_VDDIO18_SOC 11
MAKE_BASE=TRUE
VOLTAGE=1.7V ON_BUF
MAKE_BASE=TRUE
VOLTAGE=1.8V =PP1V8_XTAL_SOC 11
69 61 PP1V8_ALWAYS =PP1V8_ALWAYS 6 11 62
=PP1V8_PCIE_SOC MAKE_BASE=TRUE
=PP1V8_MIPI_SOC
9
8 LDO11 VOLTAGE=1.8V
=PP1V8_NAND_SOC 7
=PP1V8_NAND PP2V6_CAM_AF =PP2V6_CAM_REAR_AF 21
=PP1V8_NAND_EXT_SW_ON
16 70
64
LDO3 69 61
MAKE_BASE=TRUE
VOLTAGE=2.6V
=PP1V8_SOC 4 5 6 62
69 61 PP3V0_S2R_SENSOR =PP3V0_S2R_PROX 58
=PP1V8_EEPROM 6
MAKE_BASE=TRUE
VOLTAGE=3.0V =PP3V0_S2R_COMPASS 18
=PP3V0_S2R_GYRO 18 BACKLIGHT BOOST

B 69 63 PPLED_OUT_A =PPLED_REG_A 32 B
BUCK3_SW2 LDO13 MAKE_BASE=TRUE
VOLTAGE=20.4V
69 60 PP1V8_SW2 =PP1V8_SPKRAMP_DVDD 24
69 61 PP2V9_CAM =PP2V9_CAM_FRONT 21
MAKE_BASE=TRUE
MAKE_BASE=TRUE
VOLTAGE=1.8V
VOLTAGE=2.9V =PP2V9_CAM_REAR 21
69 30 PP1V8_GRAPE_EXT_SW
MAKE_BASE=TRUE
VOLTAGE=1.8V
=PP1V8_GRAPE_EXT_SW 29 30 LDO4 69 63 PPLED_OUT_B
MAKE_BASE=TRUE
=PPLED_REG_B 32
69 61 PP3V0_ALS =PP3V0_HP_ALS 23
VOLTAGE=20.4V
MAKE_BASE=TRUE
VOLTAGE=3.0V =PP3V0_MIC_ALS 23
BUCK3_SW3
PP1V8_S2R_SW3 =PP1V8_S2R_OSCAR
69 60
MAKE_BASE=TRUE
VOLTAGE=1.8V =PP1V8_S2R_PHOS
17
18
LDO14
=PP1V8_S2R_GYRO 18
72 69 61 PP1V8_SPARE PP1V8_SPARE 61 69 72
=PP1V8_S2R_COMPASS 18
MAKE_BASE=TRUE
VOLTAGE=1.8V
=PP1V8_S2R_ACCEL 18
=PP1V8_S2R_PROX 58
BUCK4
69 61 60 PP1V2_S2R
MAKE_BASE=TRUE
=PP1V2_EXTERNAL_SW
=PP1V2_S2R_DDR
64 LDO5
VOLTAGE=1.2V 14 15
69 61 PP3V1_S2R_MESA =PP3V1_S2R_MESA 33
=PP1V2_S2R_DDR_SOC 10
MAKE_BASE=TRUE
VOLTAGE=3.1V
VLCM1
BUCK4_SW1
69 61 PP5V25_GRAPE =PP5V25_GRAPE 29 30
A 69 60 PP1V2_SW1
MAKE_BASE=TRUE
VOLTAGE=1.2V
=PP1V2_EXT_SW_ON 64
MAKE_BASE=TRUE
VOLTAGE=5.25V
PAGE TITLE
69 64 PP1V2_EXT_SW
MAKE_BASE=TRUE
=PP1V2_DDR_VDDQ 14 15 LDO6 POWER: ALIASES
VOLTAGE=1.2V =PP1V2_VDDIOD_SOC 10 11 DRAWING NUMBER SIZE
PP3V3_ACC =PP3V3_ACC
=PP1V2_HSIC_SOC 5
69 61
MAKE_BASE=TRUE
VOLTAGE=3.3V
25

=PP1V2_PLL_SOC 9 11
REVISION
R
=PP1V2_CAM_FRONT 21
BRANCH
B.0.0
BUCK4_SW2 THE INFORMATION CONTAINED HEREIN IS THE
69 60 PP1V2_S2R_SW2 =PP1V2_S2R_OSCAR 17 I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE 121 OF 155
MAKE_BASE=TRUE
VOLTAGE=1.2V
SHEET
72 OF 73
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
D 1.225V PP_LDO1 36 38 42 43
D
1.8V PP_LDO2 36 38
1.8V PP_LDO3 36 37 38 55
3.075V PP_LDO4 36 38
2.85V PP_LDO5 36 38 59
2.85V PP_LDO6 35 36 69 71
1.9V PP_LDO7 36 38 40
2.05V PP_LDO8 36 42 43
1.2V PP_LDO9 36 38
0.9V PP_LDO10 36 38
1.8V PP_LDO11 35 36 38 39 40 42 43 44
0.95V PP_LDO12 36 38
2.95V PP_LDO13 36 38 55 69
2.95V PP_LDO13_GPS 55
2.7V PP_LDO14_RFSW 36 46 47
0.95V VREG_SMPS3_0V95 36 69
2.075V VREG_SMPS4_2V075 36
0.9V PP_VSW_S1 36
1.25V PP_VSW_S2 36
0.95V PP_VSW_S3 36
2.075V PP_VSW_S4 36
C C
4.7V PP_BATT_VCC 35 44 53 68
4.7V PP_VCC_MAIN 73
4.2V PP_BATT_VCC_2GPA 45
4.2V PP_BATT_VCC_QPOET 44 45 50 51
4.2V PP_BATT_VCC_RADIO 35 36
4.7V PP_BATT_VCC_DSM 53
4.2V PP_BATT_VCC_QPOET_HBS 51
4.2V PP_BATT_VCC_QPOET_ASM 50
1.8V PP_1V8_S2R_VDDIO_WLAN_BT 57 68
1.8V PP_WL_VDDIO 57
4.7V PP_VCC_MAIN 73
S1_GND 36
0V
S2_GND 36
0V 36
S3_GND 36
0V
S4_GND
0V
0V GND_SW 44
0V VOUT_BOOST_GND 44
B B
PAGE TITLE
BB/WLAN VOLTAGE ATTRIBUTES

DRAWING NUMBER SIZE
Apple Inc. 051-0301

REVISION
D
R
BRANCH B.0.0
THE POSESSOR AGREES TO THE FOLLOWING: 155 OF 155
PAGE
SHEET 73 OF 73
8 7 6 5 4 3 2 1

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L8106

U2180 D3591 U4770

U7800 Y5201 L8107 L8150 L8108

以上位置使用 337S0104,377S0155 為有極性;使用377 S0184

LAST_MODIFIED=Mon Sep 29 18:09:18 2014

10 11 SOC: DDR N/A

35 50 CELL: PROBE PTS & DEBUG CONN RADIO

60 81 PMU: ARABELA (1/3) N/A

Apple Inc. 051-0301 D

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

THE POSESSOR AGREES TO THE FOLLOWING: PAGE

ISP0 REAR CAMERA

COMPASS PHOSPHOROUS+ GRYO ACCEL

Apple Inc. 051-0301

Page Notes PART#

Power aliases required by this page:

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

(NONE) 343S00021 343S00016 U0600 IC,CAPRI,A1,PROD,SCK

BOM options provided by this page:

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

343S0675 1 IC,PMU,ARABELA,D2207A0,TOP-AC,FCBGA380 U8100 CRITICAL

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

333S0803 2 IC,CAPRI,DRAM,10X10MM,FBGA261 U1600,U1700 CRITICAL

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

333S0804 333S0803 U1600,U1700 ELPIDA DRAM

333S00014 333S0803 U1600,U1700 SAMSUNG DRAM

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

335S0972 1 TOSHIBA 16GB MLC 1YNM PPN1.5 U1800 CRITICAL 16GB_PROD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:

335S1035 335S0972 16GB_PROD U1800 HYNIX 16GB MLC 1YNM PPN1.5

64GB FLASH CONFIGURATIONS TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

335S00011 1 SANDISK 64GB TLC 1YNM PPN1.5 U1800 CRITICAL 64GB_PROD

MECHANICAL PARTS PART NUMBER ALTERNATE FOR

806-7118 1 RADIO FENCE X190 PD_FENCE_RADIO CRITICAL MLB_B

806-00001 1 AP FENCE X190 PD_FENCE_AP CRITICAL

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

335S00012 1 SANDISK 128GB TLC 1YNM PPN1.5 U1800 CRITICAL 128GB_PROD

BARCODE LABEL/EEEE CODES

335S00018 335S00012 128GB_PROD U1800 TOSHIBA 128GB TLC 1YNM PPN

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

825-00067 1 EEEE FOR 639-5813 (MLB A 16GB) EEEE_FQJ3 CRITICAL EEEE_MLB_A_16GB

825-00067 1 EEEE FOR 639-5814 (MLB A 32GB) EEEE_FQJ0 CRITICAL EEEE_MLB_A_32GB

825-00067 1 EEEE FOR 639-5815 (MLB A 64GB) EEEE_FQJ1 CRITICAL EEEE_MLB_A_64GB

825-00067 1 EEEE FOR 639-5816 (MLB A 128GB) EEEE_FQJ2 CRITICAL EEEE_MLB_A_128GB

825-00067 1 EEEE FOR 639-4747 (MLB B 16GB) EEEE_FH54 CRITICAL EEEE_MLB_B_16GB

825-00067 1 EEEE FOR 639-5809 (MLB B 32GB) EEEE_FQHY CRITICAL EEEE_MLB_B_32GB

825-00067 1 EEEE FOR 639-5810 (MLB B 64GB) EEEE_FQHW CRITICAL EEEE_MLB_B_64GB

825-00067 1 EEEE FOR 639-5811 (MLB B 128GB) EEEE_FQHV CRITICAL EEEE_MLB_B_128GB

A CKPLUS WAIVE TABLE SYNC_MASTER=N/A SYNC_DATE=N/A A

Apple Inc. 051-0301

BOOT CONFIG ID R0510 MASTER: SOC

70 6 IN I2C2_SCL_1V8 MAKE_BASE=TRUE =I2C_HP_ALS_SCL_1V8 OUT 23

R0560 =I2C_MIC_ALS_SCL_1V8 OUT 23

EFUSE SHOULD BE TIED TO GROUND PER SEG

1NOSTUFF 1 MLB_A 1 1DEV

BRD_ID[3-0] S/W READ FLOW R0530

0001 RESERVED 2. DISABLE PU AND ENABLE PD 0%

SOC: MISC & ALIASES

Apple Inc. 051-0301 D

69 4 IN SOC_TESTMODE AT39 TESTMODE (REQUEST_DFU2_L) MENU_KEY* AM26 GPIO_BTN_HOME_L IN

Apple Inc. 051-0301 D

70 24 OUT I2S_SOC2SPKRAMP_DOUT AK41 I2S3_DOUT 24 OUT