Ultra Fast FET-Input

Operational Amplifier CORPORATION

LH0032 / LH0032C

FEATURES GENERAL DESCRIPTION

• 500V/µs Slew Rate The LH0032 is a FET input, high slew rate amplifier capable
• 70MHz Bandwidth of driving up to 100mA current.
• 1012
Ω Input Impedance
• As Low as 2mV Max Input Offset Voltage With wide bandwidth, high slew rate, high input impedance
• FET Input and high current drive capability, LH0032 is an ideal choice for
• Offset Null with Single Pot many applications that includes high speed integrator, video
• No Compensation for Gains Above 50 amplifier, summing amplifier, high speed D/A converters, etc.
• Peak Output Current to 100mA ORDERING INFORMATION
Part Package Temperature Range
LH0032G H12A (TO8-12 Lead) -55oC to +125oC
LH0032CG H12A (TO8-12 Lead) -25oC to +85oC

CONNECTION DIAGRAMS

OUTPUT
COMPENSATION
BALANCE/ NC
COMPENSATION
3 2 1 V+
4 12
INV -
5 11 OUT
INPUT +
6 10
NON-INV 7 8 9 V-
INPUT
NC NC
NC

Top View

H12A

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This datasheet has been downloaded from http://www.digchip.com at this page

 LH0032 / LH0032C
CORPORATION

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±18V
Input Voltage, VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±VS
Differential Input Voltage . . . . . . . . . . . . . . . . . . ±30V or± 2VS
Power Dissipation, PD
TA = 25oC. . . . . . . . . . . . . 1.5W, derate 100oC/W to 125oC
TC = 25oC. . . . . . . . . . . . . 2.2W, derate 70oC/W to 125oC
Operating Temperature Range, TA
LH0032G . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
LH0032CG . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to +85oC
Operating Junction Temperature, TJ . . . . . . . . . . . . . . 175oC
Storage Temperature Range . . . . . . . . . . . . -65oC to +150oC
Lead Temp. (Soldering, 10 seconds). . . . . . . . . . . . . . 300oC

DC ELECTRICAL CHARACTERISTICS VS = ±15V, TMIN ≤ TA ≤ TMAX unless otherwise noted (Note 1) (TA = T j)

LH0032 LH0032C
SYMBOL PARAMETER UNITS TEST CONDITIONS
MIN TYP MAX MIN TYP MAX

2 5 2 15
VOS Input Offset Voltage mV TA = TJ = 25oC (Note 3)
10 20

∆VOS/∆T Average Offset Voltage Drift 15 50 15 50 µV/ o C (Note 4)

25 50 pA VIN = 0 TJ = 25oC (Note 2)

IOS Input Offset Current 250 500 pA TA = 25oC (Note 3)
25 5 nA

100 500 pA TJ = 25oC (Note 2)

IB Input Bias Current 1 5 nA TA = 25oC (Note 3)
50 15 nA

VINCM Input Voltage Range ±10 ±12 ±10 ±12 V Note 6

Common Mode Rejection

CMRR 50 60 50 60 dB ∆VIN = ±10V
Ratio

60 70 60 70 dB VO = ±10V, TJ = 25oC
f = 1kHz
AVOL Open-Loop Voltage Gain
RL = 1kΩ
57 57 (Note 7)

VO Output Voltage Swing ±10 ±13.5 ±10 ±13 V RL = 1kΩ

TA = 25oC,
IS Power Supply Current 18 20 20 22 mA
IO = 0 (Note 3)

Power Supply Rejection ∆VS = 10V

PSRR 50 60 50 60 dB
Ratio (±5 to ±15V)

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LH0032 / LH0032C
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AC ELECTRICAL CHARACTERISTICS VS = ±15V, RL = 1kΩ, TJ = 25oC (Note 5)

SYMBOL PARAMETER MIN TYP MAX UNITS CONDITIONS

SR Slew Rate 350 500 V/µs AV = +1

ts Settling Time to 1% of Final Value 100 ∆VIN = 20V

AV = -1
ts Settling Time to 0.1% of Final Value 300 ns

tR Small Signal Rise Time 8 20

AV = +1, ∆VIN = 1V
tD Small Signal Delay Time 10 25

Note 1. LH0032G/CG are 100% production tested as specified at 25 oC, Specifications at temperature extremes are verified by testing, periodic
characterization, or correlation.
Note 2. Specification is at 25oC junction temperature due to requirements of high-speed automatic testing. Actual values at operating
temperature will exceed the value at TJ = 25oC. When supply voltages are ±15V, no-load operating junction temperature may rise 40-60oC above
ambient, and more under load conditions. Accordingly, VOS may change one to several mV, and I B and IOS will change significantly during
warm-up. Refer to IB and I OS vs. temperature graph for expected values.
Note 3. Measured in still air 7 minutes after application of power. Guaranteed thru correlated automatic pulse testing.
Note 4. ∆VOS/∆T is the average value calculated from measurements at 25 oC and TMAX, specifications at temperature are verified by testing,
periodic characterization, or correlation.
Note 5. Not 100% production tested; verified by testing, periodic characterization, or correlation.
Note 6. Guaranteed by CMRR test condition.
Note 7. Guaranteed thru correlated pulse testing at T j = 25 oC.

AUXILIARY CIRCUITS

Offset Null Output Short Circuit Protection

V+ V+
LM113
12
6
10k +
2
11 62Ω
12 LH0032
6 4
+ 5
3 -
10
11
INPUTS LH0032 OUTPUT
5
- 10

V-
V-

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 LH0032 / LH0032C
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TYPICAL PERFORMANCE CHARACTERISTICS

MAXIMUM POWER SUPPLY CURRENT

DISSIPATION vs. SUPPLY VOLTAGE
2.5 24
INFINITE HEAT SINK
TA = -55˚C
22
POWER DISSIPATION (W)

SUPPLY CURRENT (mA)

2.0
θJC = 70˚C/W 20

1.5 TC = 25˚C
18

16
1.0
NO HEAT SINK 14 TA = +125˚C
θJA = 100˚C/W
0.5
12

0 10
0 25 50 75 100 125 150 5 10 15 20

TEMPERATURE (˚C) SUPPLY VOLTAGE (±V)

INPUT VOLTAGE RANGE AND OUTPUT BODE PLOT

VOLTAGE vs. SUPPLY VOLTAGE (UNCOMPENSATED)
20 80
VS = ±15V
RL = 1k
0
TC = 25˚C
VOLTAGE GAIN (dB)

15 60 45

PHASE (DEGREES)
VINCM , VOUT (±V)

VOUT 90
PHASE
10 40 135

VIN 180
GAIN
5 20 225

270

0 0
0 5 10 15 20 10k 100k 1M 10M 100M

SUPPLY VOLTAGE (±V) FREQUENCY (Hz)

BODE PLOT (UNITY GAIN LARGE SIGNAL

COMPENSATED) FREQUENCY RESPONSE
80 26
VS = ±15V
24 A V = +10
22
VOLTAGE GAIN (dB)

VOLTAGE GAIN (dB)

60
PHASE (DEGREES)

20
0 18
PHASE
40 45 16 A V = +1

90 14
VS = ±15V
GAIN 12
20 135 RL = 1k
10 TC = +25˚C
8
0 6
10k 100k 1M 10M 100M 10 100 1M 10M 100M

FREQUENCY (Hz) FREQUENCY (Hz)

CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
LH0032 / LH0032C
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TYPICAL PERFORMANCE CHARACTERISTICS (Continued)

COMMON MODE REJECTION LARGE SIGNAL

RATIO vs. FREQUENCY PULSE RESPONSE
COMMON-MODE REJECTION RATIO (dB)

90
VS = ±15V
80 +10
RL = 1k VS = ±15V

OUTPUT VOLTAGE (V)

70 A V = +1
+5 RL = 1k
60
50
0
40
30
-5
20
10 -10
0
10k 100k 1M 10M 100M 0 100 200 300 400 500

FREQUENCY (Hz) TIME (ns)

LARGE SIGNAL NORMALIZED INPUT BIAS AND OFFSET

PULSE RESPONSE CURRENT vs. JUNCTION TEMPERATURE
10 4
10
TO CURRENT AT TJ = 25˚C

VS = ±15V
CURRENT – NORMALIZED
OUTPUT VOLTAGE (V)

A V = +10 10 3
5 RL = 1k

0 10 2

-5
101

-10
10 0
0 100 200 300 400 500 25 45 65 85 105 125 145 165

TIME (ns) JUNCTION TEMPERATURE (˚C)

NORMALIZED INPUT BIAS

CURRENT DURING WARM-UP
100

VS = ±15V
CURRENT – NORMALIZED
TO CURRENT AT TIME = 0

TA = 25˚C

10

1
0 2 4 6 8 10

TIME FROM POWER TURN-ON (MINUTES)

CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
 LH0032 / LH0032C
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TYPICAL APPLICATIONS

Unity Gain Amplifier 10X Buffer Amplifier

8pF - 10pF 5pF
V- V-

12 12
2k 6 2 6 2
INPUT + INPUT +
3 3
11 11
LH0032 OUTPUT LH0032 OUTPUT

4 5
5 -
- 10
9k
10
100pF

V-

1k V-

100

100X Buffer Amplifier Non-Compensated Unity Gain Inverter

V+ V+
10k
6 12
INPUT +
11 +
LH0032
5
- 10k
10 5 12
INPUT -

V- LH0032
11
OUTPUT
270
10k
6
+ 10
0.01
100
V-
+

High Speed Sample and Hold

100Ω

V+
-

2N2222 LH0032 VOUT

2N4391 100Ω
VIN +

10k 2N3907 CS = 1000pF

V-
1N914
1k
V+

LOGIC
CONTROL
1/2 DH0034
*Use polystyrene dielectric for minimum drift

V-

CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
LH0032 / LH0032C
CORPORATION

TYPICAL APPLICATIONS (Continued)

High Speed Current Mode MUX

3.8pF

4 5 R5 6

V- 18µF
12
R1 2 AM9710 11 5
A1 - 2
5.1k 3
G1 11
LH0032 VOUT
6
3 1 +
R2 6
A2 10
5.1k
G2
V-

R3 9 5 7
A3
5.1k
G3

R4 13 10 8
A4
5.1k
G4

12 14

APPLICATION INFORMATION:

Power Supply Decoupling

The LH0032, like most high speed circuits, is sensitive to
layout and stray capacitance. Power supplies should be
bypassed as near to pins 10 and 12 as practicable with low
inductance capacitors such as 0.01µF disc ceramics.
Compensation components should also be located close to
the appropriate pins to minimize stray reactances.
Input Current
Because the input devices are FETs, the input bias current
may be expected to double for each 11oC junction
temperature rise. This characteristic is plotted in the typical
performance characteristics graphs. The device will self-heat
due to internal power dissipation after application of power
thus raising the FET junction temperature 40-60oC above
free-air ambient temperature when supplies are ±15V. The
device temperature will stabilize within 5-10 minutes after
application of power, and the input bias currents measured at
that time will be indicative of normal operating currents. An
additional rise would occur as power is delivered to a load due
to additional internal power dissipation.
There is an additional effect on input bias current as the input
voltage is changed. The effect, common to all FETs, is an
avalanche-like increase in gate current as the FET
gate-to-drain voltage is increased above a critical value
depending on FET geometry and doping levels. This effect
will be noted as the input voltage of the LH0032 is taken
below ground potential when the supplies are ±15V. All of the
effects described here may be minimized by operating the
device with VS ≤ ±15V.
These effects are indicated in the typical performance curves.
Input Capacitance
The input capacitance to the LH0032/LH0032C is typically
5pF and thus may form a significant time constant with high
value resistors. For optimum performance, the input

CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
 LH0032 / LH0032C
CORPORATION

capacitance to the inverting input should be compensated by Compensation

a small capacitor across the feedback resistor. The value is
Two compensation schemes may be used, depending on the
strongly dependent on layout and closed loop gain, but will
designer’s specific needs.
typically be in the neighborhood of several picofarads.
The first technique is shown in Figure 1. It offers the best
In the non-inverting configuration, it may be advantageous to
0.1% settling time for a ±10V square wave input. The
bootstrap the case and/or a guard conductor to the inverting
compensation capacitors CC and CA should be selected from
input. This serves both to divert leakage currents away from
Figure 2 for various closed-loop gains. Figure 3 shows how
the non-inverting input and to reduce the effective input
the LH0032 frequency response is modified for different value
capacitance. A unity gain follower so treated will have an
compensation capacitors.
input capacitance under a picofarad.

Figure 1. LH0032 Frequency Compensation Circuit Figure 2. Recommended Value of Compensation

Capacitor vs Closed-Loop Gain for Optimum
Settling Time

COMPENSATION CAPACITANCE CC (pF)

COMPENSATION CAPACITANCE CA (pF)

+15V
R3 0.01µF
10 100

12 CA
R2 5 _
4 75
11
INPUT LH0032 OUTPUT
R1 6 + 3 5 CC 50
2 CC
10 CA
25

0.01µF
0 0
-15V
1 10 100 1000

CLOSED LOOP GAIN

Figure 3. The Effect of Various Compensation Figure 4. LH0032 Unity Gain Non-Inverting Large
Capacitors on LH0032 Open Loop Frequency Signal Pulse Response:
Response TA = 25oC, CC = 10pF, CA = 100pF

80
A VOL
C C = 0pF 10V
PHASE SHIFT (DEGREES)

60 C C = 1pF 0
VOLTAGE GAIN (dB)

C C = 5pF
C C = 10pF
40 -45

20 C C = 5pF -90
C C = 10pF
PHASE
0 VS = ±15V -135
RL = 1k C C = 1pF
TA = 25˚C C C = 0pF
-20 -180 10V 100nS
10k 100k 1M 10M 100M

FREQUENCY (Hz)

CALOGIC CORPORATION, 237 Whitney Place, Fremont, California 94539, Telephone: 510-656-2900, FAX: 510-651-1076
LH0032 / LH0032C
CORPORATION

Although this approach offers the shortest settling time, the waveform is shown in Figure 6. The settling time to 1% final
falling edge exhibits overshoot up to 30% lasting 200 to value is actually superior to the first method of compensation.
300ns. Figure 4 shows the typical pulse response. However, the LH0032 suffers slow settling thereafter to 0.1%
accuracy at the falling edge, and nearly four times as much at
If obtaining minimum ringing at the falling edge is the primary
the rising edge, compared to the previous scheme. Note,
objective, a slight modification to the above is recommended.
however, that the falling edge ringing is considerably reduced.
It is based on the same circuit as that of Figure 1.
Furthermore, the slew rate is consistently superior using this
The values of the unity gain compensation capacitors CC and compensation because of the smaller value of Miller
CA should be modified to 5pF and 1000pF, respectively. capacitance CC required.
Figure 5 shows the suitable capacitance to use for various
The second compensation scheme works well with both
closed-loop gains. The resulting unity gain pulse response
inverting or non-inverting modes. Figure 7 shows the circuit
schematic, in which a 270ohm resistor and a 0.01µF capacitor
Figure 5. Recommended Value of Compensation are shunted across the inputs of the device. This lag
Capacitor vs Closed-Loop Gain for Optimum Slew Rate compensation introduces a zero in the loop modifying the
response such that adequate phase margin is preserved at
unity gain crossover frequency. Note that the circuit requires
no additional compensation.
COMPENSATION CAPACITANCE CC (pF)

COMPENSATION CAPACITANCE CA (pF)

5
Heat Sinking
4 1000 While the LH0032 is specified for operation without any
explicit heat sink, internal power dissipation does cause a
significant temperature rise. Improved bias current
3 performance can thus be obtained by limiting this temperature
rise with a small heat sink such as the Thermalloy No. 2241 or
CC equivalent. The case of the device has no internal
2 500
connection, so it may be electrically connected to the sink if
CA this is advantageous. However, that this will affect the stray
1 capacitance to all pins and may thus require adjustment of
circuit compensation values.

0 0
1 10 100 1000

CLOSED LOOP GAIN

Figure 6. LH0032 Unity Gain Non-Inverting Large Figure 7. LH0032 Non-Compensated Unity Gain
Signal Pulse Response: CC = 5pF, CA = 1000pF Compensation

+15V
10V
1k 0.01µF

1k 5 _ 12

11
INPUT 270 LH0032 OUTPUT
1k 6 +
10
0.01µF

0.01µF

-15V
10V 50nS

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