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  • Counters

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    Abhishek
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    counters

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    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
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    4 views3 pages

    Counters

    Uploaded by

    Abhishek
    class notes

    Copyright:

    © All Rights Reserved
    Download as TXT, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 3

    Up Counter

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;

    entity UPCOUNTER_4 is
    port (CLK,RST: in std_logic; Q: out std_logic_vector(3 downto 0));
    end UPCOUNTER_4;

    architecture behavioural of UPCOUNTER_4 is

    signal Q_S:std_logic_vector(3 downto 0):="0000";

    begin
    process(CLK,RST)
    begin
    if(RST='0') then
    Q_S <= "0000";
    else if(CLK' event and CLK='1') then
    Q_S <= Q_S+'1';
    end if;
    end if;
    end process;
    Q <= Q_S;
    end behavioural;

    Down Counter

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;

    entity DOWNCOUNTER_4 is
    port (CLK,RST: in std_logic; Q: out std_logic_vector(3 downto 0));
    end DOWNCOUNTER_4;

    architecture behavioural of DOWNCOUNTER_4 is

    signal Q_S:std_logic_vector(3 downto 0):="1111";

    begin
    process(CLK,RST)
    begin
    if(RST='0') then
    Q_S <= "1111";
    else if(CLK' event and CLK='1') then
    Q_S <= Q_S-'1';
    end if;
    end if;
    end process;
    Q <= Q_S;
    end behavioural;

    Up-Down Counter

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;

    entity UPDOWNCOUNTER_5 is
    port (DIR,CLK,RST: in std_logic; Q: out std_logic_vector(4 downto 0));
    end UPDOWNCOUNTER_5;

    architecture behavioural of UPDOWNCOUNTER_5 is

    signal Q_S:std_logic_vector(4 downto 0):="00000";

    begin
    process(CLK,RST)
    begin
    if(RST='1') then
    Q_S <= "00000";
    else if(CLK' event and CLK='1') then
    if(DIR='1') then
    Q_S <= Q_S+'1';
    else
    Q_S <= Q_S-'1';
    end if;
    end if;
    end if;
    end process;
    Q <= Q_S;
    end behavioural;

    MOD 200 Down Counter

    library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;

    entity DOWN_MOD200 is
    port (CLK,RST: in std_logic; Q: out std_logic_vector(7 downto 0));
    end DOWN_MOD200;

    architecture behavioural of DOWN_MOD200 is

    signal Q_S:std_logic_vector(7 downto 0):="11000111";

    begin
    process(CLK,RST)
    begin
    if(RST='1') then
    Q_S <= "11000111";
    else if(CLK' event and CLK='1') then
    if (Q_S="00000000") then
    Q_S <= "11000111";
    else
    Q_S <= Q_S-'1';
    end if;
    end if;
    end if;
    end process;
    Q <= Q_S;
    end behavioural;

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