EXPERIMENT - 7

AIM:To Design a 16x1 Mux with help of 4x1 Mux using structural techinique in Verilog HDL.
TOOL USED:XilinkVivado 2014.2
THEORY:In electronics, a multiplexer (or mux) is a device that combines several analog or
digital input signals and forwards them into a single output line.[1] A multiplexer of inputs
has select lines, which are used to select which input line to send to the output.[2]
Multiplexers are mainly used to increase the amount of data that can be sent over the
network within a certain amount of time and bandwidth.[1] A multiplexer is also called a
data selector. Multiplexers can also be used to implement Boolean functions of multiple
variables.
An electronic multiplexer makes it possible for several signals to share one device or
resource, for example, one A/D converteror one communication line, instead of having one
device per input signal

DESIGN:
Truth Table:

INPUTS OUTPUTS
G1 G2 D1 C B A 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 0 0 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1
0 0 0 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1
0 0 0 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1
0 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1
0 0 1 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1
0 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1
0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1
0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1
0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1
0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
0 1 X X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 0 X X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 X X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Circuit Diagram:

Applications of 16 :1 Multiplexers
 Communication System
 Computer Memory
 Telephone Network
 Transmission from the Computer System of a Satellite

Data Flow Code :

module mux16(d1,d2,d3,d4,e,s1,s2,o);
input [3:0] d1,d2,d3,d4;
input [1:0] s1,s2;
output [3:0] e;
output o;
wire [3:0] d1,d2,d3,d4,e;
wire [1:0] s1,s2;
wire o;
mux41 a1(e[0],d1,s1);
mux41 a2(e[1],d2,s1);
mux41 a3(e[2],d3,s1);
mux41 a4(e[3],d4,s1);
mux41 a5(o,e,s2);
endmodule

module mux41(o,d,s);
output o;
input [3:0] d;
input [1:0] s;
wire [3:0] d;
wire [1:0] s;
wire o;
assign o=d[s];
endmodule

Test Bench :
module mux16tb;
reg [3:0] d1,d2,d3,d4;
reg [1:0] s1,s2;
wire [3:0] e;
wire o;
integer a,b,c,d,e1;
mux16 mycode(d1,d2,d3,d4,e,s1,s2,o);
initial
begin
for(a=0;a<=15;a=a+1)
begin
d1=a;
for(b=0;b<=15;b=b+1)
begin
d2=b;
for(c=0;c<=15;c=c+1)
begin
d3=c;
for(d=0;d<=15;d=d+1)
begin
d4=d;
for(e1=0;e1<=3;e1=e1+1)
begin
s1=e1;
s2=0;#1;s2=1;#1;s2=2;#1;s2=3;#1;
end
end
end
end
end
end
endmodule

Schematic Diagram :
Simulation Result

CONCLUSION:
The Design and simulation for 16x1 Mux has been done and simulatioin results are in
accordance with the used truth table and logic design.