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  • SPI Verification IP: Serial Peripheral Interface Features Applications

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    Peer Mohammed
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    SPI VIP provides a complete verification solution of SPI DIP supporting multiple configurations. The pluggable protocol monitor and checker (PMC) supports multiple bus standard protocols both on the master and slave interface. The coverage model provides a comprehensive Functional Coverage infrastructure enabling high Functional Coverage. The VIP enables easy integration in to module and SoC verification platforms with minimal user intervention enabling robust and rapid design verification.

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    SpiVip

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    SPI VIP provides a complete verification solution of SPI DIP supporting multiple configurations. The pluggable protocol monitor and checker (PMC) supports multiple bus standard protocols both on the master and slave interface. The coverage model provides a comprehensive Functional Coverage infrastructure enabling high Functional Coverage. The VIP enables easy integration in to module and SoC verification platforms with minimal user intervention enabling robust and rapid design verification.

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    Download as PDF, TXT or read online from Scribd
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    111 views3 pages

    SPI Verification IP: Serial Peripheral Interface Features Applications

    Uploaded by

    Peer Mohammed
    SPI VIP provides a complete verification solution of SPI DIP supporting multiple configurations. The pluggable protocol monitor and checker (PMC) supports multiple bus standard protocols both on the master and slave interface. The coverage model provides a comprehensive Functional Coverage infrastructure enabling high Functional Coverage. The VIP enables easy integration in to module and SoC verification platforms with minimal user intervention enabling robust and rapid design verification.

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    of 3

    SPI Verification IP

    SPI VIP Data Sheet

    Serial Peripheral Interface

    Features Applications
    • Supports Multiple SPI Slave Models • Module Level SPI IP Verification
    o Custom • SoC Level SPI IP Verification
    o EEPROM
    • Supports Multiple Protocols of SPI Advantages
    • Supports FIFO / Non-FIFO Mode of Transfer
    • Easy Integration in both SoC & Module
    • Supports configurable Address & Data Bits Level Verification
    • Programmable Delay • Configurable for Multiple Slave standards
    o Address to Data Delay
    • Multiple Switches to Enable Verification
    • Supports Address First / Data First Modes of Transfer Components
    • Supports MSB / LSB First Modes of Data Transfer
    • Supports Programmable 8 Bit Prescalar
    o Prescale by 1/2, 1/4, 1/8, 1/16, …… 1/256
    • Pluggable Master Protocol Monitor & Checker, Functional
    Coverage
    o AHB & APB
    • Pluggable Scoreboard
    o AHB & APB
    • Pluggable Slave Protocol Monitor, Checker, Functional
    Coverage & Driver
    • Supports Multiple Simulators

    SPI VIP

    The SPI VIP endeavors in providing a complete verification solution of SPI DIP supporting multiple
    configurations. The pluggable protocol monitor and checker (PMC) supports multiple bus standard
    protocols both on the master and slave interface. The pluggable scoreboard provides extensive data
    validation with both AHB and APB bus standards. The coverage model provides a comprehensive
    functional coverage infrastructure enabling high functional coverage. The VIP is highly & easily
    configurable enabling various verification components enabled as per the user requirements. The VIP
    enables easy integration in to module and SoC verification platforms with minimal user intervention
    enabling robust and rapid design verification.

    MindTree Ltd. Dec 2008 1


    SPI VIP Data Sheet

    SPI VIP Usage Model Diagram

    Module Level

    SoC Level

    MindTree Ltd. Dec 2008 2


    SPI VIP Data Sheet

    Deliverables
    • System Verilog VIP Package • Documentation
    • Simulation Scripts o VIP User Manual
    o VCS o Verification Plan
    o NC-Verilog • Technical Support
    o Model Sim
    • VIP Integration Utilities

    More Information
    For additional information contact :

    Design House
    MindTree Ltd Phone : +91 80 26264000
    West Campus - Global Village Fax : +91 80 26264100
    RVCE Post Email : ippool@mindtree.com
    Mysore Road Web : www.mindtree.com
    Bangalore – 560 059
    Karnataka – INDIA

    Copyright © MindTree Ltd, 2008. All Rights Reserved.


    Technical specifications are subjected to change without prior notice.

    MindTree Ltd. Dec 2008 3

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