Stivenson Hernandez

Digital Systems I

Homework week 3

Using your identification number you must selecting the digit of the half and make the analysis of sequential logic in terms of truncated in the
respective combination.

You must present:

1. Analysis of timing diagrams with truncation of the Flip-Flop´s.
2. Schematic circuits with flip-flop´s and the NAND gate of truncation.

As can be seen in the example:

In data 1030596266
 0 1 2 3 4

5 6 7 8 9

Module 10 counter, displayed 0, 1, 2, 3, 4, 5, 6, 7 ,8 y 9

NOTE: You must send the document diligence in .pdf format, with your personal answer to EDMODO platform.