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 Schematic Timing Graph
The logic connectivity has been established after netlist is read in and design linked. Represent the design as a node graph. The ports and pins in the design become the
nodes in the graph, and the timing arcs become the connections between the nodes
 Combinational Gate Sequential cell
Combinational logic cells have timing arcs from each input to each output. Sequential cell have timing arcs from the clock to outputs and
timing constraints for data pins w.r.t. the clock.
This is because a change in the output can only be caused by a change at the
clock pin for a simple flop.
 Positive Unate Arc
A rising transition on an input causes the output to rise or not change.
A falling transition on an input causes the output to fall or not change.
E.g. AND/OR gate

Negative Unate Arc

A rising transition on an input causes the output to fall or not change.
A falling transition on an input causes the output to rise or not change.
E.g. NAND/NOR gate

Non-unate Arc
Output transition cannot be determined solely from the direction of
change of an input but also depends upon the state of the other inputs.
E.g. XOR gate
 Slower, Smaller footprint, Higher Resistance Faster, Larger footprint, Lower Resistance
Less current and slower slew rate, but consume lower power Draw more current thus faster slew rate, but consume more power
Approximation to Real Physics
Trade-off between Accuracy and Speed
Resistive Shielding Effective Capacitance
The output capacitance seen from the drive point is effectively less than the total When wire resistance is not negligible anymore, effective capacitance has to be used for
capacitance of the wire. Near-end capacitance will be charged quicker than far-end calculating delay through the driving cell
capacitance because of wire resistance.
 Estimation? Extraction?
Parasitic Value can be estimated or extracted depends on whether or not the actual wire has been routed.
 RC Tree Topology
Single input node
No resistive loops
All capacitance are grounded
Wire Load Model Topographical
Best-case Tree Balanced Tree Worst-case Tree
 Slew Degradation
Slowdown of the slew rate due to resistance as it travels along the wire
 Max Path Delay Calculation Min Path Delay Calculation
Worst slew must be chosen and propagated forward. Choose slowest slew to Worst slew must be chosen and propagated forward. Choose fastest slew to
propagate to downstream propagate to downstream
Max Delay Arc Min Delay Arc
“Max” stimuli is used for cell arc delay calculation “Min” stimuli is used for cell arc delay calculation
1) Maximum annotated lumped capacitive wire load are used.  max SPEF 1) Minimum annotated lumped capacitive wire load are used.  min SPEF
2) Maximum pin capacitance or receiver model are used.  max library 2) Minimum pin capacitance or receiver model are used.  min library
3) Maximum slew propagation is performed at slew merge point.  max slew rate 3) Minimum slew propagation is performed at slew merge point.  min slew rate
Single Mode
Same delay across entire design.
* Setup check :
> Launch path: slowest path through max-delay arc, single operation condition, no derating
> Capture path: fastest path through max-delay arc, single operation condition, no derating
* Hold Check:
> Launch path: fastest path through max-delay arc, single operation condition, no derating
> Capture path: slowest path through max-delay arc, single operation condition, no derating

Best Case & Worst Case (bc_wc)

Two extreme PVT corners: One corner for either of setup or check
* Setup check :
> Launch path: slowest path through max-delay arc, worst-case operation condition, late derating
> Capture path: fastest path through max-delay arc, worst-case operation condition, early derating
* Hold Check:
> Launch path: fastest path through min-delay arc, best-case operation condition, early derating
> Capture path: slowest path through min-delay arc, best-case operation condition, late derating
On-chip Variation (OCV)
The min/max delays and slews establish the ranges for possible delays and slews.
The actual delays and slews on the chip could be anywhere between these min/max bounds.
* Setup check :
> Launch path: slowest path through max-delay arc, worst-case operation condition, late derating
> Capture path: fastest path through min-delay arc, best-case operation condition, early derating
* Hold Check:
> Launch path: fastest path through min-delay arc, best-case operation condition, early derating
> Capture path: slowest path through max-delay arc, worst-case operation condition, late derating
 Timing Window
The timing window refers to the period of time between earliest possible
switching time and latest possible switching time.
 Graph-based Analysis
A timing arc can have only a single set of timing values, and these values are used for all graph paths through the timing arc.
Timing window is propagated downstream for crosstalk calculation.
 Path-based Analysis
The same timing arc can have different delay and slew for every path through the arc.
Single edge is propagated downstream for crosstalk calculation.
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