Professional Documents
Culture Documents
COURSEFILE
Coursefile contents:
1. Cover Page
2. Syllabus copy
3. Vision of the department
4. Mission of the department
5. PEOs and POs
6. Course objectives and outcomes
7. Brief note on the importance of the course and how it fits in to the curriculum
8. Prerequisites
9. Instructional Learning Outcomes
10.Course mapping with PEOs and POs
11.Class Time Table
12.Individual Time Table
13.Lecture schedule with methodology being used/adopted
14.Detailed notes
15.Additional/missing topics
16.University previous Question papers
17. Question Bank
18.Assignment topics
19.Unit wise questions
20.Tutorial problems
21.Known gaps
22.Discussion topics
23.References, Journals, websites and E-links
24. Quality measurement Sheets
b. Teaching evaluation
(Name of the Subject / Lab Course) : Switching Theory and Logic Design
Distribution List :
2) Sign : 2) Sign :
2) Sign : 1) Name :
3) Design : 2) Sign :
4) Date : 3) Design :
4) Date :
2) Sign :
3) Date :
2. Syllabus copy
JAWAHARLAL NEHRU TECHNOLOGIVAL UNIVERSITY HYDERABAD
UNIT I
NUMBER SYSTEMS AND BOOLEAN ALGEBRA AND SWITCHING FUNCTIONS: Number
systems: Base Conversion Methods, Complement of Numbers, Codes - Binary codes, Binary Coded
Decimal code and its properties, Unit distance codes, Alpha Numeric codes, Error detecting and
correcting codes.
Boolean Algebra: Basic theorems and properties
Switching Functions: Canonical and Standard forms, Algebraic simplification of digital logic gates,
Properties of XOR gates , Universal gates, Multilevel NAND/NOR realizations.
UNIT II
MINIMIZATION AND DEGIN OF COMBINATIONAL CIRCUITS: Introduction, The
Minimization with theorem, The Karnaugh Map Method, Five and Six variable Maps, Prime and
Essential Implications, Don’t care Map entries, Using the maps for Simplifying, Tabular method, Partially
specified Expressions, Multi-Output Minimization, Minimization and combinational Design, Arithmetic
Circuits, Comparator, Multiplexers, Code Converters, Wired Logic, Tristate Bus system, Practical
Aspects related to Combinational Logic Design, Hazards and Hazard Free Relations.
UNIT III
SEQUENCTIAL MACHINES FUNDAMENTALS: Introduction, Basic Architectural Distinctions
between Combinational and Sequential circuits, the Binary Cell, Fundamentals of Sequential Machine
Operation, The Flip-Flop, The D- Latch Flip-Flop, the Clocked T Flip-Flop, the clocked J-K Flip-Flop,
Design of a clocked Flip-flop, conversion from one Type of Flip-Flop to another, Timing and Triggering
considerations, Clock skew.
UNIT IV
SEQUENTIAL CIRCUITS DESIGN AND ANALYSIS: Introduction, State diagram, Analysis of
Synchronous Sequential Circuits, Approaches to the Design of Synchronous sequential Finite State
Machines, Design Aspects, State Reduction, Design Steps, Realization using Flip-Flops.
Counters: Design Of Single Mode Counters; Ripple Counter, Ring Counter, Shift Register, Shift
Register Sequences, Ring Counter using Shift Register.
UNIT V
SEQUENTIAL CIRCUITS : Finite state machine-capabilities and limitations, Mealy and Moore
models-minimization of completely specified and incompletely specified sequential machines, Partition
techniques and Merger chart methods-concept of minimal cover table.
ALGOROTHIMIC STATE MACHINES : Salient features of the ASM chart-Simple examples-System
design using data path and control subsystems-control implementations-examples of Weighing machine
and Binary multiplier.
TEXT BOOKS :
1. Switching & Finite Automata theory – Zvi Kohavi and Neeraj K Jha, ,3rd Edition, Cambridge.
2. Digital Design – Morris Mano, PHI, 3rd Edition.
REFERENCE BOOKS:
1. Introduction to Switching Theory and Logic Design – Fredriac J Hill, Gerald R Peterson, 3rd Edition,
John Willey and Sons Inc,
2. Digital Fundamentals – A Systems approach – Thomas L Floyd, Pearson, 2013.
3. Digital Logic Design – Ye Brian and HoldsWorth, Elsevier
4. Fundamentals of Logic Design – Charles H. Roth, Thomson Publications, 5th Edition, 2004
5. Digital Logic Applications and Design – John M. Yarbrough, Thomson Publications, 2006
6. Digital logic and state machine design – Comer, 3rd, Oxford 2013.
3. Vision of EEE
To provide excellent Electrical and electronics education by building strong teaching and research environment
4. Mission of EEE
To offer high quality graduate program in Electrical and Electronics education and to prepare students for
professional career or higher studies. The department promotes excellence in teaching, research, collaborative
activities and positive contributions to society
5.1 PROGRAM EDUCATIONAL OBJECTIVES
PEO 1. Graduates will excel in professional career and/or higher education by acquiring knowledge in
Mathematics, Science, Engineering principles and Computational skills.
PEO 2. Graduates will analyze real life problems, design Electrical systems appropriate to the requirement that
are technically sound, economically feasible and socially acceptable.
PEO 3.Graduates will exhibit professionalism, ethical attitude, communication skills, team work in their
profession, adapt to current trends by engaging in lifelong learning and participate in Research & Development.
5.2 PROGRAM OUTCOMES
PO 1. An ability to apply the knowledge of Mathematics, Science and Engineering in Electrical and
Electronics Engineering.
PO 2. An ability to design and conduct experiments pertaining to Electrical and Electronics Engineering.
PO 3. An ability to function in multidisciplinary teams
PO 4. An ability to simulate and determine the parameters such as nominal voltage current, power and
associated attributes.
PO 5. An ability to identify, formulate and solve problems in the areas of Electrical and Electronics
Engineering.
PO 6. An ability to use appropriate network theorems to solve electrical engineering problems.
PO 7. An ability to communicate effectively.
PO 8. An ability to visualize the impact of electrical engineering solutions in global, economic and societal
context.
PO 9. Recognition of the need and an ability to engage in life-long learning.
PO 10 An ability to understand contemporary issues related to alternate energy sources.
PO 11 An ability to use the techniques, skills and modern engineering tools necessary for Electrical
Engineering Practice.
PO 12 An ability to simulate and determine the parameters like voltage profile and current ratings of
transmission lines in Power Systems.
PO 13 An ability to understand and determine the performance of electrical machines namely speed, torque,
efficiency etc.
PO 14 An ability to apply electrical engineering and management principles to Power Projects.
6.1 COURSE OBJECTIVES
S.No Objectives
1 To learn basic tools for the design of digital circuits and fundamental concepts used in the design of digital systems
To Understand common forms of number representation in digital electronic circuits and to be able to convert
2 between different representations.
5 To impart to student the concepts of sequential circuits, enabling them to analyze sequential systems interms of state
machines.
6 To implement synchronous state machines using flip flops.
Outcome
S.No.
1 Able to manipulate numeric information in different forms, e.g. different bases, signed integers, various
codes such as ASCII, gray, and BCD.
2 Able to manipulate simple Boolean expressions using the theorems and postulates of Boolean algebra and
to minimize combinational functions.
3 Able to design and analyze small combinational circuits and to use standard combinational
functions/building blocks to build larger more complex circuits.
4 Able to design and analyze small sequential circuits and devices and to use standard sequential
functions/building blocks to build larger more complex circuits.
a. This Course provides in-depth knowledge of switching theory and design techniques of digital
circuits, which is the basis for design of any digital circuit.
b. This subject is required to understand the later subjects like LDICA, MPMC, VLSI& ES, etc.
c. By studying this subject, the students can design and understand digital systems and its
importance.
d. The students logical thinking capability will be improved which will help in placements and in
their future technical assignments.
8. PREREQUISITES:
UNIT-I
Sl Module Outcomes
No.
1 Able to Know different number systems
2 Able to do Conversion Operations between different
Number System and number systems
3 Boolean Algebra and Able to know basic theorems and properties used in
Switching Functions Boolean algebra
4 Designs different logic circuits using different logic
gates
5 Designs multilevel realization functions
UNIT-II
Sl Module Outcomes
No.
1 Able to get basic information in the design of
combinational circuits
2 Minimization and Design Able to solve and analyze Karnaugh Maps
3 of Combinational Circuits Designs Combinational multi level circuits
4 Able to know the operation of Multiplexers and other
arithmetic circuits
5 Can perform practical’s with combinational logic
circuits
UNIT-III
Sl Module Outcomes
No.
1 Able to identify architectural differences in
combinational and sequential circuits
2 Sequential machines Able to design sequential circuits for machine
fundamentals operation
3 Able to design Clocked flip flops
4 Makes use of timing and triggering circuits with
sequential logics
UNIT-IV
Sl Module Outcomes
No.
1 Able to draw state diagrams
2 Able to analyze synchronous sequential circuits
3 Sequential circuit design Designs sequential finite state machines
4 and analysis Designs different types of counters and registers
UNIT-V
Sl Module Outcomes
No.
1 Able to identify capabilities and limitations of finite
state machine
2 Able to know Mealy and Moore minimization
Sequential circuits and models
3 algorithmic state machines Able to know partition techniques and merger chart
methods
4 Able to know about concept of minimal cover table
5 Able to design any system using data path and
controls subsystems
6 Knows the control logics of weighing machine and
binary multiplier
*When the course outcome weightage is < 40%, it will be given as moderately correlated (1).
*When the course outcome weightage is >40%, it will be given as strongly correlated (2).
POs 1 2 3 4 5 6 7 8 9 10 11 12 13
STLD 2 2 2 1 2 1 1 2 2 2
CO 1: 2 2 2 1 2 1 1 2 2 2
a. Explain different
Number Systems,
Digital Systems
Year/Sem/Sec: II-B. Tech-II Sem(Version-0) Room No: Acad Year 2015-16, WEF: 07-12-2015
Class Teacher: Mrs.D.Radhika
09.30- 10.20- 11.10- 12.50-
Time 12.00-12.50 13.30-14.20 14.20-15.10 15.10-16.00
10.20 11.10 12.00 13.30
Period 1 2 3 4 5 6 7
CACHE/SPORTS/
Monday EC NT EM-II PS-I MEFA LIBRARY/
MENTORING
LUNCH
HOD:_______________DeanAcad:_______________Principal:_________________
SL.No. Unit Total Week Topic to be covered Regular/ Teaching aids Remarks
No. No. of No. in One lecture Additional used
LCD/OHP/BB
Periods
TUTORIAL
TUTORIAL
TUTORIAL
TUTORIAL
26 Comparator Regular BB
TUTORIAL
38 Regular BB
39 BB
40 VI 9
41 Regular BB
42 WEEK 9 Regular BB
43 Regular BB
44 Regular BB
45 Additional BB
46 BB
47 B.TECH I-MID
INTERNAL
EXAMINATIONS
48 WEEK 10
49 V Regular BB
50 Regular BB
51 Regular BB
52 Regular BB
53 WEEK 11 Regular BB
(15TH SEP
54 TO 21ST BB
SEP)
55
56 Regular BB
57 Regular BB
58 WEEK 12 Regular BB
59 Regular BB
60 Additional BB
61 BB
62 BB
63
Signals carry information and are defined as any physical quantity that varies with time, space, or any other
independent variable. For example, a sine wave whose amplitude varies with respect to time or the motion of a
particle with respect to space can be considered as signals. A system can be defined as a physical device that
performs an operation on a signal. For example, an amplifier is used to amplify the input signal amplitude. In this
case, the amplifier performs some operation(s) on the signal, which has the effect of increasing the amplitude of the
desired information-bearing signal.
Signals can be categorized in various ways; for example discrete and continuous time domains. Discrete-time
signals are defined only on a discrete set of times. Continuous-time signals are often referred to as continuous
signals even when the signal functions are not continuous; an example is a square-wave signal.
Number Systems
Introduction
Number systems provide the basis for all operations in information processing systems. In a number system the
information is divided into a group of symbols; for example, 26 English letters, 10 decimal digits etc. In conventional
arithmetic, a number system based upon ten units (0 to 9) is used. However, arithmetic and logic circuits used in
computers and other digital systems operate with only 0's and 1's because it is very difficult to design circuits that require
ten distinct states. The number system with the basic symbols 0 and 1 is called binary. ie. A binary system uses just two
discrete values. The binary digit (either 0 or 1) is called a bit.
A group of bits which is used to represent the discrete elements of information is a symbol. The mapping of symbols to a
binary value is known a binary code. This mapping must be unique. For example, the decimal digits 0 through 9 are
represented in a digital system with a code of four bits. Thus a digital system is a system that manipulates discrete
elements of information that is represented internally in binary form.
Decimal Numbers
The invention of decimal number system has been the most important factor in the development of science and
technology. The decimal number system uses positional number representation, which means that the value of each digit
is determined by its position in a number.
The base, also called the radix of a number system is the number of symbols that the system contains. The decimal system
has ten symbols: 0,1,2,3,4,5,6,7,8,9. In other words, it has a base of 10. Each position in the decimal system is 10 times
more significant than the previous position. The numeric value of a decimal number is determined by multiplying each
digit of the number by the value of the position in which the digit appears and then adding the products. Thus the number
2734 is interpreted as
Here 4 is the least significant digit (LSD) and 2 is the most significant digit (MSD).
In general in a number system with a base or radix r, the digits used are from 0 to r-1 and the number can be represented
as
Equation (1) is for all integers and for the fractions (numbers between 0 and 1), the following equation holds.
Binary Numbers
The binary number has a radix of 2. As r = 2, only two digits are needed, and these are 0 and 1. Like the decimal system,
binary is a positional system, except that each bit position corresponds to a power of 2 instead of a power of 10. In digital
systems, the binary number system and other number systems closely related to it are used almost exclusively. Hence,
digital systems often provide conversion between decimal and binary numbers. The decimal value of a binary number can
be formed by multiplying each power of 2 by either 1 or 0 followed by adding the values together.
Example : The decimal equivalent of the binary number 101010.
In binary r bits can represent symbols. e.g. 3 bits can represent up to 8 symbols, 4 bits for 16 symbols etc. For N
symbols to be represented, the minimum number of bits required is the lowest integer 'r'' that satisfies the relationship.
Octal Numbers
Digital systems operate only on binary numbers. Since binary numbers are often very long, two shorthand notations, octal
and hexadecimal, are used for representing large binary numbers. Octal systems use a base or radix of 8. Thus it has digits
from 0 to 7 (r-1). As in the decimal and binary systems, the positional valued of each digit in a sequence of numbers is
fixed. Each position in an octal number is a power of 8, and each position is 8 times more significant than the previous
position.
Hexadecimal Numbers
The hexadecimal numbering system has a base of 16. There are 16 symbols. The decimal digits 0 to 9 are used as the first
ten digits as in the decimal system, followed by the letters A, B, C, D, E and F, which represent the values 10, 11,12,13,14
and 15 respectively. Table 1 shows the relationship between decimal, binary, octal and hexadecimal number systems.
Decimal Binary Octal Hexadecimal
0 0000 0 0
1 0001 1 1
2 0010 2 2
3 0011 3 3
4 0100 4 4
5 0101 5 5
6 0110 6 6
7 0111 7 7
8 1000 10 8
9 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F
Hexadecimal numbers are often used in describing the data in computer memory. A computer memory stores a large
number of words, each of which is a standard size collection of bits. An 8-bit word is known as a Byte. A hexadecimal
digit may be considered as half of a byte. Two hexadecimal digits constitute one byte, the rightmost 4 bits corresponding
to half a byte, and the leftmost 4 bits corresponding to the other half of the byte. Often a half-byte is called nibble.
If "word" size is n bits there are 2n possible bit patterns so only 2n possible distinct numbers can be represented. It
implies that all possible numbers cannot be represent and some of these bit patterns (half?) to represent negative numbers.
The negative numbers are generally represented with sign magnitude i.e. reserve one bit for the sign and the rest of bits
are interpreted directly as the number. For example in a 4 bit system, 0000 to 0111 can be used to positive numbers from
+0 to +2n-1 and represent 1000 to 1111 can be used for negative numbers from -0 to -2n-1. The two possible zero's
redundant and also it can be seen that such representations are arithmetically costly.
Another way to represent negative numbers are by radix and radix-1 complement (also called r's and (r-1)'s). For example
-k is represented as Rn -k. In the case of base 10 and corresponding 10's complement with n=2, 0 to 99 are the possible
numbers. In such a system, 0 to 49 is reserved for positive numbers and 50 to 99 are for positive numbers.
Examples:
+3 = +3
-3 = 10 2 -3 = 97
2's complement is a special case of complement representation. The negative number -k is equal to 2 n -k. In 4 bits
system, positive numbers 0 to 2n-1 is represented by 0000 to 0111 and negative numbers -2n-1 to -1 is represented by 1000
to 1111. Such a representation has only one zero and arithmetic is easier. To negate a number complement all bits and add
1
Example:
119 10 = 01110111 2
Complementing bits will result
10001000
+1 add 1
10001001
That is 10001001 2 = - 119 10
To verify that the value of the 8-bit number is still -5; value of 8-bit number
= -27 + 26 + 25 + 24 + 23 +2 +1
= -128 + 64 + 32 + 16 +8 +2+1
= -128 + 123 = -5
Similar to decimal number addition, two binary numbers are added by adding each pair of bits together with carry
propagation. An addition example is illustrated below:
X 190
Y 141
X + Y 331
Similar to addition, two binary numbers are subtracted by subtracting each pair of bits together with borrowing, where
needed. For example:
X 229
Y 46
X-Y 183
Overflow occurs if signs (MSBs) of both operands are the same and the sign of the result is different. Overflow can also
be detected if the carry in the sign position is different from the carry out of the sign position. Ignore carry out from MSB.
For converting a binary number to octal, the following two step procedure can be used.
1. Group the number of bits into 3's starting at least significant symbol. If the number of bits is not evenly divisible
by 3, then add 0's at the most significant end.
Examples:
Similarly for converting a binary number to hex, the following two step procedure can be used.
1. Group the number of bits into 4's starting at least significant symbol. If the number of bits is not evenly divisible
by 4, then add 0's at the most significant end.
2. Write the corresponding 1 hex digit for each group
Examples:
The hex to binary conversion is very simple; just write down the 4 bit binary code for each hexadecimal digit
Example:
Similarly for octal to binary conversion, write down the 8 bit binary code for each octal digit.
The hex to octal conversion can be carried out in 2 steps; first the hex to binary followed by the binary to octal. Similarly,
decimal to hex conversion is completed in 2 steps; first the decimal to binary and from binary to hex as described above.
Closure
If X and Y are in set (0, 1) then operations are also in set (0, 1)
Identity
Distributive
Complement
Note that for each property, one form is the dual of the other; (zeros to ones, ones to zeros, '.' operations to '+' operations,
'+' operations to '.' operations).
From the above postulates the following theorems could be derived.
Associative
Idempotence
Absorption
Simplification
Consensus
Adjacency
Demorgans
In general form
A set is a collection of objects (or elements) and for example a set Z {0, 1} means that Z is a set containing two elements
distinguished by the symbols 0 and 1. There are three primary operations AND , OR and NOT.
NOT
It is anary complement or inversion operation. Usually shown as over bar ( ), other forms are and
AND
Also known as the conjunction operation; output is true (1) only if all inputs are true. Algebraic operators are '.', '&', ' '
OR
Also known as the disjunction operation; output is true (1) if any input is true. Algebraic operators are '+', '|', ' '
AND and OR are called binary operations because they are defined on two operands X and Y. Not is called a unary
operation because it is defined on a single operand X. All of these operations are closed. That means if one applies the
operation to two elements in a set Z {0, 1}, the result will be always an element in the set B and not something else.
Like standard algebra, switching algebra operators have a precedence of evaluation. The following rules are useful in this
regard.
1. NOT operations have the highest precedence
2. AND operations are next
3. OR operations are lowest
4. Parentheses explicitly define the order of operator evaluation and it is a good practice to use parentheses
especially for situations which can cases doubt.
Note that in Boolean algebra the operators AND and OR are not linear group operations; so one cannot solve equations by
"adding to" of "multiplying" on both sides of the equal sign as is done with real, complex numbers in standard algebra.
UNIT-II
A K-map consists of a grid of squares, each square representing one canonical minterm
combination of the variables or their inverse. The map is arranged so that squares
representing minterms which differ by only one variable are adjacent both vertically and
horizontally. Therefore XY'Z' would be adjacent to X'Y'Z' and would also adjacent to XY'Z
and XYZ'.
Minimization Technique
2-Variable K-Map
In any K-Map, each square represents a minterm. Adjacent squares always differ by just
one literal (So that the unifying theorem may apply: X + X' = 1). For the 2-variable case
(e.g.: variables X, Y), the map can be drawn as below. Two variable map is the one which
has got only two variables as input.
Equivalent labeling
K-map needs not follow the ordering as shown in the figure above. What this means is that
we can change the position of m0, m1, m2, m3 of the above figure as shown in the two
figures below.
Position assignment is the same as the default k-maps positions. This is the one which we
will be using throughout this tutorial.
The K-map for a function is specified by putting a '1' in the square corresponding to a
minterm, a '0' otherwise.
In this example we have the truth table as input, and we have two output functions.
Generally we may have n output functions for m input variables. Since we have two output
functions, we need to draw two k-maps (i.e. one for each function). Truth table of 1 bit adder
is shown below. Draw the k-map for Carry and Sum as shown below.
X Y Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Grouping/Circling K-maps
The power of K-maps is in minimizing the terms, K-maps can be minimized with the help of
grouping the terms to form single terms. When forming groups of squares, observe/consider
the following:
Example - X'Y+XY
In this example we have the equation as input, and we have one output function. Draw the
k-map for function F with marking 1 for X'Y and XY position. Now combine two 1's as shown
in figure to form the single term. As you can see X and X' get canceled and only Y remains.
F=Y
Example - X'Y+XY+XY'
In this example we have the equation as input, and we have one output function. Draw the
k-map for function F with marking 1 for X'Y, XY and XY position. Now combine two 1's as
shown in figure to form the two single terms.
F=X+Y
3-Variable K-Map
There are 8 minterms for 3 variables (X, Y, Z). Therefore, there are 8 cells in a 3-variable K-
map. One important thing to note is that K-maps follow the gray code sequence, not the
binary one.
Using gray code arrangement ensures that minterms of adjacent cells differ by only ONE
literal. (Other arrangements which satisfy this criterion may also be used.)
Each cell in a 3-variable K-map has 3 adjacent neighbours. In general, each cell in an n-
variable K-map has n adjacent neighbours.
F = XYZ'+XYZ+X'YZ
F = XY + YZ
Example
F(X,Y,Z) = (1,3,4,5,6,7)
F=X+Z
4-Variable K-Map
There are 16 cells in a 4-variable (W, X, Y, Z); K-map as shown in the figure below.
There are 2 wrap-around: a horizontal wrap-around and a vertical wrap-around. Every cell
thus has 4 neighbours. For example, the cell corresponding to minterm m0 has neighbours
m1, m2, m4 and m8.
Example
F(W,X,Y,Z) = (1,5,12,13)
F = WY'Z + W'Y'Z
Example
F = W'XY' + WY
QUINE-McCLUSKEY MINIMIZATION
Quine-McCluskey minimization method uses the same theorem to produce the solution as
the K-map method, namely X(Y+Y')=X
Minimization Technique
The expression is represented in the canonical SOP form if not already in that form.
The function is converted into numeric notation.
The numbers are converted into binary form.
The minterms are arranged in a column divided into groups.
Begin with the minimization procedure.
o Each minterm of one group is compared with each minterm in the group
immediately below.
o Each time a number is found in one group which is the same as a number in
the group below except for one digit, the numbers pair is ticked and a new
composite is created.
o This composite number has the same number of digits as the numbers in the
pair except the digit different which is replaced by an "x".
The above procedure is repeated on the second column to generate a third column.
The next step is to identify the essential prime implicants, which can be done using a
prime implicant chart.
o Where a prime implicant covers a minterm, the intersection of the
corresponding row and column is marked with a cross.
o Those columns with only one cross identify the essential prime implicants. ->
These prime implicants must be in the final answer.
o The single crosses on a column are circled and all the crosses on the same
row are also circled, indicating that these crosses are covered by the prime
implicants selected.
o Once one cross on a column is circled, all the crosses on that column can be
circled since the minterm is now covered.
o If any non-essential prime implicant has all its crosses circled, the prime
implicant is redundant and need not be considered further.
Next, a selection must be made from the remaining nonessential prime implicants, by
considering how the non-circled crosses can be covered best.
o One generally would take those prime implicants which cover the greatest
number of crosses on their row.
o If all the crosses in one row also occur on another row which includes further
crosses, then the latter is said to dominate the former and can be selected.
o The dominated prime implicant can then be deleted.
Example
Find the minimal sum of products for the Boolean expression, f= (1,2,3,7,8,9,10,11,14,15),
using Quine-McCluskey method.
Firstly these minterms are represented in the binary form as shown in the table below. The
above binary representations are grouped into a number of sections in terms of the number
of 1's as shown in the table below.
Minterms U V W X
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
14 1 1 1 0
15 1 1 1 1
No of 1's Minterms U V W X
1 1 0 0 0 1
1 2 0 0 1 0
1 8 1 0 0 0
2 3 0 0 1 1
2 9 1 0 0 1
2 10 1 0 1 0
3 7 0 1 1 1
3 11 1 0 1 1
3 14 1 1 1 0
4 15 1 1 1 1
Any two numbers in these groups which differ from each other by only one variable can be
chosen and combined, to get 2-cell combination, as shown in the table below.
2-Cell combinations
Combinations U V W X
(1,3) 0 0 - 1
(1,9) - 0 0 1
(2,3) 0 0 1 -
(2,10) - 0 1 0
(8,9) 1 0 0 -
(8,10) 1 0 - 0
(3,7) 0 - 1 1
(3,11) - 0 1 1
(9,11) 1 0 - 1
(10,11) 1 0 1 -
(10,14) 1 - 1 0
(7,15) - 1 1 1
(11,15) 1 - 1 1
(14,15) 1 1 1 -
From the 2-cell combinations, one variable and dash in the same position can be combined
to form 4-cell combinations as shown in the figure below.
4-Cell combinations
Combinations U V W X
(1,3,9,11) - 0 - 1
(2,3,10,11) - 0 1 -
(8,9,10,11) 1 0 - -
(3,7,11,15) - - 1 1
(10,11,14,15) 1 - 1 -
The cells (1,3) and (9,11) form the same 4-cell combination as the cells (1,9) and (3,11).
The order in which the cells are placed in a combination does not have any effect. Thus the
(1,3,9,11) combination could be written as (1,9,3,11).
From above 4-cell combination table, the prime implicants table can be plotted as shown in
table below.
Prime
1 2 3 7 8 9 10 11 14 15
Implicants
(1,3,9,11) X - X - - X - X - -
(2,3,10,11) - X X - - - X X - -
(8,9,10,11) - - - - X X X X - -
(3,7,11,15) - - - - - - X X X X
- X X - X X - - - X -
The columns having only one cross mark correspond to essential prime implicants. A yellow
cross is used against every essential prime implicant. The prime implicants sum gives the
function in its minimal SOP form.
Combinational Logic
Introduction
Combinatorial Circuits are circuits which can be considered to have the following generic
structure.
Whenever the same set of inputs is fed in to a combinatorial circuit, the same outputs will be
generated. Such circuits are said to be stateless. Some simple combinational logic elements
that we have seen in previous sections are "Gates".
All the gates in the above figure have 2 inputs and one output; combinational elements
simplest form are "not" gate and "buffer" as shown in the figure below. They have only one
input and one output.
Decoders
A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into
coded outputs, where the input and output codes are different; e.g. n-to-2n, BCD decoders.
Enable inputs must be on for the decoder to function, otherwise its outputs assume a single
"disabled" output code word.
And AND gate can be used as the basic decoding element, because its output is HIGH only
when all its inputs are HIGH. For example, if the input binary number is 0110, then, to make
all the inputs to the AND gate HIGH, the two outer bits must be inverted using two inverters
as shown in figure below.
A binary decoder has n inputs and 2n outputs. Only one output is active at any one time,
corresponding to the input value. Figure below shows a representation of Binary n-to-2n
decoder
Example - 2-to-4 Binary Decoder
A 2 to 4 decoder consists of two inputs and four outputs, truth table and symbols of which is
shown below.
Truth Table
X Y F0 F1 F2 F3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
Symbol
To minimize the above truth table we may use kmap, but doing that you will realize that it is
a waste of time. One can directly write down the function for each of the outputs. Thus we
can draw the circuit as shown in figure below.
Circuit
Example - 3-to-8 Binary Decoder
A 3 to 8 decoder consists of three inputs and eight outputs, truth table and symbols of which
is shown below.
Truth Table
X Y Z F0 F1 F2 F3 F4 F5 F6 F7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Symbol
From the truth table we can draw the circuit diagram as shown in figure below.
Circuit
Implementing Functions Using Decoders
Equation
S(x, y, z) = (1,2,4,7)
C(x, y, z) = (3,5,6,7)
Truth Table
X Y Z C S
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
From the truth table we know the values for which the sum (s) is active and also the carry
(c) is active. Thus we have the equation as shown above and a circuit can be drawn as
shown below from the equation derived.
Circuit
Encoders
The simplest encoder is a 2n-to-n binary encoder, where it has only one of 2 n inputs = 1 and
the output is the n-bit binary number corresponding to the active input.
Example - Octal-to-Binary Encoder
Octal-to-Binary take 8 inputs and provides 3 outputs, thus doing the opposite of what the 3-
to-8 decoder does. At any one time, only one input line has a value of 1. The figure below
shows the truth table of an Octal-to-binary encoder.
Truth Table
I0 I1 I2 I3 I4 I5 I6 I7 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
For an 8-to-3 binary encoder with inputs I0-I7 the logic expressions of the outputs Y0-Y2
are:
Y0 = I1 + I3 + I5 + I7
Y1= I2 + I3 + I6 + I7
Y2 = I4 + I5 + I6 +I7
Based on the above equations, we can draw the circuit as shown below
Circuit
Example - Decimal-to-Binary Encoder
Decimal-to-Binary take 10 inputs and provides 4 outputs, thus doing the opposite of what
the 4-to-10 decoder does. At any one time, only one input line has a value of 1. The figure
below shows the truth table of a Decimal-to-binary encoder.
Truth Table
I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 Y3 Y2 Y1 Y0
1 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 0 0 0 1 0 0
0 0 0 0 0 1 0 0 0 0 0 1 0 1
0 0 0 0 0 0 1 0 0 0 0 1 1 0
0 0 0 0 0 0 0 1 0 0 0 1 1 1
0 0 0 0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 0 0 0 0 0 1 1 0 0 1
From the above truth table , we can derive the functions Y3, Y2, Y1 and Y0 as given below.
Y3 = I8 + I9
Y2 = I4 + I5 + I6 + I7
Y1 = I2 + I3 + I6 + I7
Y0 = I1 + I3 + I5 + I7 + I9
Priority Encoder
If we look carefully at the Encoder circuits that we got, we see the following limitations. If
more then two inputs are active simultaneously, the output is unpredictable or rather it is not
what we expect it to be.
This ambiguity is resolved if priority is established so that only one input is encoded, no
matter how many inputs are active at a given point of time.
The priority encoder includes a priority function. The operation of the priority encoder is such
that if two or more inputs are active at the same time, the input having the highest priority
will take precedence.
The truth table of a 4-input priority encoder is as shown below. The input D3 has the highest
priority, D2 has next highest priority, D0 has the lowest priority. This means output Y2 and
Y1 are 0 only when none of the inputs D1, D2, D3 are high and only D0 is high.
A 4 to 3 encoder consists of four inputs and three outputs, truth table and symbols of which
is shown below.
Truth Table
D3 D2 D1 D0 Y2 Y1 Y0
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 x 0 1 0
0 1 x x 0 1 1
1 x x x 1 0 0
Now that we have the truth table, we can draw the Kmaps as shown below.
Kmaps
From the Kmap we can draw the circuit as shown below. For Y2, we connect directly to D3.
We can apply the same logic to get higher order priority encoders.
Multiplexer
A multiplexer (MUX) is a digital switch which connects data from one of n sources to the
output. A number of select inputs determine which data source is connected to the output.
The block diagram of MUX with n data sources of b bits wide and s bits wide select line is
shown in below figure.
MUX acts like a digitally controlled multi-position switch where the binary code applied to the
select inputs controls the input source that will be switched on to the output as shown in the
figure below. At any given point of time only one input gets selected and is connected to
output, based on the select input signal.
The operation of a multiplexer can be better explained using a mechanical switch as shown
in the figure below. This rotary switch can touch any of the inputs, which is connected to the
output. As you can see at any given point of time only one input gets transferred to output.
A 2 to 1 line multiplexer is shown in figure below, each 2 input lines A to B is applied to one
input of an AND gate. Selection lines S are decoded to select a particular AND gate. The
truth table for the 2:1 mux is given in the table below.
Symbol
Truth Table
S Y
0 A
1 B
To derive the gate level implementation of 2:1 mux we need to have truth table as shown in
figure. And once we have the truth table, we can draw the K-map as shown in figure for all
the cases when Y is equal to '1'.
Combining the two 1' as shown in figure, we can drive the output y as shown below
Y = A.S' + B.S
Truth Table
B A S Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1
Kmap
Circuit
Symbol
Truth Table
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Circuit
Larger Multiplexers
Larger multiplexers can be constructed from smaller ones. An 8-to-1 multiplexer can be
constructed from smaller multiplexers as shown below.
Truth Table
S2 S1 S0 F
0 0 0 I0
0 0 1 I1
0 1 0 I2
0 1 1 I3
1 0 0 I4
1 0 1 I5
1 1 0 I6
1 1 1 I7
Circuit
De-multiplexers
They are digital switches which connect data from one input source to one of n outputs.
Usually implemented by using n-to-2n binary decoders where the decoder enable line is
used for data input of the de-multiplexer.
The figure below shows a de-multiplexer block diagram which has got s-bits-wide select
input, one b-bits-wide data input and n b-bits-wide outputs.
Symbol
Truth Table
S1 S0 F0 F1 F2 F3
0 0 D 0 0 0
0 1 0 D 0 0
1 0 0 0 D 0
1 1 0 0 0 D
Earlier we had seen that it is possible to implement Boolean functions using decoders. In
the same way it is also possible to implement Boolean functions using muxers and de-
muxers.
Express function in canonical sum-of-minterms form. Choose n-1 variables as inputs to mux
select lines. Construct the truth table for the function, but grouping inputs by selection line
values (i.e select lines as most significant inputs).
Determine multiplexer input line i values by comparing the remaining input variable and the
function F for the corresponding selection lines value i.
Implement the function F(X,Y,Z) = S(1,3,5,6) using an 8-to-1 mux. Connect the input
variables X, Y, Z to mux select lines. Mux data input lines 1, 3, 5, 6 that correspond to the
function minterms are connected to 1. The remaining mux data input lines 0, 2, 4, 7 are
connected to 0.
Implement the function F(X,Y,Z) = S(0,1,3,6) using a single 4-to-1 mux and an inverter. We
choose the two most significant inputs X, Y as mux select lines.
Truth Table
Circuit
We determine multiplexer input line i values by comparing the remaining input variable Z
and the function F for the corresponding selection lines value i
when XY=00 the function F is 1 (for both Z=0, Z=1) thus mux input0 = 1
when XY=01 the function F is Z thus mux input1 = Z
when XY=10 the function F is 0 (for both Z=0, Z=1) thus mux input2 = 0
when XY=11 the function F is Z' thus mux input3 = Z'
UNIT-III
Introduction
Digital electronics is classified into combinational logic and sequential logic. Combinational
logic output depends on the inputs levels, whereas sequential logic output depends on
stored levels and also the input levels.
The memory elements are devices capable of storing binary info. The binary info stored in
the memory elements at any given time defines the state of the sequential circuit. The input
and the present state of the memory element determines the output. Memory elements next
state is also a function of external inputs and present state. A sequential circuit is specified
by a time sequence of inputs, outputs, and internal states.
There are two types of sequential circuits. Their classification depends on the timing of their
signals:
This is a system whose outputs depend upon the order in which its input variables change
and can be affected at any instant of time.
Gate-type asynchronous systems are basically combinational circuits with feedback paths.
Because of the feedback among logic gates, the system may, at times, become unstable.
Consequently they are not often used.
A clock signal is a periodic square wave that indefinitely switches from 0 to 1 and from 1 to 0
at fixed intervals. Clock cycle time or clock period: the time interval between two
consecutive rising or falling edges of the clock.
Clock Frequency = 1 / clock cycle time (measured in cycles per second or Hz)
A sequential circuit as seen in the last page, is combinational logic with some feedback to maintain
its current value, like a memory cell. To understand the basics let's consider the basic feedback logic
circuit below, which is a simple NOT gate whose output is connected to its input. The effect is that
output oscillates between HIGH and LOW (i.e. 1 and 0). Oscillation frequency depends on gate
delay and wire delay. Assuming a wire delay of 0 and a gate delay of 10ns, then oscillation
frequency would be (on time + off time = 20ns) 50Mhz.
The basic idea of having the feedback is to store the value or hold the value, but in the
above circuit, output keeps toggling. We can overcome this problem with the circuit below,
which is basically cascading two inverters, so that the feedback is in-phase, thus avoids
toggling. The equivalent circuit is the same as having a buffer with its output connected to its
input.
But there is a problem here too: each gate output value is stable, but what will it be? Or in
other words buffer output can not be known. There is no way to tell. If we could know or set
the value we would have a simple 1-bit storage/memory element.
Asynchronous Circuits.
Synchronous Circuits.
As seen in last section, Latches and Flip-flops are one and the same with a slight
variation: Latches have level sensitive control signal input and Flip-flops have edge
sensitive control signal input. Flip-flops and latches which use this control signals are
called synchronous circuits. So if they don't use clock inputs, then they are called
asynchronous circuits.
RS Latch
RS latch have two inputs, S and R. S is called set and R is called reset. The S input is used
to produce HIGH on Q ( i.e. store binary 1 in flip-flop). The R input is used to produce LOW
on Q (i.e. store binary 0 in flip-flop). Q' is Q complementary output, so it always holds the
opposite value of Q. The output of the S-R latch depends on current as well as previous
inputs or state, and its state (value stored) can change as soon as its inputs change. The
circuit and the truth table of RS latch is shown below. (This circuit is as we saw in the last
page, but arranged to look beautiful :-) ).
S R Q Q+
0 0 0 0
0 0 1 1
0 1 X 0
1 0 X 1
1 1 X 0
The operation has to be analyzed with the 4 inputs combinations together with the 2
possible previous states.
The waveform below shows the operation of NOR gates based RS Latch.
It is possible to construct the RS latch using NAND gates (of course as seen in Logic gates
section). The only difference is that NAND is NOR gate dual form (Did I say that in Logic
gates section?). So in this case the R = 0 and S = 0 case becomes the invalid case. The
circuit and Truth table of RS latch using NAND is shown below.
S R Q Q+
1 1 0 0
1 1 1 1
0 1 X 0
1 0 X 1
0 0 X 1
If you look closely, there is no control signal (i.e. no clock and no enable), so this kind of
latches or flip-flops are called asynchronous logic elements. Since all the sequential circuits
are built around the RS latch, we will concentrate on synchronous circuits and not on
asynchronous circuits.
For synchronous flip-flops, we have special requirements for the inputs with respect to clock
signal input. They are
Setup Time: Minimum time period during which data must be stable before the clock
makes a valid transition. For example, for a posedge triggered flip-flop, with a setup
time of 2 ns, Input Data (i.e. R and S in the case of RS flip-flop) should be stable for
at least 2 ns before clock makes transition from 0 to 1.
Hold Time: Minimum time period during which data must be stable after the clock
has made a valid transition. For example, for a posedge triggered flip-flop, with a hold
time of 1 ns. Input Data (i.e. R and S in the case of RS flip-flop) should be stable for
at least 1 ns after clock has made transition from 0 to 1.
If data makes transition within this setup window and before the hold window, then
the flip-flop output is not predictable, and flip-flop enters what is known as meta
stable state. In this state flip-flop output oscillates between 0 and 1. It takes some
time for the flip-flop to settle down. The whole process is called metastability. You
could refer to tidbits section to know more information on this topic.
The waveform below shows input S (R is not shown), and CLK and output Q (Q' is not shown) for a
SR posedge flip-flop.
D Latch
The RS latch seen earlier contains ambiguous state; to eliminate this condition we can
ensure that S and R are never equal. This is done by connecting S and R together with an
inverter. Thus we have D Latch: the same as the RS latch, with the only difference that
there is only one input, instead of two (R and S). This input is called D or Data input. D latch
is called D transparent latch for the reasons explained earlier. Delay flip-flop or delay latch is
another name used. Below is the truth table and circuit of D latch.
D Q Q+
1 X 1
0 X 0
Below is the D latch waveform, which is similar to the RS latch one, but with R removed.
JK Latch
The ambiguous state output in the RS latch was eliminated in the D latch by joining the
inputs with an inverter. But the D latch has a single input. JK latch is similar to RS latch in
that it has 2 inputs J and K as shown figure below. The ambiguous state has been
eliminated here: when both inputs are high, output toggles. The only difference we see here
is output feedback to inputs, which is not there in the RS latch.
J K Q
1 1 0
1 1 1
1 0 1
0 1 0
T Latch
When the two inputs of JK latch are shorted, a T Latch is formed. It is called T latch as,
when input is held HIGH, output toggles.
T Q Q+
1 0 1
1 1 0
0 1 1
0 0 0
All sequential circuits that we have seen in the last few pages have a problem (All level
sensitive sequential circuits have this problem). Before the enable input changes state from
HIGH to LOW (assuming HIGH is ON and LOW is OFF state), if inputs changes, then
another state transition occurs for the same enable pulse. This sort of multiple transition
problem is called racing.
If we make the sequential element sensitive to edges, instead of levels, we can overcome
this problem, as input is evaluated only during enable/clock edges.
In the figure above there are two latches, the first latch on the left is called master latch and
the one on the right is called slave latch. Master latch is positively clocked and slave latch is
negatively clocked.
UNIT - IV
We saw in the combinational circuits section how to design a combinational circuit from the
given problem. We convert the problem into a truth table, then draw K-map for the truth
table, and then finally draw the gate level circuit for the problem. Similarly we have a flow for
the sequential circuit design. The steps are given below.
Looks like sequential circuit design flow is very much the same as for combinational circuit.
State Diagram
The state diagram is constructed using all the states of the sequential circuit in question. It
builds up the relationship between various states and also shows how inputs affect the
states.
To ease the following of the tutorial, let's consider designing the 2 bit up counter (Binary
counter is one which counts a binary sequence) using the T flip-flop.
Q1 Q0 Q1+ Q0+ T1 T0
0 0 0 1 0 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 0 0 1 1
K-map
The K-map is the same as the combinational circuits K-map. Only difference: we draw K-map for the
inputs i.e. T1 and T0 in the above table. From the table we deduct that we don't need to draw K-map
for T0, as it is high for all the state combinations. But for T1 we need to draw the K-map as shown
below, using SOP.
Circuit
There is nothing special in drawing the circuit, it is the same as any circuit drawing from K-
map output. Below is the circuit of 2-bit up counter using the T flip-flop.
UNIT-V
Definition 1 A finite state machine is a 5-tuple, (S, A,R, _, s0) where S is a finite set of states, A is a
finite alphabet, R is a finite alphabet of responses and _ is a transition function such that for any
state,s 2 S and symbol a 2 A, _(s, a) = (s0, r0) indicates the next state, s0 and the output symbol, r0 2
R.
s0 is the initial state.
Definition 2 A recogniser is a special kind of finite state machine in which the output alphabet
contains two special symbols: accept and reject. The machine responds to any finite sequence of
input
symbols, terminated with a special end of input symbol (_), with either accept or reject.
Mealy model
The Mealy model is shown in Figure 5. It requires only 5 states. The states: Idle, Cooking
and Cooking Interrupted for that model (see Figure 6, Figure 7 and Figure 8) illustrate its
features. Other states can be studied in the provided file MWaveOven_Mealy.fsm. All
activities are done as Input actions, which means that actions essential for a state must be
performed in all states which have a transition to that state. The Timer must be now started
in both states: Idle and Cooking Interrupted.
This may be considered as a disadvantage: the functioning becomes a bit confusing.
Minimization of FSM:
INPUT OUTPUT
ASM Method
The ASM method is composed of the following steps:
ASM Chart
An ASM chart consists of an interconnection of three types of basic elements: states,
condition checks, and conditional outputs. An ASM state, represented as a rectangle,
corresponds to one state of a regular state diagram or finite state machine. The name of the
state is indicated outside the box in the top left corner. The Moore type outputs are listed
inside the box.
State box
An ASM condition check, indicated by a diamond with one input and two outputs (for true
and false), is used to conditionally transfer between two states or between a state and a
conditional output. The decision box contains the stated condition expression to be tested,
the expression contains one or more inputs of the FSM.
Decision box
Decision box: A diamond indicates that the stated condition expression is to be tested and
the exit path is to be chosen accordingly. The condition expression contains one or more
inputs to the FSM.
Conditional output box: An oval denotes the output signals that are of Mealy type. These
outputs depend not only on the state but also the inputs to the FSM.
Datapath
Once the desired operation of a circuit has been described using RTL operations, the
datapath components may be derived. Every unique variable that is assigned a value in the
RTL program can be implemented as a register. Depending on the functional operation
performed when assigning a value to a variable, the register for that variable may be
implemented as a straightforward register, a shift register, a counter, or a register preceded
by a combinational logic block. The combinational logic block associated with a register may
implement an adder, subtracter, multiplexer, or some other type of combinational logic
function.
Binary multiplier:
A binary multiplier is a electronic circuit used in digital electronics, such as a computer, to
multiply two binary numbers. It is built using binary adders.
Theory
Using long multiplication, a product of two N-bit numbers can be expressed as the sum of N
N-bit partial products, which are then added to produce a 2N-bit product.
a3 a2 a1 a0
× b3 b2 b1 b0
p7 p6 p5 p4 p3 p2 p1 p0
The partial products can be trivially computed from the fact that a i × bj = ai AND bj. The
complexity of the multiplier is in adding the partial products.
Implementation
There are several ways to implement a binary multiplier.
Multiple adders
Partial products are added in pairs using binary adders until the entire product is computed
similar to multiplying large numbers by hand. This requires N-1 adders.
Example:
2 Bit by 2 Bit Binary Multiplier
Using a 4 Bit + 4 Bit Adder
A simple adder
1-bit adder
"Ander"
A 1x4 bit Ander
4-bit Adder
Using 4 1-bit adders
1. Inhibit circuits
4. Programming
16. University previous Question papers
17. Question Bank
UNIT- I
2. a. Draw the NAND logic diagram that implements the complement of the function.
F(A,B,C,D) = ∑ (0,1,2,3,4,8,9,12)
iii.(ABC)’(A + B + C)’
a.ABC+A’B+ABC’
b.(BC’+A’D)(AB’+CD’)
c.x’yz+xz
d.xy+x(wz+wz’)
a.AB+A(B+C)+B’(B+D)
b.A+B+A‘B’C
c.A’B+A’BC’+A’BCD+A’BC’D’E
d.ABEF+ABE’F’+A’B’EF
a.(xy+z) (y+xz)
b.B’D+A’D+BD
a.AB’C+AB’D+A’B
b.A’B’C+ABC?+A’B’C’D
c.ABCD+ABC’D’+A’B’CD
.d. AB+ABC’
a.B’C’D+(B+C+D)’+B’C’D’E
b.AB+(AC)’+(AB+C)
c.A’B’C’+A’BC’+AB’C’+ABC’
d.AB+(AC)’+AB’C
a. AB’C+AB’D+A’B’
b.A’B’C+ABC’+A’B’C’D
a.Commutative
b.Associative
c.Distributive
13. Find the complement of the following Boolean functions and reduce them to
i.( a + b )’ ( a’ + b’ )’
ii.y(wz’ + wz) + xy
17. a.State and prove Boolean laws related to OR, AND, NOT gates
UNIT - II
a.F1 = ∑m(2,4,6,8,12)
b.F2 =∑m(1,3,6,7,9,10)
c.F3 = ∑m(1,3,4,5,6,9,12,14)
d.F4 =∑m(2,4,8)
19. Prove the following identities by writing the truth tables for both sides:
b.(X.Y.Z)’ = X’ + Y’ +Z’
c.X.(X +Y) = X
d.X + X’Y = X + Y
a.Boolean function
2.(a) Design a logic circuit Using minimum number of Basic gates for the following Boolean
expression.
(b) Reduce the following expression using Karnaugh map. (B’ A’ + A’B + AB’ )
(c) Find the out put of a four variable K-map, when all the cells are filled with logic LOW.
4.(a) Reduce the following function using K- map and implement it in AOI logic as
well as NOR logic F= ∑M(0, 1, 2, 3, 4, 7)
(b) What do you mean by K-map? Name its advantages and disadvantages
5.(a) Reduce the following function using K- map and implement it in AOI logic as
well as NOR logic F= ∑M(0, 1, 2, 3, 4, 7)
(b) What do you mean by K-map? Name its advantages and disadvantages
6.For the truth table given below , find the minimal expression for the out put (Y) using K-map
A B C D Y A B C D Y A B C D Y
0 0 0 0 1 0 1 1 0 1 1 0 1 1 0
0 0 0 1 0 0 1 1 1 0 1 1 0 0 1
0 0 1 0 1 1 0 0 0 0 1 1 0 1 0
0 0 1 1 0 1 0 0 1 1 1 1 1 0 1
0 1 0 0 1 1 0 1 0 0 1 1 1 1 0
0 1 0 1 1
7.(a) What is a cell of a K-map? What is meant by pair, a quad, and an octet of a map and how many
variables are eliminated?
(b) Reduce the following function using K- map and implement it using NAND
Logic. F= ∑m(0, 2, 3, 4, 5, 6, )
8.(a) What do you mean by don’t care combinations?
(b) What you mean by min terms and max terms of Boolean expressions.
10.Simplify the following Boolean expressions using K-map and implement them using NOR gates:
1. Explain the type of Hazard if any in the EXCLUSIVE - OR circuit made by five NAND gates
and the EXCLUSIVE ?OR circuit made by four NAND gates as shown in figure have any static
Hazard or Dynamic Hazard?
2.
2. A circuit receives a 4-bit Excess-3 code. Design a minimal circuit to detect the decimal numbers 0,
1, 4, 6, 7 and 8.
3. (a) Implement the following Boolean function using a 8:1 multiplexer considering ‘C’ as the input
and A,B,C as selection lines. F(ABCD) = AB’ +BD+ B’CD’
4. (a) Design a Excess-3 adder using 4-bit parallel binary adder and logic gates.
5. (a) Design a combinational logic to subtract one bit from the other. Draw the logic diagram using
NAND and NOR gates.
(b) Using 4 MSI circuits construct a binary parallel adder to add two 16-bit binary numbers. Label all
carries between the MSI circuits.
9. (a) Implement the following Boolean functions using decoder and OR gates:
F1(A,B,C,D) = ∑(2,4,7,9)
F2(A,B,C,D) = ∑(10,13,14,15)
10.(a) What is decoder? Construct 3*8 decoder using logic gates and truth table.
UNIT- III
1. Classify the required circuits into synchronous, asynchronous, pulse mode with suitable
examples.
2. Draw the circuit of JK master slave flip-flop with active high clear & active low preset &
explain.
3. Draw the circuit of master slave RS flip-flop & explain its operation with the help of truth table.
4. Discuss the disadvantages due to level triggering.
5. Convert T flip-flop to D flip-flop.
6. What is the advantage of choosing D flip flop in sequential circuits. Explain with an example.
UNIT- IV
7. Compare synchronous & asynchronous circuits
8. Using a shift register how do you obtain a circular shift.
9. Design & implement 2 bit comparator using logic gates.
10. Draw the block diagram of a 4-bit serial adder & explain its operation.
11. Design of MOD- N Synchrounous Counter.
12. Design ripple and Johnson ring counter.
UNIT- V
16. Design the ASM chart, data path circuit, control circuit using multiplexers for binary
multiplier.
17. Design a synchronous sequential circuit which goes through the following
states1,3,5,3,6,1,3,5.
18. Design control circuit for ASM chart using D flip flop & decoder.
19. Draw the portion of an ASM chart that specifies the conditional operation to increment the
register R during the state T1 & transfer to the state T2, if control inputs z & y are 1 & 0
respectively.
20. Design a synchronous sequential circuit that works as a decade counter.
18. Assignment topics
UNIT-I
1) (a) Convert the following (258)10 = ( ? ) 2 = ( ? ) 8 = ( ? ) 16
F = A’B’C+ABC+A’BC+ABC’+A’B’C’
4) What are Universal Gates? Realize all the logic gates using NAND.
5) A receiver with even parity Hamming code is received the data as 101110110100.
8) What are universal gates? Realize all logic gates using NOR Gates.
UNIT-II
1). Simplify the following expressions using K-Map and realize with NAND gates. F =
πM (1, 2, 3, 8, 9, 10, 11, 14). πd (7,15)
2). Design the logic circuit that coverts 4 bit binary data to gray code.
3) Simplify the following expressions using K-Map and realize with NAND gates.
F = ∑m (0,2,5,9,15) + ∑d(6,7,8,10,12,13)
5) Simplify the following expressions using K-Map and realize with NOR gates. F =
AB’C + A’B’C + A’BC +AB’C’ + A’B’C’.
6) Design and explain 3 to 8 decoder.
7) Minimize the following function using tabular method and find the essentials.
UNIT-III
1. What is the drawback of JK Flip Flop. How is it eliminated in Master Slave J-K Flip-Flop. Explain
with state diagram and characteristic table.
UNIT-IV
1. Design a modulo - 10 ripple counter and explain its timing diagram.
2. Design a Mod-6 asynchronous counter using J-K Flip Flops.
3. Differentiate between Combinational and Sequential Circuits with examples.
4. Design a Decade counter using SR Flip Flops.
Unit – V
2. Find the equivalence partition and reduced table for the given state machine.
P.S N.S. , O/P
X=0 X=1
A B,0 E,0
B E,0 D,0
C D,1 A,0
D B,1 E,0
E C,0 D,0
3. Find the minimal cover table for the given machine using Merger graph.
P.S N.S,Z
00 01 11 10
A A,0 --,-- E,-- B,1
B E, -- C,1 B,-- --,--
C --,-- B,0 --,1 D,0
D A,0 --,-- F,1 B,--
E B,0 --,-- B,0 --,--
F --,-- C,1 --,0 C,1
6. Construct the compatibility graph and obtain the minimal cover table for given machine.
PS NS,Z
X1 X2
A --,-- F,0
B B,0 C,0
C E,0 A,1
D B,0 D,0
E F,1 D,0
F A,0 --,--
7. Obtain set of maximal compatibles for machine shown using Merger table.
PS NS,Z
X1 X2
A E,0 B,0
B F,0 A,0
C E,- C,0
D F,1 D,0
E C,1 C,0
F D,- B,0
9. Draw an ASM chart and state table for 2 bit UP/DOWN Counter having control input M, if M = 1;
UP Counting & M = 0; DOWN Counting. The circuit has to generate output 1 whenever the count
becomes minimum or maximum.
23 22 21 20
8421
Now put the binary number underneath the other numbers and multiply the top number
by the number beneath it and put the answer underneath the other 2 with + between
each number and add the bottom row together to get your final answer.
8421
1101
8+4+0+1 = 13
11012 -> 13
161 160
16 1
1F
16+F = 16 + 15 = 31
1F16 -> 31
81 80
81
25
16+5 = 21
158 -> 21
TUTORIAL - II
The most common way of subtracting binary numbers is done by first taking the
second value (the number to be subtracted) and apply what is known as two's
complement, this is done in two steps:
By applying these steps you are effectively turning the value into a negative number,
and as when dealing with decimal numbers, if you add a negative number to a positive
number then you are effectively subtracting to the same value.
NOTE: When subtracting binary values it is important to maintain the same amount of
digits for each number, even if it means placing zeroes to the left of the value to make
up the digits, for instance, in our example we have added a zero to the left of the value
1100110 to make the amount of numerals up to 8 (one byte) 01100110.
Now we need to add 11101011 + 10011010, however when you do the addition you
always disregard the last carry, so our example would be:
which gives us 10000101, now we can convert this value into decimal, which gives
13310
Example 2
Example 3
TUTORIAL - III
Subtracting the numbers using 9’s complement & 10’s
complement
To subtract a decimal number y from another number x using the method of
complements, the ten's complement of y (nines' complement plus 1) is added to x.
Typically, the nines' complement of y is first obtained by determining the complement
of each digit. The complement of a decimal digit in the nines' complement system is
the number that must be added to it to produce 9. The complement of 3 is 6, the
complement of 7 is 2, and so on. Given a subtraction problem:
873 (x)
- 218 (y)
The nines' complement of y (218) is 781. In this case, because y is three digits long,
this is the same as subtracting y from 999.
873 (x)
=====
1654
=====
654
The first "1" digit is then dropped, in an effort to keep the same digits as the original,
giving 654. This is not yet correct. We have essentially added 999 to the equation in
the first step. Then we remove 1000 when we drop the first 1 in the answer (above) this
will make the answer we get one less than the correct answer. To fix this, we must add
1 to the answer.
654
+1
====
655
If the subtrahend has fewer digits than the minuend, leading zeros must be added
which will become leading nines when the complement is taken. For example:
48032 (x)
- 391 (y)
becomes the sum:
48032 (x)
=======
147640
Dropping the "1" yields 47640, and adding the dropped "1" to 47640 gives the answer:
47641.
Binary addition
Adding binary numbers is a very simple task, and very similar to the longhand addition
of decimal numbers. As with decimal numbers, you start by adding the bits (digits) one
column, or place weight, at a time, from right to left. Unlike decimal addition, there is
little to memorize in the way of rules for the addition of binary bits:
0+0=0
1+0=1
0+1=1
1 + 1 = 10
1 + 1 + 1 = 11
Just as with decimal addition, when the sum in one column is a two-bit (two-digit)
number, the least significant figure is written as part of the total sum and the most
significant figure is "carried" to the next left column. Consider the following examples:
The addition problem on the left did not require any bits to be carried, since the sum of
bits in each column was either 1 or 0, not 10 or 11. In the other two problems, there
definitely were bits to be carried, but the process of addition is still quite simple.
TUTORIAL-IV
Output
The AND gate is a logic gate A B
Q
that gives an output of '1' only
when all of its inputs are 0 0 0
AND
'1'. Thus, its output is '0'
Gate 0 1 0
whenever at least one of its
inputs is '0'. Mathematically, Q 1 0 0
= A · B.
1 1 1
Output
A B
The OR gate is a logic gate that Q
gives an output of '0' only when 0 0 0
all of its inputs are '0'. Thus, its
OR Gate
output is '1' whenever at least 0 1 1
one of its inputs is '1'.
Mathematically, Q = A + B. 1 0 1
1 1 1
Output
The NAND gate is an AND A B
Q
gate with a NOT gate at its end.
Thus, for the same combination 0 0 1
NAND
of inputs, the output of a
Gate 0 1 1
NAND gate will be opposite
that of an AND gate. 1 0 1
Mathematically, Q = A · B.
1 1 0
1 0 0
1 1 0
Output
A B
Q
The EXOR gate (for 'EXclusive 0 0 0
EXOR OR' gate) is a logic gate that
Gate gives an output of '1' when only 0 1 1
one of its inputs is '1'.
1 0 1
1 1 0
There are several kinds of logic gates, each one of which performs a specific function. These are the:
1) AND gate; 2) OR gate; 3) NOT gate; 4) NAND gate; 5) NOR gate; and 6) EXOR gate. Table 1
above presents these and their characteristics.
TUTORIAL - V
Minimization of Boolean expressions
1. Z = f(A,B,C) = + B + AB + AC
= (B + ) + A(C + B )
= B+ + AC + AB
=B+ + AC
Z = f(A,B,C,D) = B+B + BC + A
= B + B(C + ) + (B + A ) using B (twice) T4a
= B(1 + +A
= A(B + D) + AC
= AB + AD + AC
Step1: Represent the Minterm needs to be considered for the function by ‘1’
F1 = (x + y + z)( x + y’ + z’ )( x’ + y + z)
F = (x + yz + x)(x + yz + y)
= (x + yz)(x + y +yz)
TUTORIAL - VI
Duality principle
Duality Principle states that every algebraic expression deducible from the
postulates of Boolean algebra remains valid if the operators and identity elements
are interchanged.
Postulates a and b
Postulate 2 x+0=x x•1=x
Postulate 3, Commutative x + y = y + x xy = yx
Postulate 4, Distributive x (y + z) = xy x + yz = (x + y)(x
Postulate 5 x+ +xzx’ = 1 x+ •z)x’ = 0
Theorems a and b
Theore a b
Theorem m 1 x+x=x x•x = x
Theorem 2 x+1=1 x•0=0
Theorem 3, ( x’ )’ = x
Involution4,
Theorem x + (y + z) = (x + x • (y• z) = (x • y)
Associative
Theorem 5, y) +
(x + y)’
z = x’y’ • z = x’ + y’
(x•y)’
DeMorgan6,
Theorem x + xy = x x (x + y) = x
Absorption
Prove: (A*B)*( A + B) = 0
=0 by identity theorem
(A*B)*( A + B) = 0
Prove: (A*B) + ( A + B) =1
=1 by identity
theorem
(A*B) + ( A + B) =1
Since (A*B)*( A + B) = 0, and (A*B) + ( A + B) =1,
x + xy = x
x + xy = x•1 + xy = x(y+1) =x •1 = x
Proof of Theorem 6(b)
x(x+y) = x By duality
TUTORIAL-VIII
The first step in using K-Maps to simplify this expression is to use the SOP numbering
to represent these as 0’s and 1’s. The negated variable is written as a 0, the plain as a
1. Thus, this function is represented as 011, 101, 110, and 111.
The next step is to notice the physical adjacencies. We group adjacent 1’s into
“rectangular” groupings of 2, 4, or 8 boxes. Here there are no groupings of 4 boxes in
the form or a rectangle, so we group by two’s. There are three such groupings, labeled
A, B, and C.
the next example is to simplify F(A, B, C) = (3, 5). We shall consider use of K-Maps
to simplify POS expressions, but for now the solution is to convert the expression to
the SOP form F(A, B, C) = (0, 1, 2, 4, 6, 7). We could write each of the six product
terms, but the easiest solution is to write the numbers as binary: 000, 001, 010, 100,
110, and 111.
The trouble with K-Maps is that the technique is designed to be used only with
expressions in canonical form. In order to use the K-Map method we need to convert
the term WX’Y’ to its equivalent WX’Y’Z’ + WX’Y’Z, thus obtaining a
four-term canonical SOP.
Before actually doing the K-Map, we first apply simple algebraic simplification to F.
= W’X’Y’(Z’ + Z) + WX’Y’
= W’X’Y’ + WX’Y’
Now that we see where we need to go with the tool, we draw the four-variable K-Map.
Before we attempt to simplify F2, we note that it is a very good candidate for
simplification. Compare the first term 000 to each of the following three terms. The
term 000 differs from the term 001 in exactly one position. The same applies for
comparison to the other two terms. Any two terms that differ in exactly one position
can be combined in a simplification.
= (A + B)(A + C)(B + C)
A B C F
0 0 0 1
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 0
1 1 1 1
We plot two 0’s for the POS representation of the function – one at 010 and one at 110.
The two are combined to get –10, which translates to (B’ + C).
We close the discussion of SOP K-Maps with the example at right, which shows that
the four corners of the square are adjacent and can be grouped into a 2 by 2 square.
This K-Map represents the terms 0000, 0010, 1000, 1010 or W’X’Y’Z’ +
W’X’YZ’ +
WX’Y’Z’ + WX’YZ’. The values in the square that are constant are X = 0 and
Z = 0, thus the expression simplifies to X’Z’.
TUTORIAL - IX
Finding prime implicants of Boolean functions and determining the
essentials
where
This means that P = > F with respect to the natural ordering of the Boolean space. For
instance, the function
f(x,y,z,w) = xy + yz + w
is implied by xy, by xyz, by xyzw, by w and many others; these are the implicants of f.
The process of removing literals from a Boolean term is called expanding the term.
Expanding by one literal doubles the number of input combinations for which the term
is true (in binary Boolean algebra). Using the example function above, we may expand
xyz to xy or to yz without changing the cover of f. [1]
The sum of all prime implicants of a Boolean function is called the complete sum of
that function.
The diagram below illustrates the correspondence between the Karnaugh map and the
truth table for the general case of a two variable problem.
The values inside the squares are copied from the output column of the truth table,
therefore there is one square in the map for every row in the truth table. Around the
edge of the Karnaugh map are the values of the two input variable. A is along the top
and B is down the left hand side. The diagram below explains this:
The values around the edge of the map can be thought of as coordinates. So as an
example, the square on the top right hand corner of the map in the above diagram has
coordinates A=1 and B=0. This square corresponds to the row in the truth table where
A=1 and B=0 and F=1. Note that the value in the F column represents a particular
function to which the Karnaugh map corresponds.
Example 1:
Note that values of the input variables form the rows and columns. That is the
logic values of the variables A and B (with one denoting true form and zero
denoting false form) form the head of the rows and columns respectively.
Bear in mind that the above map is a one dimensional type which can be used to
simplify an expression in two variables.
There is a two-dimensional map that can be used for up to four variables, and a
three-dimensional map for up to six variables.
Z = A + AB
Z = A( + B)
Z=A
Example 2:
Pairs of 1's are grouped as shown above, and the simplified answer is obtained by
using the following steps:
Note that two groups can be formed for the example given above, bearing in mind that
the largest rectangular clusters that can be made consist of two 1s. Notice that a 1 can
belong to more than one group.
The first group labelled I, consists of two 1s which correspond to A = 0, B = 0 and A =
1, B = 0. Put in another way, all squares in this example that correspond to the area of
the map where B = 0 contains 1s, independent of the value of A. So when B = 0 the
output is 1. The expression of the output will contain the term
For group labelled II corresponds to the area of the map where A = 0. The group can
therefore be defined as . This implies that when A = 0 the output is 1. The output is
therefore 1 whenever B = 0 and A = 0
Hence the simplified answer is Z = +
TUTORIAL-X
1 1
COMPARATORS 2
4-Bit magnitude comparator
BCD adder
Binary to Gray code converter
G2 B2
B1
G1
B0
G0
TUTORIAL-XI
JK Flip-flop
Both the S and the R inputs of the previous SR bistable have now been
replaced by two inputs called the J and K inputs, respectively after its
inventor Jack Kilby. Then this equates to: J = S and K = R.
The two 2-input AND gates of the gated SR bistable have now been
replaced by two 3-input NAND gates with the third input of each gate
connected to the outputs at Q and Q. This cross coupling of the SR flip-flop
allows the previously invalid condition of S = "1" and R = "1" state to be
used to produce a "toggle action" as the two inputs are now interlocked. If
the circuit is "SET" the J input is inhibited by the "0" status of Q through
the lower NAND gate. If the circuit is "RESET" the K input is inhibited by
the "0" status of Q through the upper NAND gate. As Q and Q are always
different we can use them to control the input. When both inputs J and K
are equal to logic "1", the JK flip-flop toggles as shown in the following
truth table.
0 0 0 0
Memory
same as
no change
for the 0 0 0 1
SR Latch
0 1 1 0
Reset Q » 0
0 1 0 1
1 0 0 1
Set Q » 1
1 0 1 0
1 1 0 1
toggle
Toggle
action
1 1 1 0
Latches
This latch is called SR-latch, which stands for set and reset.
Flip-flops
Latches are asynchronous, which means that the output changes very soon
after the input changes. Most computers today, on the other hand, are
synchronous, which means that the outputs of all the sequential circuits
change simultaneously to the rhythm of a global clock signal.
The leftmost SR-latch is called the master and the rightmost is called the
slave.
The input signals J and K are connected to the gated "master" SR flip-flop
which "locks" the input condition while the clock (Clk) input is "HIGH" at
logic level "1". As the clock input of the "slave" flip-flop is the inverse
(complement) of the "master" clock input, the "slave" SR flip-flop does not
toggle. The outputs from the "master" flip-flop are only "seen" by the gated
"slave" flip-flop when the clock input goes "LOW" to logic level "0". When
the clock is "LOW", the outputs from the "master" flip-flop are latched and
any additional changes to its inputs are ignored. The gated "slave" flip-flop
now responds to the state of its inputs passed over by the "master" section.
Then on the "Low-to-High" transition of the clock pulse the inputs of the
"master" flip-flop are fed through to the gated inputs of the "slave" flip-flop
and on the "High-to-Low" transition the same inputs are reflected on the
output of the "slave" making this type of flip-flop edge or pulse-triggered.
Then, the circuit accepts input data when the clock signal is "HIGH", and
passes the data to the output on the falling-edge of the clock signal. In other
words, the Master-Slave JK Flip-flop is a "Synchronous" device as it only
passes data with the timing of the clock signal..
TUTORIAL-XII
Mealy Machine
The state diagram of the Mealy machine lists the inputs with their
associated outputs on state transitions arcs.
The value stated on the arrows for Mealy machine is of the form
Zi/Xi where
The state transition arrows of Moore machine are labeled with the
input value that triggers such transition.
Design a gated latch circuit with two inputs, G (gate) and D (data), and one output Q. The
gated latch is a memory element that accepts the value of D when G = 1 and retains this
value after G goes to 0. Once G = 0, a change in D does not change the value of the
output Q.
Solution
State table
State Inputs Output
D G Q
a 0 1 0
b 1 1 1
c 0 0 0
d 1 0 0
e 1 0 1
f 0 0 1
Primitive Flow table
Informal Merging
Formal Merging
Compatible Pairs
Maximal Compatibles
Reduced Table
Logic Diagram
Draw the diagram of mealy type FSM for serial adder
A serial adder is a digital circuit that can add any two arbitrarily large numbers using a
single full adder. Just as humans, the serial adder operates on one pair of bits/digits at a
time. When you add the two 4–digit numbers 7852 and 1974, for example, you typically
start by adding 2 plus 4 equal 6, then 5 plus 7 equal 12 (place 2 and carry the 1), and so
on. Similarly, given the two 4–bit numbers 1011 and 0110, the serial adder starts by
adding 1 plus 0 equal to 1, and then 1 plus 1 equal to 10 (place 0 and carry the 1), and so
on.
For a general demonstration, both a human person and a serial adder follow the same
sequential method. Given two 4–figure numbers A3A2A1A0 and B3B2B1B0, we add two
figures at a time starting with the least significant pair, and so on. First, we do A 0 + B0 =
S0. Second, we do A1 + B1 + carry = S1, and so on; where the S figures represent the sum:
A + B = S.
Notice that in the operation A1 + B1 + carry = S1, carry is not one of the inputs being
added; the inputs being added are A1 and B1. Furthermore, the value of carry does not
depend on the inputs A1 and B1. Carry is simply a given condition, the consequence of
something that happened in the past; namely, A0 + B0.
Therefore, if we were tasked to “build a circuit that can add any two binary numbers
using the sequential method that humans use,” we would treat the carry variable as a state
variable. (In computer engineering talk, any circuit with one or more state variables is
referred to as a finite state machine.)
Since the carry variable can either be 1 or 0, we say that our circuit will be a two states
machine. When the circuit is in the state where carry = 0, the relationship between the
inputs A and B and the output S is such that: if AB = 00 then S = 0; if AB = 01 then S =
1; if AB = 10 then S = 1; and if AB = 11 then S = 0. When the circuit is in the state where
carry = 1, it also follows that: if AB = 00 then S = 1; if AB = 01 then S = 0; if AB = 10
then S = 0; and if AB = 11 then S = 1. We illustrate these relationships in the state
diagram in Figure 1.
Figure 1: State transition diagram for serial adder
FSM
To present the information in the state diagram in table form, we re-label the carry
variable Z (Z for carry–out and z for carry–in) for convenience. We show the tabulated
information in Table 1 below.
From a finite state machine analysis perspective, we say z is the present state of the
machine because z is presently available as one of the inputs to the full adder; Z on the
other hand is the next state because it is one of the variables we are solving for — given
the inputs A, B and the present state (or the carry–in) z.
z Z S
0 0 0 0 1 0 1 1 0
1 0 1 1 1 1 0 0 1
z/AB 00 01 10 11 z/AB 00 01 10 11
0 0 0 0 1 0 0 1 1 0
1 0 1 1 1 1 1 0 0 1
Table 2: K-maps for the next state variable Z and the output variable S
S = A B z
Z=A•B+A•z+B•z
The reason these Boolean expressions look similar to the full adder equation is because
they are the full adder expression. Here z is the carry–in signal and Z is the carry–out
signal. Since the carry–out of the full adder becomes the carry–in to the full adder on the
next operation, we us a D flipflop to save the carry signal. We use a D flipflop because
we need the data in Z to pass to z intact for the next operation. Any other flipflop will
return some z that may or may not be equal to Z.
TUTORIAL-XIII
Nowadays, both up and down counters are incorporated into single IC that is
fully programmable to count in both an "Up" and a "Down" direction from any
preset value producing a complete Bidirectional Counter chip. Common chips
available are the 74HC190 4-bit BCD decade Up/Down counter, the 74F569 is a
fully synchronous Up/Down binary counter and the CMOS 4029 4-bit
Synchronous Up/Down counter.
Shall be provided later, as this has a revised syllabus and the course content is to be studied in
details.
22. Group discussion topics
WEBSITES
1. en.wikipedia.org/wiki/digital-electronics
2. www.encyclopedia.com/doc/1G2-3401200206.html
3. www.worldscibooks.com/engineering/3453.html
JOURNALS
1. Integration of an online digital logic design lab for it education
2. Conference on information technology education ( formerly CITC) archive
3. Proceedings of the 9th ACM SIGITE conference on information technology
education
B. Teaching Evaluation
Quality control department conducts online feedback, two times in the semester.
25.Students list