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SHAMBHUNATH INSTITUTE OF ENGINEERING & TECHNOLOGY, ALLAHABAD

FINAL SESSIONAL EXAMINATION SCHEDULE


M.TECH (ELECTRONICS AND COMMUNICATION ENGG.)
SPECIALIZATION (VLSI DESIGN)
(SESSION 2015-16)

Dated: 16.04.2016

SEM Wednesday Friday 29.04.2016 Monday Wednesday


27.04.2016 02.05.2016 04.05.2016
09:30 - 12:00 09:30 - 12:00 hrs 09:30 - 12:00 hrs 09:30 - 12:00
hrs hrs
Analog VLSI Design Low Power VLSI Algorithm for VLSI Designing with ASICs
nd
2 (VD-201) Design Design Automation (VD 024)
SEM (VD 202) (VD 203)

Kamal Pandey
(M.Tech. Co-ordinator)

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