A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with

Two-Level Redundancy

Yu-Jen Huang, Da-Ming Chang, and Jin-Fu Li∗

Advanced Reliable Systems (ARES) Laboratory
Department of Electrical Engineering
National Central University
Jhongli, Taiwan 320

Abstract

With the increasing demand of memories in system-on-chip (SOC) designs, developing efficient yield-
improvement techniques for memories becomes an important issue. Built-in self-repair (BISR) technique has
become a popular method for repairing defective embedded memories. To allocate redundancy efficiently, built-
in redundancy-analysis (BIRA) function is usually needed for designing a BISR scheme. This paper presents an
efficient BIRA scheme for RAMs with two-level redundancy (i.e., spare rows, spare columns, and spare words).
Experimental results show that the repair rate of the proposed BIRA scheme approximates to that of the exhaus-
tive search with the same redundancy organization. Furthermore, the repair rate of the proposed BIRA scheme
with two-level redundancy is higher than that of the exhaustive search scheme with one-level redundancy (i.e.,
spare rows and spare columns). The area cost of the proposed BIRA scheme is low. For example, the hardware
overhead of the proposed BIRA scheme for an 8K×64-bit RAM with three spare rows, three spare columns, and
two spare words is only about 2%.

1: Introduction
More and more system-on-chip (SOC) designs are memory-dominated designs. Among various types of cores
in SOCs, memory cores often are the densest part and designed with aggressive design rules. Thus memory yield
usually dominates the yield of SOCs. Efficient defect-tolerance techniques are imperative for large memories.
Adding redundancy is one popular and widely used defect-tolerance technique for memories. However, memories
in SOCs usually have different sizes and types. Also, accessibility of embedded memories is usually very poor.
These cause that repairing embedded memories with external equipments becomes very difficult and high cost.
Therefore, built-in self-repair (BISR) technique is gaining popular for repairing embedded memories [1]. One of
key components in BISR designs is the built-in redundancy-analysis (BIRA) component.
Redundancy analysis is not a new problem in memory repair. Many software-based redundancy analysis algo-
rithms have been reported, such as [2–4]. However, these algorithms are performed in automatic test equipment
and they cannot be realized with embedded circuits in reasonable hardware cost. Recently, various BISR and
BIRA schemes have been proposed in [5–15]. In [5], a BISR scheme for embedded SRAMs with spare columns
was proposed. However, redundancy allocation circuit is not needed since the repairable SRAMs is equipped
with 1D redundancy. In [6], a BISR memory with spare words was proposed. The BISR scheme consists of
memory BIST logic, wrapper logic (including comparing logic and spare words), and fuse boxes. Again, re-
dundancy analysis is not needed since the memory only has 1D redundancy. In the Alpha 21264, a redundancy
analyzer for a RAM with 1×1 redundancies per memory block was implemented [7]. To achieve optimal uti-
lization of redundancy, a comprehensive real-time exhaustive search test and analysis (CRESTA) scheme is used
to allocate redundancy for bit-oriented memories [8]. However, the hardware cost for realizing the CRESTA
scheme is very high. In [12], the authors extended the CRESTA scheme to support the redundancy allocation
for word-oriented memories. In [10], three BIRA algorithms for bit-oriented memories were presented. How-
ever, if these algorithms are extended for repairing word-oriented memories, the area cost is larger since every
bit in the local bitmap is replaced by a word. In [14], a BIRA scheme for word-oriented memories with 2D
∗
This work was supported in part by National Science Council, Taiwan, R.O.C., under contract NSC 94-2215-E-008-021 and MOEA,
Taiwan, R.O.C., under contract 96-EC-17-A-01-S1-002.

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 redundancy using 1D local bitmap is reported. This BIRA scheme can execute 2D redundancy allocation with
low area cost. In [13], a BIRA scheme for word-oriented memories with 2D redundancy is introduced. In [9], a
BIRA scheme for a RAM with divided-word-line structure was reported. In [15], a reconfigurable BISR scheme
is used to support multiple repairable RAMs in SOCs. According to the report of ITRS 2005, however, more
complicated redundancy architectures are needed for memory repair in nanometer process [16]. When the mem-
ory redundancy architecture becomes more complex, it will be difficult to implement the redundancy analysis
with a limited amount of logic. Thus efficient BIRA schemes are needed for nanometer-scale memories with
complicated redundancy architectures.
This paper proposes an efficient BIRA scheme for RAMs with two-level redundancy (i.e., spare rows, spare
columns, and spare words). Simulation results show that the repair rate of the proposed BIRA scheme for
an 8K×32-bit memory with one spare row, one spare column, and two spare words is much higher than the
repair rate of the exhaustive search scheme for RAMs with two spare rows and one spare column. Thus the
proposed BIRA scheme with two-level redundancy can achieve high repair rate with low area cost of redundancy.
Moreover, the area cost of the proposed BIRA scheme is low, it is only about 2% for an 8K×64-bit memory with
three spare rows, three spare columns, and two spare words.

2: Two-Level Redundancy Organization

A fail memory chip may have the following fault types: single-bit faults, row twin-bit faults, column twin-bit
faults, cluster faults, faulty rows, faulty columns, etc. Typically, the number of faulty rows or faulty columns
is small. To optimize the repair efficiency with the lowest area cost, we propose a BIRA scheme based on the
proposed two-level redundancy organization: spare rows (SRs), spare columns (SCs), and spare words (SWs).
Figure 1 depicts an example of the two-level redundancy organization. The spare row is used to replace a defective
row; the spare column is used to replace a defective column; the spare word is used to replace a defective word.

SR

SC
SW

Figure 1. Example of the two-level redundancy organization.

Spare rows and spare columns can be intrusively designed with the memory. However, spare words are difficult
to be intruded into the memory. We subsequently introduce two possible implementation approaches for spare
words. One approach is to use a small memory for spare words. The other is to design spare words with random
logics [6]. Figure 2(a) shows the conceptual block diagram for the implementation of spare words using a small
memory. As the figure shows, a content addressable memory (CAM) is used to store the faulty word addresses
sent from the BIRA circuit. The CAM parallel compares the input address with the stored faulty addresses while
the RAM is operated at mission mode. Once the input address is the same as one of the stored faulty addresses,
the CAM issues a hit signal and the the hit signal controls the multiplexer to switch the IOs to the small RAM.
Consider an 8K×64-bit RAM with 4 spare words. The access time for the RAM and the small RAM (for spare
words) is 2.15ns and 1.35ns, where Artisan memory compiler using 0.18μm technology is used to generated the
RAMs. Thus the small RAM cannot cause additional performance penalty in the repairable RAM.
Figure 2(b) shows the conceptual block diagram for the implementation of spare words using random logics
[6]. One spare word consists of one address register, one data register, and comparing logic. The address register
stores the faulty address and the data register stores the data. As Fig. 2(b) shows, the function of comparing
logic (CL) is to compare the input address with the faulty address stored in Addr Reg (address register). While
the RAM is operated at mission mode, the input address is compared with the faulty address. The comparing
result is used for the enable signal for the Read and Write control signals. If the RAM performs the Write
operation, the data input is broadcasted to the RAM and data registers. However, whether the data is written into

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 the corresponding data register or not depends on the Write enable (WE) signal of the data register. Similarly, if
the RAM performs Read operation, whether the Data out is connected to the Data Reg or RAM depends on the
Read enable (RE) signal. The speed of the spare word is higher than the access time of RAM. So the spare word
implemented with random logics also cannot cause additional performance penalty in the repairable RAM. The
ratio of area cost of the spare words using random logics to the memory under repair can be estimated by the
equation 0.2×NSW % [6], where NSW denotes the number of spare words. The area cost for implementing spare
words using small RAM will be discussed in Sec. 4.
Read

Address
FA Comp
Addr Reg &
CAM Small RE
RAM
Write
Address &
IOs CL
R/W RAM WE
DI Reg out Data
Data Reg out
RAM
out
(a) (b)

Figure 2. Implementation of spare words using (a) a small RAM and (b) random logics [6].

3: Proposed BIRA Scheme

To increase the repair efficiency, a BIRA scheme needs to collect certain amount of fault information, such
that the BIRA can allocate appropriate redundancies to replace the corresponding defective elements. Most of
BIRA schemes use local bitmap to collect the fault information [10–15]. In this paper, the proposed BIRA
scheme performs the redundancy allocation based on a compressed local bitmap to reduce the area cost of BIRA
circuit. Figure 3 depicts an example of the local bitmap. As Fig. 3 shows, when a faulty word is detected, the
corresponding faulty row and column addresses are stored in the row address register (RAR) and column address
register (CAR). Also, the Hamming syndromes of detected faulty words in the same column are stored in the
corresponding Hamming syndrome register (HSR) by performing bit-wise OR operation [14]. The Hamming
syndrome is defined as the modulo-2 sum of the fault-free data and the output data from the memory [17]. The
length of a Hamming syndrome is the number of bits of a word. Instead of a HSR is used to store the Hamming
syndrome for each pair of RAR and CAR, only a two-bit status register is used to represent the status of the
corresponding Hamming syndrome. Thus the local bitmap is compressed and the area cost of the compressed
local bitmap is small. However, the compressed local bitmap will cause some information loss. So the BIRA
algorithm must be able to make up this drawback. A two-bit status register is used to store the status of each
detected faulty word. Three possible states of the two-bit status register are (0,0), (1,0), and (1,1), where (0,0)
denotes the corresponding RAR and CAR without faulty information; (1,0) denotes the corresponding faulty
word only with one faulty bit; (1,1) denotes the corresponding faulty word with more than two faulty bits. The
width of each RAR and CAR equals the width of the row and column address. The number of RAR and CAR is
the same as the number of spare rows and spare columns.

CAR CAR CAR

Status Register
RAR
RAR
RAR
HSR HSR HSR

Figure 3. Example of a compressed local bitmap.

3.1: BIRA Algorithm

Subsequently, we describe the proposed redundancy analysis algorithm based on the compressed bitmap. The
proposed redundancy analysis algorithm consists of two-phase redundancy allocation procedure. Phase-1 and
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 Phase-2 redundancy allocation procedures are executed before and after the BIST is completed, respectively.
Before describing the complete procedure, we first explain four major rules used for redundancy allocation. The
four redundancy allocation rules are briefly described as follows.
Rule 1: If the row address of a detected faulty word with multiple faulty bits is the same as that of a stored
faulty word with multiple faulty bits and the column address of the detected faulty word is different from that of
the stored faulty word, then allocate a spare row to replace the faulty row with the row address of the detected
faulty word. Also, if the column addresses of any faulty words stored in the bitmap are the same as the column
addresses of the faulty words located at the repaired row, then allocate spare words to repair these faulty words.
It is required since the compressed bitmap results in the problem of undistinguished HSRs of the faulty words
in the same column. For example, consider a compressed local bitmap has faulty information in (R0,C0), (R0,
C1), and (R1,C0) as shown in Fig. 4(a). Subsequently, if a faulty word having multiple faulty bits with address
(R1,C2) is detected, the faulty row R1 is repaired with an available spare row. The HSR0 includes the Hamming
syndromes of the faulty words (R0,C0) and (R1,C0). This causes that individual Hamming syndrome of the two
faulty words cannot be distinguished. Therefore, the faulty word (R0,C0) must also be repaired by an available
spare word.
Rule 2: If a faulty word with single faulty bit is detected. Before storing the faulty word in the bitmap, the
proposed BIRA scheme compares its column address and the Hamming syndrome with those stored in the bitmap.
If its column address and Hamming syndrome are the same as those of a faulty word stored in the bitmap, allocate
a spare column to repair the faulty column with the column address of the defected faulty word. If the column
addresses or Hamming syndromes are different, the HSR is updated by performing bit-wise OR operation of the
original data of HSR and the corresponding status register are set. For example, consider a compressed local
bitmap has faulty information in (R0,C0) and the corresponding status register is (1,0) as depicted in Fig. 4(b).
Subsequently, if a faulty word (R2,C0) with single faulty bit is detected and its Hamming syndrome is the same
as the data stored in HSR0, the BIRA allocates an available spare column to replace the corresponding faulty
column. If its Hamming syndrome is different from the data stored in HSR0, the Hamming syndrome is stored
in the HSR0 by bit-wise OR operation and then the status register of (R2,C0) is set to (1,0).

C0 C1 C2 C0 C1 C2
R0 1 0 1 0 0 0 R0 1 0 1 1 0 0
R1 1 1 0 0 1 1 R1 0 0 0 0 1 0
R2 0 0 0 0 0 0 R2 1 0 0 0 0 0

HSR0 HSR1 HSR2 HSR0 HSR1 HSR2

(a) (b)

Figure 4. Samples of bitmap status while (a) Rule 1 and (b) Rule 2 are performed.

Rule 3: If the bitmap is full (i.e., either RARs or CARs are full; or both RARs and CARs are full) and there are
single faulty words in the bitmap, allocate spare words or spare rows to repair these single faulty words. A single
faulty word is defined as a faulty word in the bitmap and no faulty word exists in the row and the column where
the faulty word located. For example, the faulty word (R1,C1) as shown in Fig. 5(a) is a single faulty word in
the bitmap. Then the proposed BIRA scheme allocates an available spare word or spare row to replace the faulty
word.
Rule 4: If the bitmap is full and no single faulty word exists, allocate spare columns to repair the faulty words
located in the columns which HSRs has only one 1. As the Fig. 5(b) shows, four faulty words are stored in the
bitmap and the bitmap is full. In the first row, two faulty words exist but only one faulty word (R0,C2) with
multiple faulty bits. So the faulty row cannot be repaired using Rule 1. In the second column, the Hamming
syndromes of the two faulty word are different since they cannot be repaired using Rule 2. Also no single faulty
words exists in the bitmap. Therefore the proposed BIRA scheme performs Rule 4. As Fig. 5(b) shows, only the
HSR0 has one 1. Thus the BIRA algorithm allocates an available spare column to repair the faulty word (R0,C0).
Figure 6 shows the Phase-1 redundancy allocation procedure of the proposed BIRA algorithm. Once the BIST
detects a fault (i.e., Fault en=1), the BIRA algorithm checks whether the detected faulty word is a faulty word
with multiple faulty bits (MFBW) or is a faulty word with single faulty bit (SFBW). If the detected faulty word
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 C0 C1 C2 C0 C1 C2
R0 1 0 0 0 1 0 R0 1 0 0 0 1 1
R1 0 0 1 1 0 0 R1 0 0 1 0 0 0
R2 0 0 0 0 0 0 R2 0 0 1 0 0 0
HSR0 HSR1 HSR2 HSR0 HSR1 HSR2
(a) (b)

Figure 5. Samples of bitmap status while (a) Rule 3 and (b) Rule 4 are performed.

is MFBW, the BIRA checks whether the status of the bitmap meets the condition of Rule 1 or not. Then three
possible conditions will occur. First, if meet, available spare row (NSR ) and spare words (NSW ) are used to replace
the corresponding faulty elements. Then return to perform the BIST. Second, if the condition does not meet Rule
1 or NSR and NSW are exhausted and the bitmap is full, the BIRA algorithm checks whether the row address or
the column address of the detected faulty word is the same as any one of the row address or the column address
stored in the bitmap. If yes, the detected faulty word is stored in the bitmap. If no, the memory is unrepairable.
Third, if not meet or available spare rows and spare words are exhausted and the bitmap is not full, the faulty word
is stored in the bitmap. If the faulty word is stored and the bitmap is full, the BIRA algorithm checks whether the
status of the bitmap meets Rule 3 or not. If meet, the BIRA performs redundancy allocation procedure according
to Rule 3 and returns to perform BIST. If not meet, the BIRA checks whether the status of the bitmap meets
Rule 4 or not. If not meet, the BIRA return to perform BIST. If meet, the BIRA performs redundancy allocation
according to Rule 4. Then check whether the bitmap is still full.
On the contrary, if the detected faulty word is a SFBW, the BIRA algorithm checks whether the status of the
bitmap meets Rule 2 or not. If meet, the BIRA algorithm allocates the redundancy according to Rule 2. If not
meet or available spare column (NSC ) is exhausted, the BIRA algorithm checks whether the row address or the
column address of the detected faulty word is the same as that of the faulty words stored in the bitmap. If yes,
the detected faulty word is stored in the bitmap. If no, the memory is unrepairable.

Fault_en&Test_done
BIST
Fault_en

MFBW or SFBW
MFBW SFBW
Match&N SR,NSW>0 Match&N SC >0
Rule 1 MF&(Match|N SR,NSW=0) Rule 2

MF&(Match|N SR,NSW=0)
MF&(Match|N SC =0)
MF&(Match|N SC =0)
Store the fault
Same row or
same column?
MF
Map full
No Yes
MF
Match&N SR,NSW>0
Rule 3
Unrepairable Store the fault
Match|N SR,NSW=0

Rule 4
Match Match&N SC>0

Figure 6. Phase-1 redundancy allocation procedure of the proposed BIRA.

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 Once the test procedure is completed (i.e., Test done=1), Phase-2 redundancy allocation procedure of the
proposed BIRA algorithm is executed. The BIRA scheme first checks if the local bitmap is empty. If the
bitmap is empty, the analysis is completed and the memory is repairable. Otherwise, the proposed BIRA scheme
performs Rule 3 and Rule 4 to repair the faulty words. If the BIRA algorithm allocates redundancies to replace
the faulty words in the bitmap using Rule 3 and Rule 4 and available spare rows and spare words are exhausted,
the BIRA algorithm exports the Hamming syndromes in HSRs. Then the BIRA algorithm identifies the positions
of the faulty bits in these HSRs and repairs these faulty bits using available spare columns. If the number of faulty
bits is larger than the number of available spare columns, the memory is unrepairable. Otherwise the memory is
repairable.
3.2: Implementation of BIRA Circuit

Figure 7 shows the block diagram of the BIRA circuit. The BIRA circuit consists of a Syndrome Indicator, a
compressed Bitmap, an FSM, and a Repaired Address Register. The Syndrome Indicator can check the number
of faulty bits in the detected Hamming syndrome. For example, if the number of faulty bits in the Hamming
syndrome is 1 or larger than 1, the Syndrome Indicator will set the MFBW or SFBW flag to 1, respectively. The
FSM performs the redundancy allocation procedure of the proposed BIRA algorithm. It also coordinates the
interaction of the other blocks. So the FSM can be regarded as a controller for the BIRA circuit. The compressed
Bitmap accumulates the information of detected faulty words. Then if the Bitmap is full, it sets the flag of bitmap
full. The faulty information of each detected faulty word will first be compared with the information stored in
the Bitmap. This can check whether the detected faulty word has been stored in the Bitmap or not. The Bitmap
will update its content according to the control signals from the FSM. For example, if the FSM determines to use
one available spare row to repair one defective row, information of the corresponding row of the Bitmap storing
the fault information of the defective row must be cleared. That is, the corresponding CAR, RAR, HSR, and the
status registers must be set to all-0 state. The Repaired Address Register stores the repaired addresses determined
by the FSM. Once the BIRA process is completed, the addresses stored in the Repaired Address Register are
exported to the reconfiguration circuit of the memory under repair. Then the memory repair is completed.
As Fig. 7 shows, the BIRA circuit has seven IO ports. The input ports consist of BIRA en, Fault en, Test done,
Syndrome, and Faulty addr. The outputs signals are Hold and Unrepair. The BIRA en signal is used to enable
the BIRA circuit. If the BIST circuit detects a fault, the BIST is held and the Fault en is asserted. Then the BIRA
circuit will handle the information of the detected faulty word. Once the BIRA undergoes the corresponding
redundancy allocation procedure, the BIRA asserts the Hold signal which resumes the BIST circuit to test the
memory. The input ports Syndrome and Faulty Addr are buses. The Syndrome and Faulty Addr are used to
transport the Hamming syndrome and the address of the detected faulty word to the BIRA circuit. If the BIST has
completed the test procedure, the Test done is asserted. Also, if the BIRA circuit has completed the redundancy
allocation, the Unrepair signal is used to indicate whether the memory is repairable or not.

BIRA_en
Fault_en Bitmap FSM Hold
Test_done
Unrepair
Repaired
Syndrome Syndrome
Address
Faulty_addr Indicator Register

Figure 7. Block diagram of the proposed BIRA.

4: Experimental Results
We first evaluate the efficiency of the proposed BIRA scheme with the repair rate. The repair rate is defined
as the ratio of the number of repaired memories to the number of defective memories [10]. We implemented a
simulator to evaluate the repair rates of the proposed redundancy analysis algorithm and the exhaustive search
redundancy analysis algorithm. The simulator is implemented with the principle which is similar to that reported
in [18]. Table 1 shows comparison results of the repair rates of the redundancy analysis algorithm using exhaus-
tive search (denoted with Opt) and ours. In Table 1, NSR , NSC , and NSW denote the number of available spare
rows, spare columns, and spare words, respectively. Two memory configurations with different fault distributions

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 are simulated. The sample number of simulated memory cores is 500. The maximum number of injected faulty
defects is 10. The injected fault types in each memory cores are different. As Table 1 shows, Case 1 and Case
2 denote that the memory configurations are 128×32×64-bit and 64×128×32-bit, respectively. Also, the fault
distributions for Case 1 and Case 2 are different. The fault distribution in Case 1 is (10% faulty columns, 10%
row twin-bit faults, 10% column twin-bit faults, and 70% single cell faults) and in Case 2 is (10% faulty rows,
10% faulty columns, 10% row twin-bit faults, 10% column twin-bit faults, 10% row four-bit faults, and 10%
column four-bit faults, and 40% single cell faults). A row (column) twin-bit fault denotes two adjacent faulty
cells in a row (column). As the table shows, the repair rate of the proposed redundancy algorithm approximates
to that of the exhaustive search redundancy analysis algorithm for all the simulated redundancy configurations.

Table 1. Comparison results of repair rate for the exhaustive algorithm (Opt) and ours.
Case 1 Case 2
(NSR ,NSC ,NSW ) Opt Ours Opt Ours
(1,1,2) 87.2% 86.6% 88.2% 87.2%
(1,2,2) 93.2% 93.2% 94.6% 93.6%
(1,3,2) 97.4% 96.8% 97.4% 96.8%
(2,1,2) 93.4% 93.2% 94.2% 93.8%
(2,2,2) 97.0% 96.0% 98.0% 97.2%
(2,3,2) 99.4% 98.8% 99.6% 99.6%
(3,1,2) 97.2% 97.0% 97.2% 97.2%
(3,2,2) 99.4% 98.9% 99.6% 99.6%
(3,3,2) 99.8% 99.8% 99.8% 99.8%

Subsequently, we demonstrate another advantage of the proposed BIRA scheme with two-level redundancy.
Tables 2 and 3 show the comparison results of the repair rates of the Opt and Ours for different redundancy
configurations. In these tables, Δ denotes the difference of the repair rate of Ours and the repair rate of Opt.
Also, the first column and the second column show the two-level redundancy configurations (spare rows, spare
columns, and spare words) and the repair rate for the proposed BIRA scheme. The third column and fourth
column show the one-level redundancy configurations (spare rows and spare columns) for the Opt. As Table 2
shows, if one spare word is used for the two-level redundancy, the proposed BIRA scheme can achieve almost
the same repair rate as the Opt using lower redundancy cost. For example, if two spare rows, one spare column,
and one spare word are used, the repair rate of the proposed BIRA scheme is about 87.0%. If two spare rows
and one spare column is used for the optimal analysis algorithm, the repair rate is about 64.8%. The difference
between the two algorithm is higher than 22.0%. If three spare rows and one spare column are used for the Opt,
the repair rate of Opt is about 87.2% which is approximated to the repair rate of Ours. However, the Opt uses
larger redundancy cost to achieve the repair rate, since the area cost of one spare row is usually larger than that
of one spare word.

Table 2. Repair rate of the proposed algorithm with one spare word and Opt.
(NSR ,NSC ,NSW ) Ours (NSR ,NSC ) Opt Δ
(1,1) 45.0% +18.4%
(1,1,1) 63.4% (2,1) 64.8% -1.4%
(3,1) 86.6% -23.2%
(1,2) 63.4% +23.6%
(1,2,1) 87.0% (2,2) 87.2% -0.2%
(3,2) 93.8% -6.8%
(1,3) 87.0% +6.4%
(1,3,1) 93.4% (2,3) 93.8% -0.4%
(3,3) 98.0% -3.6%
(2,1,1) 87.0% (2,1) 64.8% +22.2%
(3,1) 86.6% +0.4%
(2,2,1) 94.0% (2,2) 87.2% +2.2%
(3,2) 93.8% +0.2%
(2,3,1) 97.0% (2,3) 93.8% +3.2%
(3,3) 98.0% -1.0%

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 Table 3. Comparison results of repair rates of Ours and Opt.
(NSR ,NSC ,NSW ) Ours (NSR ,NSC ) Opt Δ
(1,1) 45.6% +41.0%
(1,1,2) 86.6% (2,1) 64.6% +22.0%
(3,1) 87.6% -1.0%
(1,2) 63.4% +29.8%
(1,2,2) 93.2% (2,2) 87.4% +5.8%
(3,2) 93.2% 0.0%
(1,3) 88.0% +9.2%
(1,3,2) 97.2% (2,3) 94.2% +3.0%
(3,3) 97.8% -0.6%
(2,1,2) 93.6% (2,1) 64.6% +29.0%
(3,1) 87.6% +6.0%
(2,2,2) 96.8% (2,2) 87.4% +9.4%
(3,2) 93.2% +3.6%
(2,3,2) 99.0% (2,3) 94.2% +4.8%
(3,3) 97.8% +1.2%

Table 3 also shows this advantage, if two spare words are used, the proposed BIRA scheme can achieve higher
repair rate with lower area cost of redundancy. For example, if one spare row, one spare column, and two spare
words are used for the proposed BIRA scheme, the repair rate is about 86.6%. However, if two spare rows and
one spare column are used for the Opt, the repair rate is about 64.6%. Apparently, the repair rate of the proposed
BIRA scheme is larger than that of Opt. Also, the redundancy cost for the proposed BIRA scheme is smaller than
that for the Opt, since the area cost of two spare words is usually smaller than that of one spare row. Note that
the repair rates of Opt shown in Tables 2 and 3 are different for the same redundancy configuration. This is the
difference caused by the random defect injection. Moreover, if we compare the repair rates of Ours in Tables 2
and 3, we can see that the increment of the repair rate is very large with the increment of one additional spare
word. For example, the repair rate of Ours for the redundancy configuration (1,1,1) and (1,1,2) is 63.4% and
86.6%, respectively. The increment of repair rate is 23.2% with only one additional spare word.
We also designed and synthesized the proposed BIRA scheme with TSMC 0.18μm standard cell library. The
BIRA circuit mainly consists of a Bitmap, an FSM, a Repaired Address Register, and a Syndrome Indicator. For
an 8K×64-bit RAM with 3 spare rows, 3 spare columns, and 2 spare words, the number of gates of the proposed
BIRA scheme is about 6088. The ratio of the area of the BIRA circuit to the area of the RAM is only about 2%.
Finally, we summarize the area cost for implementing the spare words using small memory. Table 4 sum-
marizes the area cost of redundancies. The targeted memory configuration is 8K×64-bit with 512 rows and 16
columns and the word length is 64 bits. The area is 2.891mm2 .The spare rows, spare columns, and spare words
are generated by the Artisan memory compiler based on 0.18μm technology. Since the minimal size of the
memory generated by the compiler is 4 words. Therefore, the area of 2 spare words is estimated as half of the
area of 4 spare words. We compare the area cost of redundancies based on the redundancy configurations which
have almost the same repair rate according to the Table 3. For example, the redundancy configurations (1,1,2)
and (3,1) have almost the same repair rate for Ours and Opt. As Table 4 shows, if spare words are used, the
redundancy area is smaller. For example, if one spare row, one spare column, and two spare words are used, the
area is 0.360mm2 . If three spare rows and one spare column are used, the area is 0.403mm2 . Thus the proposed
BIRA scheme with two-level redundancy can achieve good repair rate with small redundancy cost.

Table 4. Area cost of redundancies implemented with small memories.

(NSR ,NSC ,NSW ) Area (mm2 ) Gate counts Area cost (NSR ,NSC ) Area (mm2 ) Gate counts Area cost
(1,1,2) 0.360 36075 12.45% (3,1) 0.403 40383 13.94%
(1,2,2) 0.552 55315 19.09% (3,2) 0.595 59624 20.58%
(1,3,2) 0.751 75257 25.98% (3,3) 0.794 79565 27.46%
(2,1,2) 0.408 40885 14.11% (4,1) 0.409 40985 14.15%
(3,3,2) 0.804 80568 27.81% (5,3) 0.806 80768 27.88%
(1,1,4) 0.370 37077 12.80% (5,1) 0.415 41586 13.45%
(1,2,4) 0.562 56317 19.44% (5,2) 0.607 60827 21.00%

Proceedings of the 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06)
0-7695-2706-X/06 $20.00 © 2006 8
 5: Conclusions
We have presented an efficient BIRA scheme for RAMs with two-level redundancy. Experimental results show
that the proposed BIRA scheme can achieve very high repair rate. The repair rate of the proposed BIRA scheme
approximates that of the redundancy analysis algorithm using exhaustive search under the same redundancy
configurations. On the other hand, the repair rate of the proposed BIRA scheme even is higher than that of the
redundancy analysis algorithm using exhaustive search scheme with one-level redundancy. Thus the proposed
BIRA scheme with two-level redundancy can achieve high repair rate with low area cost of redundancy. We also
have realized the proposed BIRA scheme with TSMC 0.18μm standard cell library. Results show that the area
cost of the proposed BIRA scheme for an 8K×64-bit RAM is only about 2%.

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Proceedings of the 21st IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT'06)
0-7695-2706-X/06 $20.00 © 2006 9