Test Compression and Logic BIST at Your Fingertips

Shianling Wu, Laung-Terng (L.-T.) Wang, Jin Woo Cho, Zhigang Jiang, and Boryau Sheu
SynTest Technologies, Inc.

Abstract ATE
Test Responses
This paper describes two Design-For-Test (DFT) methods
that provide flexibility in order to achieve desired test cost Pass/Fail Comparator
reduction goal using embedded scan compression and
Logic Built-In Self-Test (BIST). In some applications, one Expected Responses
method can be used in conjunction with the other. Test Patterns VirtualScan
Inputs
VirtualScan SI1 ... SIm
Circuit
1. Introduction
Broadcaster
While test data volume and test application time are key Full-Scan s10 s11 s12 s13 ... sm0 sm1 sm2 sm3
cost metrics in test economics, when investing in DFT, Circuit
one must study end-to-end impact from the baseline: the ...
IC’s. The solution should be effective and simple enough
for easy implementation. There are many approaches to t10 t11 t12 t13 . . . tm0 tm1 tm2 tm3
achieving test cost reduction. Logic BIST (Built-In Self- Compactor
Test) and test compression are among the most viable and
proven solutions with years of practical applications SO1 ... SOm
worldwide across many different product types. Each
method has its own unique advantages. For some Fig. 1 VirtualScan Architecture
applications, one method may be used on top of the other
in a single design to achieve maximal test cost reduction.
VI1 TDO VI2
2. Test Compression (TDI) (Optional) (Mode)
SI1 ... SIm
With the conventional scan technique, test data volume
and test application time are proportional to the maximum
length of the scan chains. To address the test cost issues
C . . . ... . . .
due to ever-increasing design size, we have developed
VirtualScan technology [1]. As shown in Fig. 1, B . . . . . .
VirtualScan splits the original scan chains into shorter ...
internal scan chains and implements a low overhead, i10 i11 i12 i13 im0 im1 im2 im3
combinational logic based Broadcaster and Compactor S
pair to bridge between limited external scan ports and 0 1 0 1 0 1 ... 0 1 0 1 0 1
large amount of internal scan chains. With VirtualScan,
s10 s11 s12 s13 . . . sm0 sm1 sm2 sm3
up to 10x to 50x test compression ratio can be achieved.
Test patterns for VirtualScan are generated using multi- ...
capture schemes with proper scan constraints imposed by .t .t .t
Broadcaster. In addition, VirtualScan eliminates unknown 10 11 12 t13 . . . .tm0 .t
m1
.t
m2 tm3
value (X) and aliasing effects algorithmically without
additional circuitry. VirtualScan is by nature a full-scan Fig. 2 Broadcaster Structure
system so it can easily support stuck-at, transition, path
delay, bridging faults, and N-detect features.
2.1 Multiple-Capture Clocking Scheme
Fig. 2 shows an example of the VirtualScan Broadcaster
structure. The C block is an optional circuit that provides VirtualScan uses a complete multi-capture clocking
additional signals as the controlled stimuli to obtain scheme as in Fig. 3. Suppose a circuit has two clock
higher fault coverage. The optional S block allows users domains CD1 and CD2, driven by clocks CLK1 and
to switch to serial mode (the original full-scan scheme) to CLK2, respectively, and that CD1 transfers data to CD2.
recoup fault coverage loss due to constraints imposed by As shown in Fig. 3, a test pattern is shifted into all scan
VirtualScan Broadcaster, thus achieving the same overall
flip-flops (FFs) in both CD1 and CD2, and capture is first
fault coverage as the conventional full-scan system but
conducted for CD1 by only activating CLK1 but keeping
with much lower test cost.
CLK2 inactive. After a delay larger than the clock skew

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0-7803-9039-3/$20.00 © 2005 IEEE
between CD1 and CD2, capture is then conducted for furnished with its own PRPG/MISR pair. In addition,
CD2 by only activating CLK2 but keeping CLK1 inactive. phase shifters, PS1 and PS2, (or space expanders, SpE1
The test responses obtained in two captures are then and SpE2), and space compactors, SpC1 and SpC2, are
shifted out together. Note that there is no shift operation used when needed to reduce PRPG and MISR lengths.
between the two capture operations, so it minimizes the
Shift Window Capture Window Shift Window
pattern load time. For transition or path-delay ATPG,
C1 C2
double-capture pulses instead of the single-capture pulses
TCK1 … …
are used to test timing-related delay faults at-speed [2]. d1 d2 d3 d4 d5
C3 C4
Shift Capture Shift
TCK2 … …
SE SE

Fig. 5 At-speed Test Timing Control

CLK1 … …
The double-capture scheme is the basis for providing at-
CLK2 … … speed self-test capability in TurboBIST-Logic. As
illustrated in Fig. 5, the first capture pulses C1 and C3 of
Fig. 3 Multi-Capture Clocking Scheme respective clock domains are pulsed to create function-
like logic states, and the second capture pulses C2 and C4
will then create the function-like transitions to be caught
3. Logic BIST by scan FFs. Durations d2 and d4 are set based on
functional clock frequencies. Thus, true at-speed testing is
In deep-submicron, multi-frequency SoC designs, guaranteed since no test clock frequency manipulation is
bridging and transition faults are dominant fault models. conducted. In addition, there is no strict restriction on the
To address these test requirements, we developed durations of d1 and d5, making it possible to use a single
TurboBIST-Logic to offer at-speed logic Built-In Self- and slow scan enable signal (SE) for all clock domains.
Test (BIST) [2]. As depicted in Fig. 4, the TurboBIST- This significantly eases physical design for logic BIST.
Logic architecture is comprised of a BIST-ready core, Duration d3 can be adjusted to test inter-domain faults. In
pairs of Pseudo-Random Pattern Generators (PRPGs) this way, the capture operation can be correctly conducted
and Multiple-Input Shift Registers (MISRs) for pattern without adding any state-holding FFs that increase delay
generation and output data compaction, an input selector on functional paths.
for BIST or top-up ATPG, a gating block for test clocks,
and a controller for managing the whole BIST operation. 4. Other Considerations
A standard Boundary-Scan interface is often implemented A complete DFT solution may require hierarchical DFT
for loading initial test data or for downloading internal synthesis at RTL, scan synthesis to gate-level, top-up
states during fault diagnosis. ATPG, and fault diagnosis. While TurboBIST-Logic does
not need external test stimuli, the pseudo-random tests
TPG may need supplementary tests to improve the IC’s overall
CK1
PRPG1 PRPG2 fault coverage. For this, some may insert test points, while
CK2
PS1/SpE1 PS2/SpE2
others may apply VirtualScan on top of TurboBIST-Logic.
Start
Finish Input Selector PI/SI
Result 5. Conclusions
TDI CCK1 TCK1
TDO Clock
Controller CCK2 Gating TCK2
Clock
Domain C
Clock
Domain PO/SO
This paper presented DFT methods for test compression
TCK
TSM
Block #1 #2 and logic BIST. Each method can be used independently
BIST-Ready Core or combined to achieve ultra-high product quality and test
cost reduction goals.
SpC1 SpCn

MISR1
ODC
Fig. 4 TurboBIST-Logic Architecture
The BIST-ready core is a full-scan circuit with unknown
value (X) sources properly blocked and all BIST rule
violations fixed. Test points are inserted as needed to
improve BIST fault coverage. For skew management for
testing multiple clock-domain circuits, each domain is
MISRn
References
[1] L.-T. Wang, X. Wen, H. Furukawa, F.-S. Hsu, S.-H. Lin,
S.-W. Tsai, K. S. Abdel-Hafez, and S. Wu, “VirtualScan:
A New Compressed Scan Technology for Test Cost
Reduction,” Proc. Int’l Test Conf., pp. 916-925, 2004.
[2] B. Cheon, E. Lee, L.-T. Wang, X. Wen, P. Hsu, J. Cho, J.
Park, H. Chao, and S. Wu, “At-Speed Logic BIST for IP
Cores,” Proc. Design, Automation and Test in Europe
(DATE), pp. 860-861, Mar. 2005.

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