CycloneII FPGA / ASIC

Multimedia Application

Platform
User Guide
1.1 ASIC/FPGA Introduction
Cyclone II Multimedia Platform is a implement for all there layers: beginner,
pre-intermediate and advanced. Its add-on modules provide the conjunction of
school and company designers. The user can implement VLSI (Very Large Scale
Integration)…with DHL , the digital logic circuit design and realize further the
digital media and image processor.

FPGA/ASIC Media Cyclone II FPGA system platform also provides RTL IP Code
and System Verification by the realization of the image to PC through USB.

Figure 1.1、FPGA / ASIC Multimedia Platform

1.2 General Feature
1. EP2C35 FBGA 672 Cyclone II FPGA Chip

‹ Altera FPGA 90nanometers chip.

‹ Provide 70 ten thousand gate count

‹ Clock Distribution Circuit: decrease Clock Skew.

‹ Block: increase the digital operation effect

‹ Large quantity of Embedded Memory

2. Four 384K byte Frame Buffer Memory: store the VGA image data at
LCD Panel.

‹ It can provisional image data at 2.0＂LCD Panel or VGA

3. Two 1M SRAM: store the CMOS image data

4. It can store image from CMOS Image sensor capture

5. One 2.0 inch 640*240 TFT LCD

‹ high resolution (dot) : 640(W) × 240(H)

6. One CMOS Image Sensor

‹ 30ten thousand pixels to active/static iamge capture (focus function)

7. Two PS2 Outputs: controlled the keyboard and mouse

‹ Keyboard and Mouse

8. Two audio Outputs : conduct the digital image design

‹ Digital audio design

9. One 24 Video DAC: support 80MSPS Operation and VGA image

output.

‹ 80MSPS Operation

‹ VGA Output

10. Six 7-segs display: for Stopwatch, Count down, Alarm clock designs

‹ Stopwatch、counter from the end、counter、alarm

11. 24 user self-definition LED: for signal light design

‹ Implement the LED ticker

12. 16 self-definition push-button switch

13. Three 8 bit DIP Switch

14. 8 pairs of crystals for users: implement the Multiple Clock System
Design with the variety of users＇demands

‹ Multiple Clock System Design

15. Design PLL (Phase Lock Loop)output by Quartus II

16. Provide USB ByteBlaster JTAG and AS(Active serial)

 1.3 EP2C35F672 Cyclone II
Table 2.2、Cyclone II EP2C35 F672 Feature
Resource EP2C35

LE 33,216

M4K RAM 105

Memory (bit) 483,840

18x18 Multipler 35

PLLs 4

I/Os 475

HSTL-15 Class I 205

1.4 Peripheral
1.4.1 Seven Segment LED
The modules of the 7-segments are(form right to left part):
U13/U14/U15/U16/U17/U18. the followings show the position toward Cyclone II
FPGA pins.
U13 U14
Signal Cyclone II FPGA Pins Signal Cyclone II FPGA Pins

A D2
B C2
C B4
D F10
E F3
F F9
G F4
DOT A4
A B5
B A5
C B6
D C3
E J5
F G10
G H12
DOT A6
 U15 U16
Signal Cyclone II FPGA Pins Signal Cyclone II FPGA Pins

A B7 A B9
B A7 B A9
C B8 C H8
D C6 D D8
E D6 E E8
F C4 F D7
G D5 G C7
DOT A8 DOT G5

U17 U18
Signal Cyclone II FPGA Pins Signal Cyclone II FPGA Pins

A G6 A G9
B J8 B J9
C F7 C H11
D E10 D D1
E C9 E F11
F C8 F D10
G D9 G C10
DOT K9 DOT H10

1.4.2 Dip Switch

Cyclone II Multimedia Platform disposes three dip switches. See
picture 2.3

U12 U10 U11

The serial numbers of the 3 dip switches are U11/U12/U13. The followings are
the positions toward FPGA.

U11 U10 U12

Cyclone II Cyclone II Cyclone II
Signal Signal Signal
FPGA Pins FPGA Pins FPGA Pins

1 L10 1 K2 1 L7
2 T10 2 K1 2 L9
3 T9 3 L2 3 N9
4 P3 4 L3 4 P9
5 R2 5 M2 5 P7
6 R3 6 L4 6 P4
7 M3 7 M5 7 R5
8 M4 8 L6 8 R4

1.4.3 Button Switch

Cyclone II Multimedia Platform disposes 16 button switches. Picture 2.5

shows the positions.

sw15 sw13 sw11 sw9 sw7 sw5 sw3 sw1

sw16 sw14 sw12 sw10 sw8 sw6 sw4 sw2

 The serial numbers of 16 button switches designed by the user.

Button Switch
Signal Cyclone II FPGA Pins Signal Cyclone II FPGA Pins

sw1 T17 sw2 U24

sw3 U23 sw4 U22
sw5 W24 sw6 V24
sw7 Y22 sw8 V22
sw9 Y21 sw10 W21
sw11 Y23 sw12 Y24
sw13 AB25 sw14 AB26
sw15 AD24 sw16 AB23

1.4.4 The light emitting diode(LED)

Cyclone II Multimedia Platform disposes 24 LEDs for the designers which
can be set freely. The LEDs colors are red, green, and blue. See picture 2.7

BD7 ~ BD0 GD7 ~ GD0 RD7 ~ RD0

The serial numbers of the LEDs.

Red (RD0~RD7) Green (GD0~GD7) Blue (BD0~BD7)

Cyclone II Cyclone II Cyclone II
Signal Signal Signal
FPGA Pins FPGA Pins FPGA Pins

RD0 U26 GD0 AA26 BD0 V23

RD1 U25 GD1 AA25 BD1 W23
RD2 V26 GD2 R19 BD2 AC26
RD3 V25 GD3 T19 BD3 AC25
RD4 W26 GD4 T20 BD4 AD25
 RD5 W25 GD5 T21 BD5 AA24
RD6 Y26 GD6 U20 BD6 AA23
RD7 Y25 GD7 U21 BD7 AB24

1.4.5 16X2 LCDM Module

Cyclone II Multimedia Platform disposes one LED (U19)- blue back-lighted and
white on the gray background. Picture 2.5 shows the positon.

The following shows the serial pin numbers of the LCD.

LCD
Signal Cyclone II FPGA Pins

RS J1
RW K4
E K3
DB0 H6
DB1 H3
DB2 H4
DB3 J3
DB4 J4
DB5 H2
DB6 H1
DB7 J2
1.4.6 VGA & Audio & PS2 Interface application

Cyclone II Multimedia Platform disposes 24 bites full-color digital to analog

decoder which output form VGA, PS2 and 2 Audio interfaces. See picture 2.10

The serial pins of 24bites full-color VGA/PS2/Audio modules.

VGA Video DAC ( P2 )

Signal Cyclone II FPGA Pins

Blue0 K26
Blue1 K25
Blue2 J26
Blue3 M24
Blue4 M21
Blue5 N23
Blue6 N24
Blue7 H19
Green0 K23
 Green1 L23
Green2 L24
Green3 M22
Green4 M23
Green5 P24
Green6 K19
Green7 H26
Red0 K21
Red1 L20
Red2 L21
Red3 L19
Red4 M20
Red5 K24
Red6 P23
Red7 K18
BLANK N20
SYNC M19
SYNC_T J25
M1 L25
M2 M25
VGA_HS R24
VGA_VS R20

AUDIO Interface ( J4 )
Signal Cyclone II FPGA Pins

AUDIO_L1 T22
AUDIO_R1 T23
AUDIO Interface ( J5 )
Signal Cyclone II FPGA Pins

AUDIO_L2 T24
AUDIO_R2 T25
 PS2 Interface ( J6 )
Signal Cyclone II FPGA Pins

PS2_KB_DAT P17
PS2_KB_CLK R25
PS2 Interface ( J7 )
Signal Cyclone II FPGA Pins

PS2_MS_DAT T18
PS2_MS_CLK R17

1.4.7 2.0 inch LCD

TFT LCD ( U7 )
Signal Cyclone II FPGA Pins

LCD_CLK N26
VSYNC J24
HSYNC H25
LCD_DATA0 G23
LCD_DATA1 G24
 LCD_DATA2 K22
LCD_DATA3 G25
LCD_DATA4 G26
LCD_DATA5 H23
LCD_DATA6 H24
LCD_DATA7 J23

2.4.8 Frame Buffer

The applications on digital camera, cellular phone and digital…are common.

See picture 2.12
 Frame Buffer ( U3 )
Signal Cyclone II FPGA Pins Signal Cyclone II FPGA Pins

DI0 G14 DO0 J14

DI1 C15 DO1 J13
DI2 D14 DO2 G12
DI3 F14 DO3 J11
WE F13 RE G11
GND GND GND GND
TST G13 OE J10
WRST D12 RRST B14
WCK C12 RCK A14
VDD 3.3V DEC 3.3V
DI4 E12 DO4 B12
DI5 F12 DO5 B11
DI6 C11 DO6 A10
DI7 D11 DO7 B10

Frame Buffer ( U4 )
Signal Cyclone II FPGA Pins Signal Cyclone II FPGA Pins

DI0 G17 DO0 C16

DI1 G18 DO1 D16
DI2 F18 DO2 D15
DI3 F17 DO3 E15
WE D17 RE F15
GND GND GND GND
TST C17 OE J17
WRST H17 RRST B18
WCK H16 RCK A18
VDD 3.3V DEC 3.3V
DI4 F16 DO4 B17
DI5 G16 DO5 A17
DI6 G15 DO6 B16
DI7 H15 DO7 B15
 Frame Buffer ( U5 )
Signal Cyclone II FPGA Pins Signal Cyclone II FPGA Pins

DI0 B23 DO0 K17

DI1 A23 DO1 D18
DI2 B22 DO2 E18
DI3 A22 DO3 J18
WE B21 RE C19
GND GND GND GND
TST A21 OE D19
WRST B20 RRST D20
WCK A20 RCK E20
VDD 3.3V DEC 3.3V
DI4 B19 DO4 C21
DI5 A19 DO5 D21
DI6 K16 DO6 C22
DI7 J16 DO7 C23

Frame Buffer ( U6 )
Signal Cyclone II FPGA Pins Signal Cyclone II FPGA Pins

DI0 F26 DO0 C24

DI1 F25 DO1 D23
DI2 E26 DO2 E22
DI3 E25 DO3 E24
WE D26 RE F23
GND GND GND GND
TST D25 OE F24
WRST C25 RRST J20
WCK B25 RCK H21
VDD 3.3V DEC 3.3V
DI4 B24 DO4 J21
DI5 G22 DO5 J22
DI6 G21 DO6 P18
DI7 E23 DO7 N18
2.4.9 ASRAM
Cyclone II Multimedia Platform provides 2 1M x 8 ASARM which can
store much more media data. Picture 2.13 show the position of ASRAM.

ASARM provides 3 control signals: 20-bit A0~~19, 8-bit (I/O0~I/O7) and CE,
OE and WE. Picture 2.14 shows the structure of ASARM.
The serial numbers and positions of ASARM are as follow:

ASRAM ( U20 )
Type Signal Cyclone II FPGA Pins

A A0 AD12
D A1 AA13
D A2 AA14
R A3 AC14
E A4 AA15
S A5 AD17
S A6 AC17
A7 W15
A8 Y16
A9 W16
A10 AE18
A11 AF18
A12 AE17
A13 AF17
A14 AE16
A15 Y14
A16 Y13
A17 AA12
A18 Y12
A19 AF19
D IO0 AC15
A IO1 AB15
T IO2 AD16
A IO3 AC16
IO4 AE15
I/O IO5 AF13
IO6 AE13
IO7 AE12
C OE Y15
 T CE AD15
L WE AA16

ASRAM ( U21 )
Type Signal Cyclone II FPGA Pins

A A0 W17
D A1 V17
D A2 V18
R A3 AA17
E A4 AC18
S A5 AB21
S A6 AD22
A7 AC22
A8 AA20
A9 AD23
A10 U17
A11 W19
A12 AC19
A13 Y18
A14 AA18
A15 AF21
A16 AE20
A17 AF20
A18 AE19
A19 U18
D IO0 AD19
A IO1 AC20
T IO2 AB20
A IO3 AD21
IO4 AE23
I/O IO5 AF23
IO6 AE22
IO7 AF22
C OE AE21
T CE AB18
L WE AC21
1.4.10 CMOS Image Sensor
The 3030ten thousand pixels 640x480 image sensor which can perform
644x484 in raw data format can be manual focused. The sensor can transmit the
image data to PC pin with the USB image catcher and rewrite the register data in
the sensor.

The position of the sensor card. The arrow shows the lens direction.
Picture show the input and output interface

SYSCLK VSYNC

HSYNC

CMOS
Sensor
SCL PXCK

SDA PXD[7:0]

PWDN

The serial numbers and position of the image sensor are as follow:

CMOS Sensor ( J3 )
Signal Cyclone II FPGA Pins

PX0 AA10
PX1 AC7
PX2 Y11
PX3 W11
PX4 AA11
PX5 V11
PX6 V13
PX7 T8
VSYNC Y10
PXCLK PXCLK
SYSCLK SYSCLK
HSYNC AB8
SDA AC9
SCL AC8
PWDN AA9

1.4.11 Programmable clock

Cyclone II Multimedia Platform provides varied pulse designs. It

support 8 quartz crystal and Phase Lock Loop,PLL which can output the
definite frequency, alter or delay the feed back. The designers can input the
outer clock through the SMA. Picture 2.19 shows the positions of the
system pulse.

The designer can put the OSC quartz crystal on Cyclone II Multimedia
Platform
 OSC ( X1~X8 )
OSC (Up) X7 X5 X3 X1

Cyclone II FPGA Pins P1 A13 P26 N26

OSC (Down) X8 X6 X4 X2

Cyclone II FPGA Pins N1 D13 AF14 AC13

‹ PLL

PLL ( PLLP1~ PLLP4 )

Pin(Up) PLLP4 GND PLLP3 GND PLLP2 GND PLLP1 GND

Pins V21 GND E5 GND F21 GND AA7 GND

Pin(Down) PLLN4 GND PLLN3 GND PLLN2 GND PLLN1 GND

Pins V20 GND F6 GND F20 GND AA6 GND

The designers can input the clock media by the SMA

(SMA1)
Num SMA1

Pins B13 or AE14 or N25 or P25 or C13 or AD13

1.4.12 Jump
Cyclone II Multimedia Platform disposes several JUMP for OSC or
PLL clock. The user can apply widely. Take VGA_CLK for instance, the
designers can use 25MHz or PLLP4 for VGA clock input. In some occasion,
the clocks are limited, such as 24.576and 12.175, etc. Picture 2.23 shows the
positions of JUMP.
The following shows the jumps pin numbers.

SENSOR_SYSCLK JUMP
Num 1 2 3

Name OSCX1 Sensor_SYSCLK PLLP2

Pins assign N26 Sensor_SYSCLK F21

★★ SENSOR_SYSCLK JUMP default ( 1-2 )

SENSOR_PXCLK JUMP
Num 1 2 3

Name FPGA_CLK_IN Sensor_PXCLK User IO

Pins assign P2 or N2 Sensor_PXCLK J7

★★ SENSOR_PXCLK JUMP default ( 2-3 )

LCD_CLK JUMP
Num 1 2 3

Name OSCX1 LCD_CLK PLLP2

Pins assign N6 LCD_CLK F21
★★ LCD_CLK JUMP default ( 1-2 )

VGA_CLK JUMP
Num 1 2 3

Name PLLP4 VGA_CLK OSCX4

Pins assign V21 VGA_CLK AF14

★★ VGA_CLK JUMP default ( 1-2 )

FAST AS / AS JUMP
Num 1 2 3

Name VCC MSEL1 GND

Pins assign VCC MSEL1 GND

★★ Fast AS / AS JUMP default ( 2-3 )

2.4.13 Device Configuration

1.4.14 user Expansion block interface

The user expansion block interface can be posed on Cyclone II Multimedia
Platform. The expansion block interface also dispose the power protection circuit
which provides up to 5V. The two block of the expansion interface are
expansion long interface and expansion short interface. Picture 2.25 shows the
positions.
The pin numbers of Expansion short block interface.

(JP6)
Address Signal Cyclone II FPGA Pins Address Signal Cyclone II FPGA Pins

JP6.1 5V VCC_5V JP6.2 GND GND

JP6.3 SB_11 W2 JP6.4 SB_12 AC11
JP6.5 SB_13 AD11 JP6.6 SB_14 W10
JP6.7 SB_15 AD10 JP6.8 SB_16 AB10
JP6.9 SB_17 AB12 JP6.10 SB_18 AC12
JP6.11 SB_19 V14 JP6.12 SB_20 AD8
JP6.13 SB_21 U9 JP6.14 SB_22 V9
JP6.15 SB_23 V10 JP6.16 SB_24 AC10
JP6.17 SB_25 AC5 JP6.18 SB_26 AD6
JP6.19 GND GND JP6.20 OSCX4 AF14
JP6.21 SB_27 AC6 JP6.22 GND GND
JP6.23 SB_28 AD7 JP6.24 GND GND
JP6.25 SB_29 W8 JP6.26 GND GND
JP6.27 SB_30 AF10 JP6.28 SB_31 AE11
JP6.29 SB_32 AC3 JP6.30 GND GND
JP6.31 SB_33 AA5 JP6.32 SB_34 AD5
JP6.33 SB_35 AE8 JP6.34 OSCX6 D13
JP635 SB_36 AF8 JP6.36 SB_37 AE9
JP6.37 SB_38 AF9 JP6.38 OSCX2 AC13
JP6.39 SB_39 AE10 JP6.40 GND GND

(JP7)
Address Signal Cyclone II FPGA Pins Address Signal Cyclone II FPGA Pins

JP7.1 GND GND JP7.2 5V VCC_5V

JP7.3 GND GND JP7.4 SB_0 AE7
JP7.5 SB_1 AF6 JP7.6 SB_2 AE5
JP7.7 SB_3 AF4 JP7.8 SB_4 AE2
JP7.9 SB_5 AE3 JP7.10 SB_6 AD4
JP7.11 SB_7 AF5 JP7.12 SB_8 AE6
JP7.13 SB_9 AF7 JP7.14 SB_10 U12

(JP8)
Address Signal Cyclone II FPGA Pins Address Signal Cyclone II FPGA Pins

JP8.1 Vunreg VCC_Vunreg JP8.2 GND GND

JP8.3 3V3 VCC_3V3 JP8.4 GND GND
JP8.5 3V3 VCC_3V3 JP8.6 GND GND
 JP8.7 3V3 VCC_3V3 JP8.8 GND GND
JP8.9 OSCX8 N1 JP8.10 GND GND
JP8.11 OSCX1 N26 JP8.12 GND GND
JP8.13 OSCX7 P1 JP8.14 GND GND
JP8.15 3V3 VCC_3V3 JP8.16 GND GND
JP8.17 OSCX3 P26 JP8.18 GND GND
JP8.19 OSCX5 A13 JP8.20 GND GND

The pin numbers of Expansion long block interface.

(JP9)
Address Signal Cyclone II FPGA Pins Address Signal Cyclone II FPGA Pins

JP9.1 5V VCC_5V JP9.2 GND GND

JP9.3 LB_0 AD3 JP9.4 LB_1 AD2
JP9.5 LB_2 AB1 JP9.6 LB_3 AB2
JP9.7 LB_4 Y1 JP9.8 LB_5 AA2
JP9.9 LB_6 AA1 JP9.10 LB_7 AC2
JP9.11 LB_8 AC1 JP9.12 LB_9 AB4
JP9.13 LB_10 W2 JP9.14 LB_11 W1
JP9.15 LB_12 V2 JP9.16 LB_13 V1
JP9.17 LB_14 U2 JP9.18 LB_15 AA3
JP9.19 GND GND JP9.20 LB_16 AA4
JP9.21 LB_17 AB3 JP9.22 GND GND
JP9.23 LB_18 T2 JP9.24 GND GND
JP9.25 LB_19 U1 JP9.26 GND GND
JP9.27 LB_20 Y5 JP9.28 LB_21 Y4
JP9.29 LB_22 Y3 JP9.30 GND GND
JP9.31 LB_23 W6 JP9.32 LB_24 W4
JP9.33 LB_25 U7 JP9.34 LB_26 V3
JP9.35 LB_27 V6 JP9.36 LB_28 V7
JP9.37 LB_29 W3 JP9.38 LB_30 U6
JP9.39 LB_31 U3 JP9.40 GND GND

(JP10)
Address Signal Cyclone II FPGA Pins Address Signal Cyclone II FPGA Pins

JP10.1 GND GND JP10.2 5V VCC_5V

JP10.3 LB_33 R7 JP10.4 LB_34 G1
JP10.5 LB_35 G2 JP10.6 LB_36 K5
JP10.7 LB_37 R6 JP10.8 LB_38 R8
JP10.9 LB_39 U10 JP10.10 LB_40 K7
JP10.11 LB_41 J6 JP10.12 LB_42 F1
JP10.13 LB_43 F2 JP10.14 LB_44 E2

(JP11)
Address Signal Cyclone II FPGA Pins Address Signal Cyclone II FPGA Pins

JP11.1 Vunreg VCC_Vunreg JP11.2 GND GND

JP11.3 3V3 VCC_3V3 JP11.4 GND GND
JP11.5 3V3 VCC_3V3 JP11.6 GND GND
JP11.7 3V3 VCC_3V3 JP11.8 GND GND
JP11.9 PLLP1 AA7 JP11.10 GND GND
JP11.11 PLLP2 F21 JP11.12 GND GND
JP11.13 PLLP3 E5 JP11.14 GND GND
JP11.15 3V3 VCC_3V3 JP11.16 GND GND
JP11.17 3V3 VCC_3V3 JP11.18 GND GND
JP11.19 3V3 VCC_3V3 JP11.20 GND GND

(JP12)
Address Signal Cyclone II FPGA Pins Address Signal Cyclone II FPGA Pins

JP12.1 GND GND JP12.2 GND GND

JP12.3 OSCX8 N1 JP12.4 OSCX1 N26
JP12.5 GND GND JP12.6 GND GND
JP12.7 LB_45 E1 JP12.8 LB_46 G3
JP12.9 GND GND JP12.10 GND GND
JP12.11 OSCX7 P1 JP12.12 OSCX3 P26
JP12.13 GND GND JP12.14 GND GND
JP12.15 LB_47 G4 JP12.16 LB_48 K6
JP12.17 LB_49 K8 JP12.18 LB_50 T7
JP12.19 LB_51 V5 JP12.20 LB_52 U5
JP12.21 LB_53 U4 JP12.22 LB_54 T4
JP12.23 GND GND JP12.24 GND GND
JP12.25 OSCX5 A13 JP12.26 OSCX4 AF14
JP12.27 GND GND JP12.28 GND GND
JP12.29 LB_55 P6 JP12.30 LB_56 T6
JP12.31 LB_57 V4 JP12.32 GND GND
JP12.33 GND GND JP12.34 PLLP4 V21
JP1235 GND GND JP12.36 GND GND
JP12.37 OSCX6 D13 JP12.38 OSCX2 AC13
JP12.39 GND GND JP12.40 GND GND

2.4.15 Power Supply

Cyclone II Multimedia Platform supports 1V2 /3V3 and 5V.the average
of the power loss is 10W. The following shows the information:
 Power Supply LEDs
Board Reference Signal Description
1V2_OK VCC_1V2 Indicates the presence of 1.2 V
3V3_OK VCC_3V3 Indicates the presence of 3.3 V
5V_OK VCC_5V Indicates the presence of 5 V

The power circuit positions

Digital Image Sensor

2.1 CMOS Interface

 The digital image sensor contains 640x480 CMOS Image Camera Module
interface (644x484 in raw data). See Figure 2.6. The definition are as follow,

„ SYSCLK：System clock signal(limit 26MHz，use 25MHz)25MHz

„ PWDN： power-control signal
„ SCL：I2C clock signal
„ SDA：I2C data signal (two-way)
„ VSYNC：Vertical synchronization
„ HSYNC：Horizontal synchronization
„ PXCK：Output clock signal
„ PXD[7:0]：Output Bus

Figure 2.6、output/ input interface

2.2 The image sensor output data formats

 The digital image sensor contains a image processor which can control the
exposure, modify automatically white-balance . It also provides 3 modes for the
user: YCbCr(422 format)、RGB(565format) and RAW DATA. See Figure 2.7, 2.8
andd 2.9. The sensor’s output format is YCbCr. The RAW DATA in Figure 2.5
indicates the original output data. See 2.10, 2.11 and 2.12.

Figure 2.7、YCbCr output format(Default)

 Figure 2.8、RGB data output format

Figure 2.9、RAW DATA output format

Figure 2.10、YCbCr data format output timing

Figure 2.11、RGB data format output timing

 Figure 2.12、RAW data format output timing

2.3 The way to control the image sensor

The interface of the image sensor whose ID is7’b1000000 is a I2C paralled
interface. It can control both the sensor and the processor. The way to control it is
to change the control register on the sensor and the processor through the I2C
paralled interface. See Figure 2.1~2.4.
 Figure 2.13、I2C timing spec.

The user should avoid not to alter the register due to the fact that most of the
requirement can be provided by the processor.
Table 2.1、CMOS Processor Register list
Table 2.2、CMOS Controller Register list
Table 2.3、Description
Table 2.4、CMOS Controller Register Description
2.4 CMOS Project
As Figure 2.14 shows

Figure 2.14

Step1：

Figure 2.15、RGB320x240.mif

After created mif file，use MegaWizard of Altera Quartus II to build a

32x16 ROM，and named ROM32x16。As Figure2.16~Figure2.22 shows。
Figure 2.16、Start MegaWizard (Step 1)

Figure2.17、(Step 2)

Figure2.18、(Step 3)
 Figure2.19、(Step 4)

Figure2.20、(Step 5)

Figure2.21、RGB320x240.mif (Step 6)
 Figure2.22、(Step 7)

Step2：CMOS_I2C_s I2C (Verilog)

`define Slave_ID 7'b1000000

`define Write 1'b0
`define OpNum 6'd11 //Max=32

`define Idle 4'd00

`define Write_Start 4'd01
`define Write_Cmd 4'd02
`define WWait1 4'd03
`define Write_Addr 4'd04
`define WWait2 4'd05
`define Write_Data 4'd06
`define WWait3 4'd07
`define Write_Stop 4'd08

module CMOS_I2C_s (rst_n,

SYS_clk,
 SCL,
SDA
);

input rst_n; //reset

input SYS_clk; //System Clock

output SCL; //I2C clock CLK_In/128

inout SDA; //I2C Data

//temp register declaration

reg [5:0] ROM_ADDR; //ROM Address
wire [15:0] ROM_DATA; //ROM DATA

reg SDATA_Out;
reg SDATA_Out_En;

reg [6:0] CLK_reg;

wire FSM_CLK;
reg [7:0] WCmd;
reg [7:0] OpAddr;
reg [7:0] OpData;
reg ReadOp_En;
reg OpFinish;

reg [2:0] BitCnt;

reg [4:0] CState;
//--------------------------------------------------------
// LPM_ROM 16x16 Instance
//--------------------------------------------------------
ROM32x16 OpROM (
.address(ROM_ADDR[4:0]),
.clock(SCL),
.q(ROM_DATA)
);

//--------------------------------------------------------
// Clock Generator
//--------------------------------------------------------
always @(negedge SYS_clk or negedge rst_n)
if(!rst_n) CLK_reg <= 7'b00000;
else CLK_reg <= CLK_reg + 1;

assign FSM_CLK = CLK_reg[5];

//--------------------------------------------------------
// Initiate WCmd
//--------------------------------------------------------
always @(rst_n)
if(!rst_n)
begin
WCmd <= {`Slave_ID,`Write};
end

//--------------------------------------------------------
// ROM State
//--------------------------------------------------------
always @(ROM_ADDR)
 if(ROM_ADDR==`OpNum) OpFinish = 1'b1;
else OpFinish = 1'b0;

//--------------------------------------------------------
// Operand Data
//--------------------------------------------------------
always @(posedge FSM_CLK or negedge rst_n)
if(!rst_n) {OpAddr,OpData} <= 16'h0000;
else if(ReadOp_En) {OpAddr,OpData} <= ROM_DATA;
else {OpAddr,OpData} <= {OpAddr,OpData};

//--------------------------------------------------------
// SIE FSM
//--------------------------------------------------------
always @(posedge FSM_CLK or negedge rst_n)
if(!rst_n)
begin
ROM_ADDR <= 6'b000000;
ReadOp_En <= 1'b0;
SDATA_Out_En <= 1'b1;
SDATA_Out <= 1'b1;
BitCnt <= 3'b111;
CState <= `Idle;
end
else case(CState)
`Idle : begin
SDATA_Out_En <= 1'b1;
SDATA_Out <= 1'b1;
BitCnt <= 3'b111;
 if(!SCL && !OpFinish)
begin
ReadOp_En <= 1'b1;
CState <= `Write_Start;
end
else
begin
ReadOp_En <= 1'b0;
CState <= `Idle;
end
end

//--------------------------------------------------------
// Write Comd routine
//--------------------------------------------------------
`Write_Start : begin
SDATA_Out_En <= 1'b1;
if(!SCL )
begin
CState <= `Write_Start;
SDATA_Out <= 1'b1;
end
else
begin
CState <= `Write_Cmd;
SDATA_Out <= 1'b0;
end
end
`Write_Cmd : begin
 ReadOp_En <= 1'b0;
SDATA_Out_En <= 1'b1;
if(!SCL )
begin
SDATA_Out <= WCmd[BitCnt];
BitCnt <= BitCnt;
CState <= `Write_Cmd;
end
else
begin
SDATA_Out <= SDATA_Out;
BitCnt <= BitCnt-1;
if(BitCnt==3'b000)
CState <= `WWait1;
else
CState <= `Write_Cmd;
end
end
`WWait1 : begin
SDATA_Out_En <= 1'b0;
BitCnt <= 3'b111;
if(!SCL )
CState <= `WWait1;
else
CState <= `Write_Addr;
end
`Write_Addr : begin
SDATA_Out_En <= 1'b1;
if(!SCL )
 begin
SDATA_Out <= OpAddr[BitCnt];
BitCnt <= BitCnt;
CState <= `Write_Addr;
end
else
begin
SDATA_Out <= SDATA_Out;
BitCnt <= BitCnt-1;
if(BitCnt==3'b000)
CState <= `WWait2;
else
CState <= `Write_Addr;
end
end
`WWait2 : begin
SDATA_Out_En <= 1'b0;
BitCnt <= 3'b111;
if(!SCL )
CState <= `WWait2;
else
CState <= `Write_Data;
end
`Write_Data : begin
SDATA_Out_En <= 1'b1;
if(!SCL )
begin
SDATA_Out <= OpData[BitCnt];
BitCnt <= BitCnt;
 CState <= `Write_Data;
end
else
begin
SDATA_Out <= SDATA_Out;
BitCnt <= BitCnt-1;
if(BitCnt==3'b000)
CState <= `WWait3;
else
CState <= `Write_Data;
end
end
`WWait3 : begin
SDATA_Out_En <= 1'b0;
BitCnt <= 3'b111;
if(!SCL )
CState <= `WWait3;
else
CState <= `Write_Stop;
end
`Write_Stop : begin
SDATA_Out_En <= 1'b1;
if(!SCL )
begin
CState <= `Write_Stop;
SDATA_Out <= 1'b0;
end
else
begin
 CState <= `Idle;
ROM_ADDR <= ROM_ADDR + 1;
SDATA_Out <= 1'b1;
end
end
endcase
//--------------------------------------------------------
// Output Declaration
//--------------------------------------------------------
assign SCL = CLK_reg[6];
assign SDA = (SDATA_Out_En) ? SDATA_Out : 1'bz;

endmodule

Step3：CMOS_I2C_s symbol
 Figure2.1、CMOS_I2C_s

Step4：CMOS2Buffer (Verilog)

module CMOS2Buffer (SYS_rst,

PXCK,
VSYNC,
HSYNC,
PXD,

WCK,
WRST,
WE_n,
WDATA,
TST
 );

input SYS_rst; //System reset

input PXCK; //Sensor Clock
input VSYNC; //VSYNC
input HSYNC; //HSYNC
input [7:0] PXD; //Sensor DATA[7:0]

output WCK; //RAM clock

output WRST; //RAM reset
output WE_n; //write enable
output [7:0] WDATA; //data
output TST;
assign WDATA = (!HSYNC) ? PXD : 8'b0;
assign WCK = PXCK;
assign WRST = ~VSYNC;
assign WE_n = HSYNC;
assign TST = 1'b0;

endmodule

Step5：DispCtl (Verilog)
R[4:0] => {R[4:0], R[4:2]}
G[5:0] => {G[5:0], G[5:4]}
B[4:0] => {B[4:0], B[4:2]}

module DispCtl (SYS_rst,

SYS_clk,
 RCK,
OE_n,
RRST,
RE_n,
RDATA,

VSYNC,
HSYNC,
LCD_DATA
);

input SYS_rst; //LCD Enable Signal

input SYS_clk; //System Clock
output RCK; //Read CLK
output OE_n; //Read Output Enable
output RRST; //Read Reset
output RE_n; //Read Enable
input [7:0] RDATA; //DATA Bus

output VSYNC; //Vertical sync

output HSYNC; //Horizontal sync
output[7:0] LCD_DATA; //Data Bus to LCD

reg RE_n;
reg VSYNC;
reg HSYNC;
reg [7:0] LCD_DATA;

//Temp reg and wires declaration

 reg [18:0] VCnt;
reg VDisp_EN;
reg Field;
reg [10:0] HCnt;
reg Hdisp_EN;

reg [1:0] PixState;

reg [1:0] OpFilter;
reg [1:0] OpFilter_dly;

reg [7:0] DATA_tmp1;

reg [7:0] DATA_tmp2;

//--------------------------------------------------------
// LCD Interface Signal
//--------------------------------------------------------
//VSYNC
always @(negedge SYS_clk)
if(!SYS_rst)
begin
VCnt <= 19’b0;
Field <= 1’b0;
VSYNC <= 1’b1;
end
else if(VCnt==19’d409499)
begin
VCnt <= 19’b0;
Field <= ~Field;
VSYNC <= 1’b0;
 end
else
begin
VCnt <= VCnt + 1;
Field <= Field;
VSYNC <= 1’b1;
end

always @(VCnt or Field)

if(Field) //Even Field
begin
if(VCnt>=’d33540 && VCnt<’d407940)
Vdisp_EN <= 1’b1;
else
Vdisp_EN <= 1’b0;
end
else
begin
if(VCnt>=’d32760 && VCnt<’d407160)
Vdisp_EN <= 1’b1;
else
Vdisp_EN <= 1’b0;
end

//HSYNC
always @(negedge SYS_clk)
if(!SYS_rst)
begin
HCnt <= 11’b0;
 HSYNC <= 1’b1;
end
else if(HCnt==11’d1559)
begin
HCnt <= 11’b0;
HSYNC <= 1’b0;
end
else
begin
HCnt <= HCnt + 1;
HSYNC <= 1’b1;
end

always @(HCnt)
if(HCnt>=’d19 && HCnt<’d1519) Hdisp_EN <= 1’b1;
else Hdisp_EN <= 1’b0;

//--------------------------------------------------------
// Frame Buffer Interface Signal
//--------------------------------------------------------
assign RCK = SYS_clk;
assign OE_n = 1’b0;
assign RRST = Vdisp_EN;
always @(negedge SYS_clk or negedge SYS_rst)
if(!SYS_rst)
begin
RE_n <= 1’b1;
PixState <= 2’b00;
OpFilter <= 2’b11;
 end
else if(Vdisp_EN && Hdisp_EN)
case(PixState)
2’b00: begin
RE_n <= 1’b0;
PixState <= 2’b01;
OpFilter <= 2’b00;
end
2’b01: begin
RE_n <= 1’b0;
PixState <= 2’b10;
OpFilter <= 2’b01;
end
2’b10: begin
RE_n <= 1’b1;
PixState <= 2’b11;
OpFilter <= 2’b10;
end
2’b11: begin
RE_n <= 1’b1;
PixState <= 2’b00;
OpFilter <= 2’b11;
end
endcase
else
begin
PixState <= 2’b00;
RE_n <= 1’b1;
OpFilter <= 2’b11;
 end

always @(negedge SYS_clk or negedge SYS_rst)

if(!SYS_rst) OpFilter_dly <= 2’b11;
else OpFilter_dly <= OpFilter;

always @(posedge SYS_clk)

if(!SYS_rst) begin DATA_tmp1 <= 8’b0;
DATA_tmp2 <= 8’b0; end
else if(PixState==2’d1) DATA_tmp1 <= RDATA;
else if(PixState==2’d2) DATA_tmp2 <= RDATA;
else begin DATA_tmp1 <= DATA_tmp1;
DATA_tmp2 <= DATA_tmp2; end

//--------------------------------------------------------
// LCD Data
//--------------------------------------------------------
always @(OpFilter_dly or DATA_tmp1 or DATA_tmp2)
case(OpFilter_dly)
2’b00: LCD_DATA = {DATA_tmp1[7:3],DATA_tmp1[7:5]};
2’b01: LCD_DATA =
{DATA_tmp1[2:0],DATA_tmp2[7:5],DATA_tmp1[2:1]};
2’b10: LCD_DATA =
{DATA_tmp2[4:0],DATA_tmp2[4:2]};
2’b11: LCD_DATA = 8’b00000000;
endcase

endmodule
 Step6：

Figure2.24

Step7：Add ROM32x16 file

AS Figure2.25、Figure2.26 shows。

Figure2.25、(Step 1)
 Figure2.26、(Step 2)

Step8：Pin assigment
As Figure2.27

Figure2.27、Assignments
 Figure2.28

Figure2.29

Figure2.30、TFT-LCD

Step9：Compile
Figure2.31