Assessing the Performance of CMOS

Amplifiers Using High-k Dielectric with

Metal Gate on High Mobility Substrate

Deepa Anand(B) , M. Swathi(B) , A. Purushothaman,

and Sundararaman Gopalan

Department of Electronics and Communication Engineering,

Amrita Vishwa Vidyapeetham, Amritapuri, India
deepa.anand89@gmail.com, swathi.prakashan@gmail.com

Abstract. With the increase in demand for high-performance ICs for

both memory and logic applications, scaling has been continued down
to 14 nm node. To meet the performance requirements, high-k dielectrics
such as HfO2 , ZrO2 have replaced SiO2 in the conventional MOS struc-
ture for sub-45 nm node. Correspondingly, the polysilicon gate electrode
has been replaced by metal gate electrode in order to enable integra-
tion with high-k. Furthermore, the standard silicon substrate has been
replaced by high mobility substrate in order to obtain desired transistor
performance. While the fabrication technology for CMOS has advanced
rapidly the traditional design tools used for designing circuits contin-
ues to use conventional MOS structure and their properties. This paper
aims to analyze frequency response of CMOS common source ampli-
fier(CSA) and differential amplifier by simulating in MATLAB using
metal gate/high-k/Ge structure and to compare with traditionally used
amplifier design using standard MOS structure.

Keywords: CMOS - Complementary Metal Oxide Semiconductor

EOT - Effective Oxide Thickness · CSA - Common Source Amplifier
UGB - Unity Gain Bandwidth
High-k dielectrics based amplifier design

1 Introduction
In accordance with Moore’s law, the transistor density on a chip has been increas-
ing exponentially over the last several decades [1], which leads to continuous
scaling of the device. This continued scaling has resulted in improvement in
functionality and performance of the chip while reducing the power consump-
tion and cost. One of the fundamental components of an IC for any application
(memory, logic, telecommunications etc.) is the CMOS transistor, which accounts
for more than 95% of transistors used by the industry [2,3]. Traditionally, the
MOS structures are made up of polysilicon gate electrode, SiO2 gate dielectric
and conventional silicon substrate. However, scaling of device dimensions leads
c Springer Nature Singapore Pte Ltd. 2018
M. Singh et al. (Eds.): ICACDS 2018, CCIS 905, pp. 279–289, 2018.
https://doi.org/10.1007/978-981-13-1810-8_28
280 D. Anand et al.

to the subsequent reduction in gate oxide thickness which in turn has led to very
high leakage current especially for 45 nm node and below [4,5]. This has been
overcome by use of hafnium-based and zirconium-based dielectrics which have
higher dielectric constant (≈22–25) [8,19] than the conventional SiO2 . Since the
high-k dielectrics are not thermodynamically stable with polysilicon and due to
poly depletion effect which reduces the overall gate capacitance, polysilicon has
to be replaced with suitable metal gate electrodes [4,5]. The gate capacitance
needs to be maintained high for better performance of the device. The gate
capacitance is given by the Eq. 1,
Cox k
= 0 (1)
A tox
where, Cox is the oxide capacitance, 0 is the permittivity, k is the dielectric
constant, A is the area, and tox is the oxide thickness. As the MOSFET width
and length are decreasing, Cox has come down. For all these years this was coun-
tered by decreasing tox . However as SiO2 thickness reduces below 4–5 nm, direct
tunneling between the gate electrode and substrate takes place which causes
high leakage and reliability issues [5]. But this leakage was found acceptable for
high-performance applications down to 65 nm node, however, for the 45-nm node
and below the tox requirement goes below 1 nm which causes unacceptably high
leakage current [4,5,19]. Therefore, in order to reduce the leakage current high-k
dielectrics were used. In accordance with Eq. 1, for the same oxide capacitance,
a thinner SiO2 film can be replaced with a much thicker high-k film which will
cause a significant reduction in leakage, which will also improve the reliability.
Equation 2 gives the thickness of the high-k film which is equivalent to 1 nm
SiO2 . The EOT (equivalent to 1 nm SiO2 thickness) is calculated using the k
values 17 for ZrO2 , 22 for HfO2 and 5 for nitrided oxide (SiON) obtained from
fabricated results [13,15,17].
 
kSiO2
EOT = tHigh−k (2)
kHigh−k
where, tHigh−k and kHigh−K are the thickness and relative dielectric constant
of the high-k material. The thickness of ZrO2 , HfO2 , and nitrided oxide (SiON)
are obtained as 4.35 nm, 5.64 nm, 1.6 nm respectively for EOT, equivalent to
1 nm SiO2 thickness. As further scaling continues a lower EOT is preferred [6]
and using high-k would ensure lower leakage compared to SiO2 . For 1 nm EOT,
the leakage current is found to be in the range of ≈10−3 A/cm2 for ZrO2 and
HfO2 which is very much less compared to SiO2 which has a leakage current
of 100 A/cm2 [19]. After the rigorous study on high-k materials for over two
decades, HfO2 and ZrO2 were chosen as suitable candidates based on their high-k
value (≈ 22–25), compatibility with the substrate, good band offset, high thermal
stability etc [19].
Poly-crystalline silicon (polysilicon) was used as gate material since it has
same chemical composition as the silicon channel beneath the gate oxide, due to
its high melting point, easiness to fabricate etc. But because of dopant penetra-
tion, poly depletion effect, Fermi level pinning, thermodynamic stability issue
 Assessing the Performance of CMOS Amplifiers 281

with high-k [5] etc, polysilicon had to be replaced with the metal gate in the
45 nm node. It was found that high-k/ metal gate is much better than high-
k/poly w.r.t above mentioned issues. There are many candidates such as TaN,
TiN, Pt etc which can be used for the gate electrode, based on the work function
and thermal stability [5,7,9,10].
It was observed that upon the integration of high-k dielectrics into CMOS it
leads to mobility degradation of the carrier at high electric field in the channel
region due to columbic scattering [14]. In 45 nm node, this issue was addressed
by using ‘strained silicon’ in the substrate/channel region which improves the
mobility of the carriers [5]. However, since 45 nm node, scaling of high-k continues
even further, leading to further mobility degradation (due to increase in the
vertical electric field). This may be resolved by using high mobility substrates
such as Germanium or Gallium Arsenide in the channel region for the sub-22 nm
nodes [5,16,19].
While the fabricated technology has changed drastically since 2007, IC
designs and design tools continue to use basic MOS structure and their charac-
teristics. Despite the fact that there are a lot of studies on high k/metal gate
transistors, not much study is available for CMOS amplifier design circuits using
high-k and metal gates. Since the technology is progressed for conventional MOS
structure, it will be better if high-k/metal gate/Ge combination is used. By using
this combination in the designing stage itself we can get a more accurate pre-
diction of the VLSI circuit. In this work, CMOS single stage common source
amplifier (CSA) circuits (R Load, Active load) and the differential amplifier is
designed with metal gate/high-k/Ge transistor using MATLAB. With the sim-
ulation results, the impact of various combinations of gate stack on frequency
response is studied and this is being compared with traditionally used MOS
transistor.

2 Methodology
An amplifier is one of the essential and critical circuit which have a wide range of
applications [2,3]. Gain and bandwidth are two main parameters in the amplifier.
Amplifier performance can be improved by increasing these two parameters. The
effect of proposed gate stacks such as TaN/HfO2 /Ge, Pt/ZrO2 /Ge and strained-
Si is studied on the above parameters and compared with traditional gate stack
(Polysilicon/SiO2 /Si).
The frequency response of CMOS single stage amplifier primarily depends on
trans conductance and output resistance. Transconductance, gm , is defined as the
change in current to change in voltage by keeping VDS constant [12]. Increase
in gm will increase the gain (amplification) and bandwidth of the amplifier.
Transconductance gm is given as,
  
W
gm = un Cox VGS − VT H (3)
L
where μn - electron mobility, Cox - oxide capacitance, W - width, L - length,
VGS - Gate source voltage, VT H - threshold voltage.
282 D. Anand et al.

From the above Eq. 3, it is clear that gm is dependent on mobility, gate oxide
thickness, width, length, current, VGS , and VT H . Mobility, gate oxide thickness
and threshold voltage depends on the materials used in the gate stack whereas
width, length, current, and VGS are design parameters.
Mobility varies with channel length and adds second order effects on tran-
sistor parameters. For conventional MOS structure the effective mobility for
fabricated device is 260 cm2 /V s [19], but upon using strained silicon extracted
mobility obtained from fabricated result is 450 cm2 /V s [17]. For smaller gate
length using metal gate/high-k/G, we can obtain higher mobility compared to
the metal gate/high-k/Si gate stack [5,11]. As transconductance depends directly
on mobility (Eq. 3) it is obvious that we can achieve an increase in transconduc-
tance upon using strained-Si and metal gate/high-k/Ge gate stack combination.
Since the saturation current also depends directly on the mobility (Eq. 4),
increase in mobility by using strained-Si and Germanium can also result in the
increase of drive current which makes the device to perform better. The satura-
tion current is given as,
  2
1 W
ID = un Cox VGS − VT H (4)
2 L
where ID - saturation current
The transistor parameters for proposed gate stacks is obtained for EOT of
1 nm. As discussed in the above section by using high-k materials, same gate
capacitance as that of SiO2 can be obtained with higher gate oxide thickness.
As a result of which gate leakage will get reduced.

2.1 Frequency Response of Single Stage CSA (R Load and Active

Load):
A single stage CSA with the resistive load and active load are considered in
the paper (Fig. 1: A and B). Gain and bandwidth (UGB) for proposed combi-
nations of gate stacks are analyzed and compared with traditional gate stack
(Polysilicon/SiO2 /Si).

Fig. 1. (A) Common source amplifier with R load. (B) Common source amplifier with
Active load

The open loop transfer function of CSA with R load is obtained as [12],
gm R D
A(S) = (5)
1 + sRD CL
 Assessing the Performance of CMOS Amplifiers 283

Where, RD is load resistance, CL is load capacitance, r01 saturation resis-

tance of nMOS. Since RD is very much smaller in size than r01 and both are
in parallel, r01 can be neglected. As a result, the channel length coefficient does
not affect the gain of R load CSA. From the Eq. 5, it is clear that gain depends
on trans conductance. As gm increases gain will be increased.
CSA with resistive load has got trade-offs between voltage swing, gain, and
bandwidth hence resistor has to be replaced with active load [12]. The open loop
transfer function of CSA with the Active load is obtained as,

gm (r01 ||r02 )
A(S) = (6)
1 + s(r01 ||r02 )CL

Where r01 and r02 are saturation resistances of nMOS and pMOS.
Care has to be taken to address the device parameter λ, which affects the gain
in Active load. This is because saturation resistances r01 and r02 depend inversely
on this parameter. λ is channel length modulation coefficient. It is predominant
in short channel devices. Channel length modulation is a phenomenon which
results in a non-zero slope in ID - VDS characteristics and hence drain current
never saturates [12].
Often, the channel-length modulation coefficient λ is expressed as early volt-
age VA , which is the inverse of λ. Early voltage is obtained from output charac-
teristics of MOSFET, by extrapolating the graph to the x-axis [14] (Fig. 2).

Fig. 2. Obtaining early voltage

Device parameter, λ for various combinations in the paper, is obtained from

output characteristics of the fabricated device with the respective combinations
from works of literature [13,15,17]. For traditional MOS structure output charac-
teristics is obtained from Cadence simulations. Substituting the obtained values
of λ, the gain obtained from the frequency response of CSA with the active load
of various combinations is compared with CSA with traditional MOS structure.
The work is extended to study on differential amplifier Fig. 3. The differential
input is given to the two transistor M1 and M2. Vb is applied in such a way that,
the transistor M3, M4, MT will be in saturation. MT is the tail transistor, which
acts as a constant current source. Current has to be maintained constant to
avoid DC voltage shift [12].
284 D. Anand et al.

Fig. 3. Differential amplifier

Frequency response of the differential amplifier is obtained as,

2gm (r01 ||r03 )

A(S) = (7)
1 + s(r01 ||r03 )CL

Where r01 and r03 are saturation resistances of nMOS and pMOS.
Using the Eq. 7, frequency response of the differential amplifier is analyzed
and gain for different gate stacks is compared.
Finally, the study on Unity Gain Bandwidth (UGB) is done. UGB also deter-
mines the amplifier performance. Bandwidth is the range of frequencies over
which amplifier can produce a specified level of performance. Unity Gain Band-
width (UGB) is the frequency at which the open loop gain becomes unity. UGB
depends on transistor parameter transconductance, gm , and load capacitance. It
is given as:
gm
U GB = (8)
CL
From the Eq. 8, it is clear that when gm increases UGB will get increased.
Increase in UGB makes the amplifier to work at higher frequencies also, which
is much advantageous for many applications. In this work, UGB for various
combinations is obtained using the Eq. 8 and compared.

3 Results and Discussions

The effect of Strained-Si, TaN/HfO2 /Ge and Pt/ZrO2 /Ge gate stacks on tran-
sistor parameters is studied first and compared with traditional gate stack
Polysilicon/SiO2 /Si. TaN/HfO2 /Ge and Pt/ZrO2 /Ge gate stacks are used
because there is fabricated data in various literatures. For all simulations
except for active load CSA and differential amplifier design W/L ratio is taken
as 125µ/5µ, Vgs = 1.2 V, Vth = 0.3V. The extracted electron mobility at
0.6 MV/cm for TaN/HfO2 /Ge is 215 cm2 /V s [18], Pt/ZrO2 /Ge is 275 cm2 /V s
[13], polysilicon/SiO2 /Si is 260 cm2 /V s [19] and for strained-Si is 450 cm2 /V s
[17]. The effect of Strained-Si, TaN/HfO2 /Ge and Pt/ZrO2 /Ge gate stacks on
 Assessing the Performance of CMOS Amplifiers 285

transistor parameters is studied first and compared with traditional gate stack
Polysilicon/SiO2 /Si.
The transistor parameters such as saturation current, transconductance
which effect CSA characteristics are compared and tabulated (Table 1) for var-
ious combinations of gate stack (Fig. 4) whose thickness is taken with respect
to 1 nm EOT of SiO2 . The effect of the increase in mobility can be clearly
observed from this simulation. Increase in transconductance and saturation cur-
rent is tremendous compared with traditional MOS structure. From the Table 1,
it can be found that as thickness is reduced and mobility is increased, transistor
performance can be improved.

Fig. 4. Transistor parameter analysis

Table 1. Analysis on Transistor Parameters with respect to oxide thickness

Gate stack materials gm (mA/V) Id (mA)

Polysilicon/SiO2 /Si 20.2 9.1
TaN/HfO2 /Ge 16.7 7.5
Pt/ZrO2 /Ge 21.4 9.6
Strained-Si 28 13.1

The frequency response of common stage amplifier (CSA) is done with the
resistive load and active load (Fig. 5) and compared (Table 2). Depending on
gain and bandwidth, R load is taken as 100 ohms. From the Table 2 it can be
observed that for smaller R load, gate stacks under consideration can give gain
which is comparable with traditional gate stack. It can be observed that by
using germanium substrate and strained-Si, and with the incorporation of high-
k/metal gate as the gate oxide and gate electrode, we can obtain gain which is
comparable with traditional device. From the Table 2, it can be observed that
for R load, strained-Si gives higher gain than traditional gate stack. It is because
286 D. Anand et al.

Fig. 5. Frequency response of CSA

Table 2. Comparison of frequency response of CSA (R Load and Active Load) and
Differential Amplifier

Gate stack materials R Load Active Load Differential amplifier

Polysilicon/SiO2 /Si 6.11 dB 19.9 dB 25.9dB
TaN/HfO2 / Ge 4.46 dB 18.1 dB 24.1 dB
Pt/ZrO2 /Ge 6.61 dB 8.15 dB 14.2 dB
Strained-Si 8.95 dB 9.43 dB 15 dB

of higher mobility. TaN/HfO2 /Ge combination gives lesser gain compared with
traditional gate stack because of lower mobility as compared to traditional one.
The frequency response of CSA with active load depends on device parame-
ter as discussed in the above section. By curve fitting method, lambda values for
nMOS and pMOS are obtained from the fabricated results of Id − Vds charac-
teristics of strained-Si [17], TaN/HfO2 /Ge gate stack [15], Pt/ZrO2 /Ge [13] and
Polysilicon/SiO2 /Si from Cadence result. Lambda values obtained for nMOS
and pMOS devices with TaN/HfO2 /Ge are 0.185 V −1 and 0.0925 V −1 for W/L
ratio 400 µ/10 µ, for Pt/ZrO2 /Ge are 0.58 V −1 and 0.29 V −1 with W/L ratio
320µ/2µ, for strained-Si are 0.5 V −1 and 0.25 V −1 with W/L ratio 0.3 µ/70 nm
and for traditional device 0.15 V −1 and 0.075 V −1 with W/L ratio 125 µ/10 µ.
From the results of λ it can be observed that as length decreases λ value increases
(Strained-Si and Pt/ZrO2 /Ge) which affects the gain. Also, as Ge substrate is
showing higher λ value because of short channel effect compared with tradi-
tional gate stack, gain for poly/SiO2 /Si is higher compared to gate stacks under
consideration (Table 2).
From the above results, it can be observed that strained-Si gives better results
for transistor characteristics such as saturation current, transconductance com-
pared to traditional substrate because of its higher mobility. The gain of CSA
(R load) with strained-Si gives a better result. But in active load TaN/HfO2 /Ge
 Assessing the Performance of CMOS Amplifiers 287

gives better result compared to all other proposed combinations. The gain for
TaN/HfO2 /Ge gate stack is slightly lesser than Poly/SiO2 /Si, it is because of
channel length modulation coefficient λ. Gate stack using Pt/ZrO2 /Ge gives
good results but active load gain is less compared to other combinations because
of high channel length coefficient.
As done in the above section, frequency response of differential amplifier for
different gate stacks is obtained (Fig. 6). From the results (Table 2), it is observed
that TaN/HfO2 /Ge gate stack can give better gain for differential amplifier
design comparing with traditional gate stack even under the high short channel
effect (λ). As length is getting decreased short channel effect gets increased in Ge
substrate compared to Si substrate. Even under this high short channel effect,
the gate stack using Ge substrate is giving better gain.

Fig. 6. Frequency response of differential amplifier

UGB is obtained for various combinations and tabulated (Table 3). It can
be observed that the gate stack which gives higher gm gives higher UGB. The
UGB obtained for strained-Si is higher than traditional gate stack. But as gain
and bandwidth become key parameters for amplifier applications, TaN/HfO2 /Ge
gate stack outperformed all other proposed stacks.
When power consumed for various gate stacks were calculated it was found
that TaN/HfO2 /Ge gate stack consumes less power (Table 3).
From all the above results it can be concluded that TaN/HfO2 /Ge gives
better frequency response for active load and differential amplifier under less

Table 3. Comparison of Unity Gain Bandwidth and power consumption for various
gate stacks

Gate stack materials UGB Power

Polysilicon/SiO2 /Si 20.2 GHz 10.92 mW
TaN/HfO2 /Ge 16.7 GHz 9 mW
Pt/ZrO2 /Ge 21.4 GHz 11.52 mW
Strained-Si 29.13 GHz 15.72 mW
288 D. Anand et al.

power consumption and low leakage current compared to traditional gate stack
and other gate stacks under consideration.

4 Conclusion
Transistor parameters such as transconductance, saturation current, oxide capac-
itance using different metal gate/high-k with Ge substrate and strained-Si has
been analyzed and compared with traditional gate stack Polysilicon/SiO2 /Si.
Simulation results for the frequency response of CMOS CSA (R load and Active
load) using different metal gate/high-k with Ge substrate and strained-Si has
been analyzed and compared with traditional gate stack Polysilicon/SiO2 /Si.
The work has been extended to differential amplifier design and found that
TaN/HfO2 /Ge gate stack gives similar performance as that of traditional gate
stack while maintaining an improved reliability and lower leakage. Also, as
TaN/HfO2 /Ge gate stack consumes lesser power, it can be a good option for
future design of amplifiers. This work can be extended to fabrication of ampli-
fiers using the above gate stack combinations and compare the simulation results
with the fabricated results.

References
1. Mack, C.A.: Fifty years of Moore’s law. IEEE Trans. Semicond. Manuf. 24(2),
202–207 (2011)
2. Ravindran, A., Balamurugan, K., Jayakumar, M.: Design of cascaded common
source low noise amplifier for s-band using transconductance feedback. Indian J.
Sci. Technol. 9(16) (2016)
3. Vinod, B., Balamurugan, K., Jayakumar, M.: Design of CMOS based reconfig-
urable LNA at millimeter wave frequency using active load. In: ICACCCT 2014,
IEEE-Explore, pp. 713–718 (2014)
4. Seshan, K.: Limits and hurdles to continued CMOS scaling. In: Handbook of Thin
Film Deposition. 4th edn. Science Direct (2018)
5. He, G., Zhu, L., et al.: Integrations and challenges of novel high-k gate stacks in
advanced CMOS technology. In: Progress in Materials Science. Elsevier (2011)
6. Gardner, M.I., Gopalan, S., et al.: EOT Scaling and Device Issues for High-k Gate
Dielectrics. IEEE (2003)
7. Gopalan, S., Onishi, K.: Electrical and physical characteristics of Ultrathin
Hafnium Silicate films with polycrystalline silicon and TaN gates. Appl. Physics
Lett. 80(23), 4416–4418 (2002)
8. Wilk, G.D., Wallace, R.M., Anthony, J.M.: Hafnium and zirconium silicates for
advanced gate dielectrics. J. Appl. Phys. 15(1), 484 (2000)
9. Nam, S.-W.: Characteristics of ZrO2 films with Al and Pt gate electrodes. J. Elec-
trochem. Soc. 150, G849–G853 (2003)
10. Frank, M.M.: High-k/metal gate innovations enabling continued CMOS scaling.
In: Solid-State Device Research Conference (ESSDERC) (2011)
11. Pillarisetty, R.: Academic and industry research progress in germanium nanode-
vices. Nature 479(7373), 324 (2011)
12. Razavi, B.: Design of Analog CMOS ICs. McGraw-Hill (2001)
 Assessing the Performance of CMOS Amplifiers 289

13. Chui, C.O., et al.: A Sub-400o C Germanium MOSFET Technology with High-K
Dielectric and Metal Gate. IEEE (2002)
14. Chau, R.: High-k/metal-gate stack and its MOSFET characteristics. IEEE Elec-
tron. Dev. Lett. 25(6), 408–410 (2004)
15. Whang, S.J., et al.: Germanium’p- and n-MOSFETs Fabricated with Novel Surface
Passivation (plasma-PH3 and thin AIN) and TaN/HfO2 Gate Stack. IEEE (2004)
16. Del Alamo, J.A.: Nanometre-scale electronics with III-V compound semiconduc-
tors. Nature 479, 317–323 (2011)
17. Hwang, J.R., et al.: Performance of 70 nm strained-silicon CMOS devices. In:
Symposium on VLSI Technology Digest of Technical Papers (2003)
18. Wu, N., et al.: Characteristics of Self-Aligned Gate-First Ge p- and n-Channel
MOSFETs Using CVD HfO2 Gate Dielectric and Si Surface Passivation. IEEE
(2007)
19. Robertson, J., Wallace, R.M.: High-K materials and metal gates for CMOS appli-
cations. In: Materials Science and Engineering R. Elsevier (2015)