Soft-Switching in DC-DC Converters:

Principles, Practical Topologies,

Design Techniques, Latest Developments

Raja Ayyanar
Arizona State University
Ned Mohan
University of Minnesota
Eric Persson
International Rectifier
Some of the slides in this presentation are used for the course EE5741 Advanced Power Electronics given by Prof Robbins and Prof Mohan at the University of Minnesota

© 2002, N. Mohan, R. Ayyanar, E. Persson APEC 2002 1

 Objectives

• What is soft-switching?
• Basic principles
• Concentration on a few
popular topologies
• Design techniques
• Computer simulations
• New developments

2
 What is Soft-Switching
• Switching transitions occur under favorable
conditions – device voltage or current is zero
• Reduced switching losses, switch stress,
possibly low EMI, easier thermal management
• A must for very high frequency operation,
(also medium frequency at high power levels)

• Usually involves compromises in conduction loss,

switch rating, passive components etc.

4
 Relationship Between Efficiency
and Power Density
500
500
450

400
400
Pout
η=
350

300
300 Pout + Ploss
η
Power Rating

∴ Pout =
250

Ploss
200
200 Ploss = 20W 1−η
150

100
100
50

Ploss = 10W
00
0.8 0.82 0.84 0.86 0.88 0.9 0.92 0.94 0.96
0 .8 0.84 0.88 0.92 0.96

Efficiency
5
 Hard-Switching
iL iT +
vT
-
Vd
-+
vdiode
+− iL ≈ Io
vgate

vT
idiode

iT vdiode

Ploss

Psw ∝ f s ⎡⎣tc( on ) + tc( off ) ⎤⎦

6
 MOSFET Characteristics
Output characteristics

Cross-sectional view of an n-channel MOSFET

source gate

n+ Cgs n+
p p
Cgd Transfer characteristics
Cds
n−
drain-body
depletion layer

n+

drain

7
 MOSFET Characteristics

Df Io

( )
Vin
C gd iD = f Vgs
RG

C gs
VGG

MOSFET model valid in Variation of capacitances with Vds

active and cutoff regions

8
Simulation of Hard Switching Converters
L2

40nH
I3
D2 1A

80

R3
1m

V1 R2 M1
Ideal diode
50V
IRF150
25.0
IRF150
0
20

vDS
10

vGS
iD
0

gate
input
-10
0s 0.5us 1.0us 1.5us 2.0us 2.5us 3.0us 3.5us 4.0us
V(M1:d)/4 ID(M1)*2 V(R2:2) V(V3:+) 9
Time
 Simulation of Hard Switching Converters
• Diode reverse recovery
55

PARAMETERS:
vds 5A I1

MUR2020R
R_LOAD = 1
40 D5
fs = 100k

V1
100 MUR2020R
20
vgs
R2

MTB20N20E
Io ids M1
10
0
V1 = 0 V4
V2 = 15
TD = 1u
-10 TR = 1n
30.0us 30.4us 30.8us 31.2us 31.6us 32.0us 32.4us 32.8us 33.2us 33.6us 34.0us
-I(R3) V(M1:1)/2 V(M1:2) I(I1) TF = 1n
Time PW = 2u
38.5 38.5 PER = {1/fs}

vds vds MTB20N20E

20.0

ids
20.0
vgs
vgs
Io ids Io
0 0

30.9154us 30.9500us 31.0000us 31.0500us 31.1000us 31.1299us

32.95us 33.00us 33.05us 33.10us 33.15us 33.20us 33.25us 33.30us 33.34us
-I(R3) V(M1:1)/3 V(M1:2) I(I1)
-I(R3) V(M1:1)/3 V(M1:2) I(I1)
Time
Time

10
 Problems of Hard-Switching
• Switching losses
• Device stress, thermal management
• EMI due to high di/dt and dv/dt
• Energy loss in stray L and C

Possible Solutions (combination)

• Snubbers to reduce di/dt and dv/dt
Þ usually no change in losses (unless loss recovery)
• Circuit layout to reduce stray inductances
• Gate drive
Þ circuit layout
Þ turn on / off speeds
• Soft switching to achieve ZVS and/or ZCS
11
 Snubbers
• Passive components (R, L, C) and a diode to shape
switching trajectories
Turn-on snubber (seldom used)
Þ At turn-on
iT
V
+v
- T iT (t ) = d t
Ls
Vd Ls Rs
• low di/dt
• lower turn-on losses in the device
Io • low reverse recovery current

Þ Price to be paid at turn-off

vT • 1/2 LI2 energy dissipated during off interval
0 t • off interval > 2 to 3 times LS/RS time constant
iT • switch voltage rating increases by RSIO
0 t
12
 Turn-off Snubbers
RS
iT
+ DS
iCS † At turn-off
vT CS
-
Vd • while vT builds up
iT = Io − iCS
(iC flows through DS )
Io S

• switch turn-off loss decreases

• lower dv/dt
iT
Io
CS = 0 † Issues at turn-on
C S1 • 1/2 CV2 energy dissipated in RS and switch
C S2 • switch current rating increases by Vd / R S
C S3
00
Vd vT • ON interval > 2 to 3 times RSCS time constant
C S3 > C S2 > C S1

13
 Soft-Switching

• ZVS (Zero Voltage Switching)

• ZCS (Zero Current Switching)

Advantages
- Lower losses (may be !)
- Low EMI (may be !)
- Allows high frequency operation

14
 ZVS (Zero Voltage Switching)
Turn ON Turn OFF

• Switch voltage brought to zero • Low-loss transition

before gate voltage is applied • Parallel capacitor as a
• Ideal, zero-loss transition loss-less snubber

• Preferred scheme for very high frequency

applications using MOSFETs
15
ZCS (Zero Current Switching)
Turn OFF
• Switch current brought to zero
before gate voltage is removed
• Ideal, zero-loss transition

Turn ON
• Low-loss transition
• Series inductor as a loss-less snubber
• Energy in junction capacitance is lost

Best suited for converters with IGBTs due to

tail current at turn-off

16
 ZVS and Hard-Switched Waveforms

Zero-voltage switched Hard-switched

12V vdrain − source

vdrain − source
vgate− source
vgate − source

0V 0V

−12V −12V

17
An Example: Zero Voltage Transition (ZVT)

Synchronous Buck Converter

v
C+
( 0) = 0
v - ( 0 ) = Vd
At t = 0 , T + is turned off C

v +v = Vd
C+ i C+ C-
T+ C+
iL

iL 0
+ D +
Vd
A
− L
− i
T C- +
Vo
-
−
−
C
D
18
 Zero Voltage Transition (ZVT)
Since v +v = Vd Also, i -i = iL
C+ C- C+ C-
dv dv
C+ C-
Cs + Cs =0 ∴ i = -i =
iL
dt dt C+ C- 2
∴ i +i =0
C+ C-
Vd
∴v =0
+
Cs+ i
C+
C+
T
v = Vd
C-
+
iL 0
Vd D+
A
− L
T− i
C- +
Vo
−
−
Cs-
D

• At the end of this charge/discharge interval,

positive iL is carried by D −
• Subsequently, T − is turned on; iL must
reverse direction 19
 Zero Voltage Transition

vvaA ((tt ))
Cs+ i Vd
+ C+
T Vo
iL
+ D + 0
Vd
A t0 t’0 t"0 t1 t1’ t2 t3 t
− L
T− i
C- +
Vo
Cs-
− iL
−
D

0
t

Conducting T + D− T − D+ T+
Devices None None
None

20
Simulation of a ZVT Buck Converter
PARAMETERS:
PulseWidth = 4.5us
TDLY1 = 5.5us
R7 M1
TDLY2 = 0.5us
V7
25 IRF150 L1 Period = 10us

V1 TD = {TDLY1}
21V 20uH
IC = 2A

R8 M2 C2 R6
1000uF
IC = 10V 10.0
V8
25 IRF150

TD = {TDLY2}
ZVT_buck.opj
0
20

gate
vDS input
10

vGS
iL
0

iD
-10

-20
9us 10us 11us 12us 13us 14us 15us 16us 17us
21
V(M2:d)/2 ID(M2)*2 V(M2:g) I(L1)*2 V(V8:+)
Time
 Classification of
Soft-Switching Schemes

• Load Resonant Converters

• Converters with Resonant Switches (Quasi-
resonant, Multi-resonant)
• Resonant Transition Converters
– ZVT and ZCT

22
 Phase Shift Controlled
Full-Bridge Converter (ZVT)
† Makes use of switch capacitances and transformer
leakage inductance and magnetizing current

TA+ TB+
D a+ D +b
+ A Io
Vd a
− b
B −
TA− TB− D a D −b

• Poles A & B switched at nearly 50% duty-cycle

• Output voltage regulation is achieved by phase
modulating the two pole outputs
47
 Switching waveforms
vA

+ D B+ vB
+ +
T
DA
T +
Vd + A B
LlT D a+ D +b
2 − vAB a
ficticious Vin
A
iAB + iL Io
0 v AB
D −A B − b
Vd + −
T T −
A B D a− D −b
2 −
− D B−
iAB

In pole A In pole B
+Vd
T − to T ⇒ v AB =0 T − to T ⇒ v AB = +Vd
A A+ B B+ 0
T to T ⇒ v AB =0 0
A+ A− T to T ⇒ v AB = -Vd
-Vd B+ B−
48
 Transitions - Pole B

TB− to TB+ TB- to TB+

v AB
iAB
TB+
TA+ +
iL D a
+ Io
a
Vd A t
− B b
D −b
TB−
TB+ to TB-
0
• v AB = +Vd • v AB = -Vd
0

• iL stays at I o • iL stays at - I o
49
 Transitions - Pole A

TA+ TB+ +
iL D a v AB TA + to TA-
+ Io iAB
a
Vd
− A b
B
TA− D −b t

T to T ⇒ v AB = 0
A+ A− -Vd

• All four diodes conduct

• Leakage inductance resonates with switch capacitance
• Determination of Tdel critical for ZVS design
• Load dependent ZVS

50
 Methods to increase ZVS range
• Use of external series inductor

+ Lo
iAB +
+
Vin A L B vrect
series Vo
− −
−

vAB Disadvantages
† Loss of volt-sec
iAB
0 higher turns-ratio

higher increased
conduction loss VA ratings
vrect
† Load dependent ZVS
left-leg 51
 Use of magnetizing current

+
i mag
i load + i mag
Vin A B Disadvantages
− † higher conduction loss due to
• peak circulating current
• current through right-leg
vAB i mag MOSFETs
• peak magnetizing current
independent of Vin

2
left − leg
52
 Factors Affecting ZVS

™ ZVS Load Range

™ Capacitance across MOSFETs

– internal and external
™ Leakage inductance
™ Delay time
™ Magnetizing current

ƒ Design of other parameters like Lo, Co, transformer etc

identical to hard switched PWM

53
 Designing for ZVS
MOSFET voltage during critical
turn-on transition
vds

( )
Leq
vds = Vin − I mag _ pk + I refl sin (ω t )
2 Cds
1 t
ω= π
2π Leq Cds 2
LLk 2Cds

Conditions for ZVS

( I mag _ pk + I refl )
Leq
1. ≥ Vin,max
2 Cds
π
2. Tdelay = Leq .2 Cds
2

54
 Designing for ZVS
A Possible Design Approach Using MathCAD
• Sweep for all practical values of
Cds - based on limiting voltage rise during turn-off
Tdelay - as a percentage of switching period
• Calculate required Imag,pk and Llk for each set

• Calculate switch peak current and RMS current

Turn-off loss Conduction loss

• Calculate total losses. Iterate for different ZVS ranges

55
 Designing for ZVS

Total
Losses
(W)

j i

j ⇒ Cds
i ⇒ Tdel
Total_loss
56