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CAUTION:
International Rectifier recommends the following guidelines for safe operation and
handling of IRAUDAMP9 demo board:
Applications
Specifications
General Test Conditions (unless otherwise noted) Notes / Conditions
Supply Voltages ±75V
Load Impedance 2Ω
Self-Oscillating Frequency 300kHz No input signal, Adjustable
Gain Setting 33dB 1Vrms input yields 1-kW
sinusoidal output power
Physical Specifications
Dimensions 7.76”(L) x 5.86”(W) x 2.2”(H)
192 mm (L) x 149mm (W) x 56mm(H)
Weight 0.54kgm
3000W,Non-inductive Resistors
2-Ohm
J1 G
S3
CH1 Output J3
J8
VS pins (CH1-O)
S2
Normal
Protection
J6
J7
CH1
Input R100
Volume S1
R130
Test Procedures
Test Setup:
1. Connect 2Ω - 3000 W dummy loads to the output connectors (J1 as shown on Figure 1).
2. Connect the Audio Precision Analyzer (AP) signal Generator output to J7.
3. Initially set the voltages of the dual power supplies to ±75V with current limits to 0.5 A.
4. Make sure to TURN OFF the dual power supplies before connecting to the unit under test
(UUT).
5. Set switch S1 to middle position (self oscillating).
6. Set volume level knob R130 fully counter-clockwise (minimum volume).
7. Connect the dual power supply to J3 as shown in Figure 1.
Power up:
8. Turn ON the dual power supply. The ±B supplies must be applied and removed at the
same time.
9. Red LED (Protection) should turn on almost immediately and turn off after about 3s.
10. Green LED (Normal) then turns on after the red LED is extinguished and should stay ON.
11. Note the quiescent current for the positive supply should be 67mA ±10mA at +75V.
12. Quiescent current for the negative supply should be 105mA ±15mA at –75V.
13. Push switch S3 (Trip and Reset push-button) to restart the LEDs sequence, which should
be the same as noted above in steps 9 and 10.
14. Monitor switching waveform at VS1/J4 (pins 9-12) of CH1 on Daughter Board using an
oscilloscope.
15. For IRAUDAMP9, the self-oscillating switching frequency is pre-calibrated to 300 kHz.
To modify the IRAUDAMP9 frequency, adjust the potentiometer P1 for CH1.
16. Set the current limit of the dual power supplies to ~18A. Make sure the volume control
potentiometer is turned to full counterclockwise position. Apply 1V rms @ 1 kHz from the
Audio Signal Generator to the audio input connector J7.
17. Turn control volume, R130 clock-wise to obtain an output reading of 1.0 kW. For all the
subsequent tests as shown on the Audio Precision graphs below, measurements are taken
across J1 with an AES-17 Filter. Observe that a 1 VRMS input generates an output voltage
of ~44.8 VRMS. Alternatively, a 100-mVrms input would give an output of ~ 10.03W that
corresponds to 4.48Vrms across a 2-ohm load.
18. Using an oscilloscope monitor the output signals at J1 while sweeping the audio input
signal from 10 mVRMS to 2 VRMS. The waveform must be a non distorted sinusoidal signal.
2-ohm
. Cfb filter +B
pF Raa
GNDD Caa
AGND
0V
+VAA Hi-side buffer
npn
0V
C2integrator C1integrator AGND VB Q1n
Q4A Q4B
COMP
nF pF
IRS2092S HO Rgate
Ccomp
Rfreq
0V
IRFB4227 IRFB4227
Dbs
Cbs
Rgate
Rin AGND AGND 0V
INPUT
IN- Q1p
- Modulator VS pnp Vs Vo
and L-out
AGND + Shift level Lo-side buffer
GND AGND Integrator VCC LP Filter Cout
npn
Q2n
LO Q3A Q3B
CSD
AGND Rgate
Heatsink GNDD
IRFB4227 IRFB4227
+VCC Rgate
-VSS COM Q2
Vcc cap
pnp
Css .
AGND -B
Rss
. Trip
D
Green (TO-220
RESET OVP / UVP Case Temp.) DCP HOPS
Red
LEDs OTP
Functional Description
Class-D Operation
The C2integrator, C1integrator, R21 + potentiometer P1 form a front-end second-order integrator. This
integrator receives a rectangular feedback signal from the Class D switching stage and outputs a
quadratic oscillatory waveform as a carrier signal. To create the modulated PWM signal, the input
+B
VB Czobel
C bus filter
Q1n
Rzobel
Cvcc1
Q1p
Rgs3A Rgs3B
Vs Vout
L out filter
VCC
C out filter
R Load
Cvcc2 Q2n
LO
Rg2A Q4A Rg2B Q4B
GND
Q2p
Rgs4A Rgs4B
BJT buffer
Low side
-B
The IRAUDAMP9 has all the necessary housekeeping power supplies onboard and only requires
a pair of symmetric power supplies ranging from ±38 V to ±82 V (+B, GND, -B) for operation. The
internally-generated housekeeping power supplies include a ±5 V supply for analog signal
processing (preamp, etc.), and a +12 V supply (Vcc), referenced to –B, to supply the Class D
gate-driver stage.
For the externally-applied power, a regulated power supply is preferable for performance
measurements, but not always necessary. The bus capacitors, C45 ~ C48 on the motherboard,
along with high-frequency bypass-capacitors C19 ~ C26 on daughter board, address the high-
frequency ripple current that result from switching action. In designs involving unregulated power
supplies, the designer should place a set of bus capacitors, having enough capacitance to handle
the audio-ripple current, externally. Overall regulation and output voltage ripple for the power
supply design are not critical when using the IRAUDAMP9 Class D amplifier as the power supply
rejection ratio (PSRR) of the IRAUDAMP9 is excellent as shown in Figure 9 below.
-75Vbus
Bus Pumping
Since the IRAUDAMP9 is a half-bridge configuration, bus pumping does occur. Under normal
operation during the first half of the cycle, energy flows from one supply through the load and into
the other supply, thus causing a voltage imbalance by pumping up the bus voltage of the receiving
power supply. In the second half of the cycle, this condition is reversed, resulting in bus pumping
of the other supply.
The following conditions worsen bus pumping:
– Lower frequencies (bus-pumping duration is longer per half cycle)
– Higher power output voltage and/or lower load impedance (more energy transfers
between supplies)
– Smaller bus capacitors (the same energy will cause a larger voltage increase)
Input
Input signal is an analog signal ranging from 20Hz to 20kHz with up to 2 VRMS amplitude with a
source impedance of no more than 600 Ω. Input signal with frequencies around 20kHz may cause
LC resonance in the output LPF and may result to a large reactive current flow through the
switching stage, especially if the amplifier is not connected to any load - this can activate OC
protection.
Output
The IRAUDAMP9 has single output and therefore have terminals labeled (+) and (-) with the (-)
terminal connected to power ground. Each channel is optimized for a 2 Ω speaker load for a rated
output power of 1200 W @ 1% THD+N.
It is common in amplifier design to have a RC snubber called Zobel network that is used to damp
the resonance and prevent peaking frequency response with high load impedance. Instead, the
IRAUDAMP9 has a simple detection circuit in placed, which consist of a NPN transistor, blocking
diode and a current limiting resistor to detect the output peak status from exceeding –B supply
during resonance of the output LC filter. This circuit pulls the Cstart capacitor (C66) down to output
(+) that sends a signal to IRS2092S to inhibit the power stage from switching. As the output
returns to unclipped level, the base-to-emitter voltage is reduced and releases the CSD cap to
start charging. This would allow the IRS2092S to resume driving operation of the power stage.
Fig. 11 Shutdown circuit diagram when output goes lower than negative rail.
Efficiency
Figure 12 shows efficiency characteristics of the IRAUDAMP9. The high efficiency is achieved by
the following major factors:
1) Low conduction loss due to the low RDS(ON) of the IRFB4227 mosfets
2) Low switching loss due to the high gate drive output for fast rise and fall times
3) Secure dead-time provided by the IRS2092S, avoiding cross-conduction
90%
80%
Total System Efficiency
70%
Efficiency (%)
60%
50%
40%
30%
20%
10%
0%
0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600
Output filter:
The amplified PWM output is reconstructed back to an analog signal by the output LC LPF.
This LPF is formed by L4 and C34, provides pass band for the audio frequencies while filtering out
the switching carrier signal. A single stage output filter can be used with switching frequencies of
around 300 kHz ; a design with a lower switching frequency may require an additional stage of
filtering.
Since the output filter is not included in the control loop of the IRAUDAMP9, the reference design
cannot compensate for performance deterioration due to the output filter. Therefore, it is important
to select filter components with the following characteristics in mind.
1) The DC resistance of the inductor should be minimized to 6 mΩ or less.
2) The linearity of the output inductor and capacitor should be high with respect to load
current and voltage.
The preamp allows partial gain of the input signal. It is possible to evaluate the performance
without the preamp and volume control, by removing R154 and feeding the input signal directly
through R46 resistors (IN-1). This effectively bypasses the preamp and connects the RCA inputs
directly to the Class D power stage input. Improving the preamp noise performance and the output
filter, will improve the overall system performance approaching that of the stand-alone Class D
power stage.
The self-oscillating frequency is determined by the total delay time inside the control loop of the
system. The delay of the logic circuits, propagation delay of IRS2092S gate-driver, delay caused
by the external buffer, IRFB4227 (x 2 pairs) switching speed, time-constant of front-end integrator
and variations in the supply voltages are critical factors of the self-oscillating frequency. Under
normal conditions, the switching-frequency is around 300 kHz with no audio input signal and a
+/-75 V supply.
Switch S1 is an oscillator selector. This three-position switch is selectable for internal self-
oscillator (middle position – “SELF”), or either internal (“INT”) or external (“EXT”) clock
synchronization.
The IRAUDAMP9 does not use any series relay to disconnect the speaker from the audible
transient noise, but rather depends on IRS2092S’s on-chip noise reduction circuit that yields
audible noise levels that are far less than those generated by the relays they replace. This results
in a more reliable, superior performance system.
CSD= 2/3VDD
CSD
+5 V CStart
Time
-5 V
VCC
UVP@-38 V
-B
CH1_O
Audio MUTE
Figure 13, Conceptual Startup Sequencing of Power Supplies and Audio Section Timing
For startup sequencing, +/-B supplies startup at different intervals. As +/-B supplies reach +5 V
(Vaa) and -5 V (Vss) respectively, the analog supplies (Vaa, Vss) start charging and, once +B
CSD= 2/3VDD
CSD
CStart +5 V
Time
-5 V
VCC
-B
UVP@-38 V
CH1_O
Audio MUTE
Class D shutdown
Music shutdown
Figure 14. Conceptual Shutdown Sequencing of Power Supplies and Audio Section Timing.
Shutdown sequencing is initiated once UVP is activated. As long as the supplies do not discharge
too quickly, the shutdown sequence can be completed before the IRS2092S trips UVP. Once UVP
is activated, CSD and Cstart are discharged at different rates. In this case, threshold Ref2 is
reached first and the preamp audio output is muted. Once CStart reaches threshold Ref1, the click-
noise reduction circuit is activated. It is then possible to shutdown the Class D stage (CSD
reaches two-thirds VDD). This process takes less than 200 ms.
For any external fault condition (OTP, OVP, UVP or DCP – see “Protection”) that does not lead to
power supply shutdown, the system will trip in a similar manner as described above. Once the
fault is cleared, the system will reset (similar sequence as startup).
CSD= 2/3VDD
CSD
CStart
Time
External trip
Reset
CH1_O
Audio MUTE
Figure 15. Conceptual Click Noise Reduction Sequencing at Trip and Reset
R41
VB
R25
Q4A Q4B
1.2V Rgate
HO
Hi-side buffer IRFB4227 IRFB4227 0V
Rgate
0V
Q1p
VS
pnp Vs Vo
. CSD L-out
CSD
VCC LP Filter Cout
npn
Q2n
LO Q3A Q3B
OCSET
Rgate
OCREF Heatsink GNDD
Lo-side buffer
IRFB4227 IRFB4227
Rgate
Q2
R19 R17
5.1V pnp
-B
TO-220
D4
The external shutdown circuit will disable the output by pulling down CSD pins . If the fault
condition persists, the protection circuit stays in shutdown until the fault is removed.
The low-side current sensing feature protects the low side MOSFET from an overload condition
from negative load current by measuring drain-to-source voltage across RDS(ON) during its on state.
OCP shuts down the switching operation if the drain-to-source voltage exceeds a preset trip level.
An external resistive divider R17 and R19 on the daughter board are used to program the low-side
OCP trip point.
High-side over-current sensing monitors drain-to-source voltage of the high-side MOSFET during
the on state through the CSH and VS pins. The CSH pin detects the drain voltage with reference
to the VS pin, which is the source of the high-side MOSFET. In contrast to the low-side current
sensing, the threshold of the CSH pin to trigger OC protection is internally fixed at 1.2V. An
external resistive divider, R41 and R43 are used to program a hi-side OCP trip point. An external
reverse blocking diode D8 is required to block high voltage feeding into the CSH pin during low-
side conduction. By subtracting a forward voltage drop of 0.6V at D1, the minimum threshold
which can be set for the high-side is 0.6V across the drain-to-source.
Thermal Considerations
Due to limited heat sink size, the IRAUDAMP9 is designed for high efficiency to deliver 1 kW rated
power for 1 minute at open-air room temperature ( starting w/ Tamb: ~22 - 25C)
However, the IRAUDAMP9 requires larger heatsink design to handle one-eighth of the continuous
rated power, which is generally considered to be a normal operating condition for safety
standards. If the user decides to increase the size of the heatsink or have a minimum forced air-
cooling, the daughter board can handle continuous rated power.
Figure 17. Thermal image of the heatsink assembly during 1/8 rated power burn-in test.
Figures 18-19 show over current protection reaction time of the IRAUDAMP9 in a short circuit
event. As soon as the IRS2092S detects an over current condition, it shuts down PWM. After one
second, the IRS2092S tries to resume the PWM. If the short circuit persists, the IRS2092S repeats
try and fail sequences until the short circuit is removed.
VS pin Load
CSD pin
VS pin Load current
current
VS pin
Figure 18. Positive-side OCP waveforms during short circuit test at 10W load condition.
-5V
-B
+B INLEFT
+B
-B
SD VCC
+5V
CH1 O POWER GND
INLEFT GND
-5V
U_AMP9_SYNC_PS
AMP9_SYNC_PS Rev1.0.Sch
SYNC
GND
POWER GND
+5V
-5V
VCC
-B
+B
SD
C64 C65 33K
1CLR 2CLK 10uF, 16V 0.1uF, 16V
10uF, 16V 0.1uF, 16V U14 +5V
R84
OE VDD 1QA 2CLR R85
S1A 10K
SW D19 68k Z7 R86 Z8
GND OUT 1QB 2QA 47K
E
S
Trip-Restart
I
U_1 C67 S3
MMBT5551 MMBT5551
SW-PB
1A VCC R95 R96
0.1uF, 100V
R97 47K 47K
SW-3WAY_A-B
1Y 6A 68k
R98 R99
100R 2A 6Y OVP
SYNC 10k -B Trip and restart
2Y 5A +B +B
R101 R100
J6 5K POT C68
47R 3A 5Y C69 -B -B
BNC R102
10uF, 16V 0.1uF, 16V R103
330R 3Y 4A 82k -5V -5V
C70
EXT. CLK 100pF, 50V GND 4Y +5V +5V
74HC14
POWER GND
CLK1 +5V
R104 +B
S2A 1K GND
S NORMAL1
O R105
SW
R106 Q10
T 47K
MMBT5401
1K R111
SW-3WAY_A-B PROTECTION1
47K
R107 R108
CLK2
MUTE 100K
47R
R110
5.76k
Q12
R132
J9 CH2 R112 MMBT5551
100K
CH1 O
CH2 O
1418-ND 100K
DC protection
GND R113
u
n
s
t
u
f
f
f
o
r
A
M
P
9
5.76k
DCP
R116
100K R117 R118 R119
R131 100K C71 100K 100K
R156 R120
100R 330uF, 16V R121
U_3 open 5.76k
R123 Q13 1k
ZCEN AINL
47K MMBT5401
R133 47R
CS
CS CS AGNDL
R134 47R C77 +5V R124
SDATAI SDATAI SDATAI AOUTL INRIGHT R126 5.76k
10uF, 50V -5V
R115 10R R128 0R0 C78 5.76k
C79 R127
+5V VD+ VA- -5V 0.1uF, 16V
C1 U_2 Q14 R153
R122 0R0 10uF, 16V 5.76k
10uF, 50V MMBT5551 P1
DGRD VA+ +5V 8 1
VSS VDD 0R0
1 6 J8
R135 C75 +5V R130 R129
SCLK SCLK AOUTR INLEFT 7 2 CS 2 5
10uF, 50V CT2265 VR0 CS CS 2
47R 47K 3 4
SDATAI 1
SDATAO AGNDR 6 3
VR1 SDATA SDATAI
C80 -B N/A N/A
MUTE MUTE AINR 10nF, 50V 5 4
CLK SIMUL
CS3310 R114 R157
100R open 3310IR02
SCLK
SCLK
R109
J7
100K CH1
1418-ND
INLEFT_1
C32
L4
CH1J1 OUT
CH1 O
150pF
C33 22uH
INLEFT
R154 R40 CH1 IN R38 100K R39 1K
1
1K 3.3K C37 2
10uF, 50V
C34
Trip-Restart
C72 R43 OPEN 277-1022
2.2uF, 275V
2.2nF R45A 2.2k
47k
-B
Q9A
MMBT5551
D5A
1
PWM1
+B +B
2
VSS -5V
1
CH2 O VSS for AMP9 -B -B
CH2 O
2 3
CH2 O SIGNAL GND1
+B 3
CH2O VCC VCC
4 4
CH2 O SIGNAL GND1
5
-B +5V +5V
6 5
C45 C46 -B SIGNAL GND1 -B
7
R58 R59 -B -5V -5V
1200uF, 100V 1200uF, 100V 8 6 VSS for AMP9
200K 200K -B NC -5V
9
CH1 O D23 POWER GND
10 7
CH1 O
C47 C48 CH1 O VCC VCC RS1DB
J3 11
CH1 O
1200uF, 100V 1200uF, 100V 12 8
3 CH1 O SIGNAL GND2 GND
13
2 +B
-B 14 9
1 +B SIGNAL GND2
15
+B VAA for AMP9
277-1272 16 10
+B VAA +5V
J4 11
SD SD
12
PWM2
+5V +5V
B Z1
R3
C3 C4 SYNC SYNC R4 15V
10K
Z2 4.7uF, 100V 1uF, 100V R147 Q18 10R
56V PZT2222A POWER GND
10R For AMP9
Q2
C E
+5V R5
GND
C
For AMP9 Q3 10K
FZT855TA
MMBTA92
B
R6
B
C2
+B 10uF, 16V SD3
20k
Z10 R7
E
5.6V Z3 10K Z4
U3 C6 C7 56V 5V
4.7uF, 100V 1uF, 100V
VCC BST
C11 -B
SD PRE 0.022uF, 50V L2
R146 R141 7V
47.5k VIN SW
SYNC3 0R0 C10 U2
R12 R14 470uH R15 0.470uF, 16V
SYNC IS 10R 4.7k 1% VCC BST
47R D2 SD3
B180 C9
COMP PGND C16 C86 SD PRE 0.022uF, 50V L1 12V
R17 4.7uF, 50V 4.7uF, 100V R151 R150
18.7k FB OUT VIN SW VCC
SYNC1 0R0
R18 R144 R8 R9 470uH R10 4.7R
C13 RT SS 1.00k 1% 47.5k SYNC IS 10R 8.66k
47R D1
0.470uF, 16V B180
R19 RAMP AGND C19 C20 COMP PGND
20.5k LM5574 0.0082uF, 50V 330pF, 100V R11 C12 C84 C35 C83
C21 18.7k FB OUT
0.0068uF, 50V R13 4.7uF, 50V 4.7uF, 100V 10uF, 16V 10uF, 16V
C22 RT SS 1.00k
0.0022uF, 100V
R16 RAMP AGND C14 C15
20.5k LM5574 0.0082uF, 50V 330pF, 100V
C17
0.0068uF, 50V
C18
0.0022uF, 100V
-B
D3
B1100
C23 C24
4.7uF, 100V 1uF, 100V
U4
VCC BST
C25
SD PRE 0.022uF, 50V L3
R145 R148
47.5k VIN SW
SYNC2 0R0
R29 R30 470uH R31
SYNC IS 10R 4.7k 1%
47R D4
B180
COMP PGND C27 C85
R32 4.7uF, 50V 4.7uF, 100V
18.7k FB OUT
R36 Q20 PZT2907AT1
C26 RT SS 1.00k 1% R149
0.470uF, 16V -5V
RAMP AGND 10R
R37 C28 C29
20.5k LM5574 0.0082uF, 50V 330pF, 100V For AMP9
C30
0.0068uF, 50V
C31 R142
0.0022uF, 100V -B C82
20k
10uF, 16V
-7V -Vout_PS Z12
5.6V
R52
+75V Bus
R104 715R
SD Q101 75k C33
Q100
4.7k OTP1 0.47 uF 250V
TH1
R45 Rp1
C100
0R ZXTN25100BFH 0R C34
OPTIONAL-
0.1uF
R105 10k
R101 4.7k TH2.2k C18 R40
33k (Unstuff for
0.47 uF 250V CH1 Output
3.3uF R43 C32
1kW-AMP9) to LPF
VSS 2.2uF Q9
R102 10k 3.6k D1 CH1 O
C37
J2-A +B
R7 10R +5V R25 1 nF
1 16 R41
VAA VAA CSH 10K Q6A R23B Q6B R23C Q6C 1 16
1K 5.6k R23A 2 15
Audio Gnd 1 VB 4.7R 4.7R
P1 R21 470 4.7R 3 14
2 15
GND1 GND VB 4 13
Q8 R37
0R 5 12
CH1- input 3 14 IRFB4227 IRFB4227 IRFB4227
10R 6 11
IN-1 IN- HO 7 10
R46 C5 R32 R22A R22B R22C
C21 C23 C1 D6 8 9
1nF 1nF 1nF 22uF ZXTP25100BFH 10K 10K 10K
3.01k C30 4 13 A26578-ND
COMP VS
J1-A
10nF
1 4 D4 R1 R26 Heatsink
5 12
2 5 CSD VCC 4.7R VCC
0R
3 6 100R C36
C10 10uF
-5V ZXTN25100BFH 1 nF
A26568-ND 6 11 J2-B -B
VSS LO R44
R3 Q3 1 16
0R R21A Q5A R21B Q5B R21C Q5C
R19 C31 2 15
7 10 4.7R 4.7R
10R VREF COM 2.2uF 4.7R 3 14
VSS 8.2k R36
R30 4 13
-B 10R
C12 R9 5 12
8 9
3.3uF OCSET DT 6 11
VCC 10R
VAA U1 IRS2092S R12 IRFB4227 IRFB4227 IRFB4227 C35 7 10
J1-B OCset
4.7K 0.1uF 8 9
7 10 R50 R5 R20A R20B R20C
A26578-ND
8 11 75k 10K
open 10K 10K
9 12 R17 R35
SD
C3 1R
A26568-ND D7 R13 Q2
2.2k
GND2 3.3K 10uF DS1 ZXTP25100BFH
-75V Bus
-75V Bus
-B
Additional files for assembly that may not be related with Gerber files:
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105
Data and specifications subject to change without notice. 03/25/2011