Aditya Engineering College (A) Aditya Engineering College (A)

ADITYA ENGINEERING COLLEGE (A)
EMBEDDED SYSTEMS
K.PAVANI
Associate Professor
Department of Electronics and Communication Engineering
Aditya Engineering College (A)
Email: pavani.k@aec.edu.in
EMBEDDED FIRMWARE DESIGN

(UNIT-III)
K.PAVANI
Associate Professor
Unit-3 Outcomes
At the end of the Course, Student will be able to:

CO 3 : Construct the firmware for an embedded systems by various design approaches
Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

Contents
Embedded Firmware design approaches
Embedded Firmware development languages
Interrupt sources
ISR concept
Interrupt servicing mechanism
Multiple interrupts
DMA
Device driver programming
Concepts of C versus Embedded C.
Embedded Firmware Design Approaches
K.PAVANI
Sr.Assistant Professor
Learning Outcomes
At the end of this lecture, Student will be able to:
LO 1 :Understand the various approaches for design of Embedded Firmware

Embedded Firmware
• The embedded firmware is responsible for controlling the various

peripherals of the embedded hardware and generating response in
accordance with the functional requirements of the product.
• The embedded firmware is the master brain of the embedded system.
• The embedded firmware imparts intelligence to an Embedded system.
• It is a one time process and it can happen at any stage.

• The product starts functioning properly once the intelligence imparted
to the product by embedding the firmware in the hardware.
• The product will continue serving the assigned task till hardware
breakdown occurs or a corruption in embedded firmware.
• In case of hardware breakdown , the damaged component may need to

be replaced and for firmware corruptions the firmware should be re-
loaded, to bring back the embedded product to the normal functioning.

• The embedded firmware is usually stored in a permanent memory

(ROM) and it is non alterable by end users.
• Designing Embedded firmware requires understanding of the

particular embedded product hardware, like various component
interfacing, memory map details, I/O port details, configuration and
register details of various hardware chips used and some programming
language (either low level Assembly Language or High level language
like C/C++ or a combination of the two)

The embedded firmware development process starts with the
conversion of the firmware requirements into a program model
using various modeling tools.
The firmware design approaches for embedded product is
purely dependent on the complexity of the functions to be
performed and speed of operation required.

Embedded Firmware design approaches
There exist two basic approaches for the design and implementation of embedded
firmware, namely;
 The Super loop based approach(Conventional Procedural Based Firmware Design)

 The Embedded Operating System based approach
The decision on which approach needs to be adopted for firmware development is

purely dependent on the complexity and system requirements

The Super loop based approach
The Super loop based firmware development approach is Suitable for

applications that are not time critical and where the response time is not so
important (Embedded systems where missing deadlines are acceptable).
It is very similar to a conventional procedural programming where the code is
executed task by task
The tasks are executed in a never ending loop
The task listed on top on the program code is executed first and the tasks just
below the top are executed after completing the first task

A typical super loop implementation will look like:
1. Configure the common parameters and perform initialization for various hardware components memory,
registers etc
2. Start the first task and execute it
3. Execute the second task
4. Execute the next task
5. .
6. .
7. Execute the last defined task
8. Jump back to the first task and follow the same flow.

The ‘C’ program code for the super loop is given below
void main ()
{
Configurations (); Initializations ();
while (1)
{
Task 1 ();
Task 2 ();
:
:
Task n ();
}
}

Advantages:
 Doesn’t require an Operating System for task scheduling and monitoring and
free from OS related overheads.
 Simple and straight forward design.
 Reduced memory footprint.

Cons:
Non Real time in execution behavior (As the number of tasks increases the
frequency at which a task gets CPU time for execution also increases)
Any issues in any task execution may affect the functioning of the product
(This can be effectively tackled by using Watch Dog Timers for task execution
monitoring)
Enhancements:
Combine Super loop based technique with interrupts
Execute the tasks (like keyboard handling) which require Real time attention as
Interrupt Service routines.
Embedded OS based Approach
• The embedded device contains an Embedded Operating System which can be one
of:
 A Real Time Operating System (RTOS)

 A Customized General Purpose Operating System (GPOS)

• The Embedded OS is responsible for scheduling the execution of user tasks and
the allocation of system resources among multiple tasks
• It Involves lot of OS related overheads apart from managing and executing user
defined tasks
• Microsoft® Windows XP Embedded is an example of GPOS for embedded
devices
• Point of Sale (PoS) terminals, Gaming Stations, Tablet PCs etc are examples of
embedded devices running on embedded GPOSs
• ‘Windows CE’, ‘Windows Mobile’ , ‘QNX’, ‘VxWorks’, ‘Thread X’, ‘Micro C/OS-
II’, ‘Embedded Linux’, ‘Symbian’ etc are examples of RTOSs employed in
Embedded Product development
• Mobile Phones, PDAs, Flight Control Systems etc are examples of embedded
devices that runs on RTOSs

Embedded Firmware development languages
K.PAVANI
Learning Outcomes
LO 1 :Learn Various development languages to design Embedded Firmware

Embedded firmware Development Languages

1. Assembly Language
2. High Level Language

Subset of C (Embedded C)
Subset of C++ (Embedded C++)
Any other high level language with supported Cross-
compiler
3. Mix of Assembly & High level Language

 Mixing High Level Language (Like C) with Assembly
Code
 Mixing Assembly code with High Level Language (Like
C)
 Inline Assembly
Assembly Language
• ‘Assembly Language’ is the human readable notation of ‘machine language’
• ‘Machine language’ is a processor understandable language
• Machine language is a binary representation and it consists of 1s and 0s .
• Assembly language and machine languages are processor/controller dependent
• An Assembly language program written for one processor/controller family will

not work with others
• Assembly language programming is the process of writing processor specific

machine code in mnemonic form, converting the mnemonics into actual processor
instructions
Embedded Systems
(machine language) and associated data using an assembler
K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23
•The general format of an assembly language instruction is an Opcode followed by

Operands
•The Opcode tells the processor/controller what to do and the Operands provide
the data and information required to perform the action specified by the opcode
•It is not necessary that all opcode should have Operands following them. Some of
the Opcode implicitly contains the operand and in such situation no operand is
required. The operand may be a single operand, dual operand or more
•The 8051 Assembly Instruction MOV A, #30

• Assembly language instructions are written one per line

• A machine code program consists of a sequence of assembly language
instructions, where each statement contains a mnemonic (Opcode +
Operand)
• Each line of an assembly language program is split into four fields as:
LABEL OPCODE OPERAND COMMENTS
DELAY:MOV AX,BX
INC CX
JNC DELAY

• LABEL is an optional field. A ‘LABEL’ is an identifier used extensively
in programs to reduce the reliance on programmers for remembering
where data or code is located. LABEL is commonly used for representing
• A Memory location, address of a program, sub-routine, code portion.
• Labels are always suffixed by a colon and begin with a valid character
DELAY: MOV R0, #255; Load Register R0 with 255
• The symbol ; represents the start of a comment. Assembler ignores the
text in a line after the ; symbol while assembling the program
• DELAY is a label for representing the start address of the memory
location where the piece of code is located in code memory
• The above piece of code can be executed by giving the label DELAY as
part of the instruction. E.g. LCALL DELAY; LMP DELAY

Assembly Language – Source File to Hex File Translation

• The Assembly language program written in assembly code is saved as .asm (Assembly file) file
or a .src (source) file or a format supported by the assembler
• Similar to ‘C’ and other high level language programming, it is possible to have multiple
source files called modules in assembly language programming. Each module is represented by
a ‘.asm’ or ‘.src’ file or the assembler supported file format similar to the ‘.c’ files in C
programming
• The software utility called ‘Assembler’ performs the translation of assembly code to machine
code
• The assemblers for different family of target machines are different. A51 Macro Assembler
from Keil software is a popular assembler for the 8051 family micro controller


• Each source file can be assembled separately to examine the syntax errors and incorrect assembly
instructions
• Assembling of each source file generates a corresponding object file. The object file does not contain
the absolute address of where the generated code needs to be placed (a re-locatable code) on the
program memory
• The software program called linker/locater is responsible for assigning absolute address to object
files during the linking process
• The Absolute object file created from the object files corresponding to different source code modules
contain information about the address where each instruction needs to be placed in code memory
• A software utility called ‘Object to Hex file converter’ translates the absolute object file to
corresponding hex file (binary file)

Advantages
1.Efficient Code Memory & Data Memory Usage (Memory Optimization):
 The developer is well aware of the target processor architecture and
memory organization, so optimized code can be written for performing
operations.
 This leads to less utilization of code memory and efficient utilization of
data memory.
2.High Performance:
 Optimized code not only improves the code memory usage but also
improves the total system performance.
 Through effective assembly coding, optimum performance can be
achieved for target processor.

3.Low level Hardware Access:

 Most of the code for low level programming like accessing
external device specific registers from OS kernel ,device drivers,
and low level interrupt routines, etc are making use of direct
assembly coding.
4.Code Reverse Engineering:

 It is the process of understanding the technology behind a product
by extracting the information from the finished product.
 It can easily be converted into assembly code using a dis-
assembler program for the target machine.

Drawbacks:
1. High Development time:
 The developer takes lot of time to study about architecture ,memory organization, dressing modes and
instruction set of target processor/controller.
 More lines of assembly code is required for performing a simple action.

2. Developer dependency:
 There is no common written rule for developing assembly language based applications.
3.Non portable:
 Target applications written in assembly instructions are valid only for that particular family of
processors and cannot be re-used for another target processors/controllers.
 If the target processor/controller changes, a complete re-writing of the application using assembly
language for new target processor/controller is required.

High Level Language

• The embedded firmware is written in any high level language like C, C++
• A software utility called ‘cross-compiler’ converts the high level language to target processor
specific machine code
• The cross-compilation of each module generates a corresponding object file. The object file does
not contain the absolute address of where the generated code needs to be placed (a re-locatable
code) on the program memory
• The software program called linker/locater is responsible for assigning absolute address to object
files during the linking process
• The Absolute object file created from the object files corresponding to different source code
modules contain information about the address where each instruction needs to be placed in code
memory
• A software utility called ‘Object to Hex file converter’ translates the absolute object file to
corresponding hex file (binary file)

High Level Language – Source File to Hex File Translation

Advantages
• Reduced Development time: Developer requires less or little knowledge on internal hardware
details and architecture of the target processor/Controller.
• Developer independency: The syntax used by most of the high level languages are universal and a
program written high level can easily understand by a second person knowing the syntax of the
language
• Portability: An Application written in high level language for particular target processor /controller
can be easily be converted to another target processor/controller specific application with little or less
effort

Drawbacks
 The cross compilers may not be efficient in generating the

optimized target processor specific instructions.
 Target images created by such compilers may be messy and
non- optimized in terms of performance as well as code size.
 The investment required for high level language based
development tools (IDE) is high compared to Assembly
Language based firmware development tools.

Mixing of Assembly Language with High Level Language
• Embedded firmware development may require the mixing of Assembly Language

with high level language or vice versa.
• High Level language and low level language can be mixed in three different ways
 Mixing Assembly Language with High level language like ‘C’

 Mixing High level language like ‘C’ with Assembly Language
 In line Assembly

Mixing Assembly Language with High level language like ‘C’
• Assembly routines are mixed with ‘C’ in situations where the entire program is written in ‘C’ and the cross
compiler in use do not have built in support for implementing certain features like ISR.
• If the programmer wants to take advantage of the speed and optimized code offered by the machine code
generated by hand written assembly rather than cross compiler generated machine code.
• For accessing certain low level hardware ,the timing specifications may be very critical and cross
compiler generated machine code may not be able to offer the required time specifications accurately.
• Writing the hardware/peripheral access routine in processor/controller specific assembly language and
invoking it from ‘C’ is the most advised method.

Mixing ‘C’ and assembly is little complicated.

• The programmer must be aware of how to pass parameters from the ‘C’ routine to assembly and values
returned from assembly routine to ‘C’ and how Assembly routine is invoked from the ‘C’ code.
• Passing parameter to the assembly routine and returning values from the assembly routine to the caller
‘C’ function and the method of invoking the assembly routine from ‘C’ code is cross compiler dependent.
• There is no universal written rule for purpose.
• We can get this information from documentation of the cross compiler.
• Different cross compilers implement these features in different ways depending on GPRs and memory
supported by target processor/controller

Mixing High level language like ‘ C ’ with Assembly Language
• The source code is already available in assembly language and routine written in a high level language needs
to be included to the existing code.
• The entire source code is planned in Assembly code for various reasons like optimized code, optimal
performance, efficient code memory utilization and proven expertise in handling the assembly.
• The functions written in ‘C’ use parameter passing to the function and returns values to the calling functions.

• The programmer must be aware of how parameters are passed to the function and how values
returned from the function and how function is invoked from the assembly language environment.
• Passing parameter to the function and returning values from the function using CPU registers ,
stack memory and fixed memory.
• Its implementation is cross compiler dependent and varies across compilers.

In line Assembly
• Inline assembly is another technique for inserting the target processor/controller specific assembly
instructions at any location of source code written in high level language ‘C’
• Inline Assembly avoids the delay in calling an assembly routine from a ‘C’ code.
• Special keywords are used to indicate the start and end of Assembly instructions
E.g:
#pragma asm
Mov A,#13H
#pragma end asm

Interrupt Sources
K.PAVANI
Learning Outcomes
LO 1 :Learn how interrupt service routines is used to address and service the device
IOs

Interrupt Sources
Hardware Sources of interrupts

 Hardware Interrupts Related to Internal Devices
 Hardware Interrupts Related to External Devices-1
 Hardware Interrupts Related to External Devices-2
Software Sources of interrupts
 Software Error related Hardware Interrupts
 Software Instruction-Related Interrupt Sources

ISR CONCEPT
Interrupt means event, which invites attention of the processor on occurrence of some action at
hardware or software interrupt instruction event.
In response to the interrupt, the routine or program, which is running presently interrupts and an
interrupt service routine (ISR) executes.
ISR is also called device driver in case of the devices and called exception or signal or trap
handler in case of software interrupts.
Processor executes the program, called interrupt service routine or signal handler or trap
handler or exception handler or device driver, related to input or output from the port or device or
related to a device function on an interrupt and does not wait and look for the input ready or output
completion or device-status ready or set

Hardware interrupt:
When a device or port is ready, a device or port generates an interrupt, or when it completes the assigned action
or when a timer overflows or when a time at the timer equals a preset time in a compare register or on setting a
status flag (for example, on timer overflow or compare or capture of time) or on click of mice in a computer, it
generates an interrupt. This interrupt is called hardware interrupt.
Software Interrupt:
When software run-time exception condition detected , either the processor-hardware or software instruction
generates an interrupt. This interrupt is called Software interrupt or trap or Exception, which calls an ISR


How does call to ISR differ from a function (routine) call?
 On a function call, the instructions are executed from a new address.Execute like in as
function in the ‘C’ or in a method in Java.
 ISR also the instructions are executed from a new address like in as function in the ‘C’ or in a
method in Java
 A function call is after executing present instruction in any program and is a planned (user
programmed) diversion from the present instruction in sequence of instructions to another
sequence of instructions; this sequence of instructions executes till the return from that.
 An ISR call is after executing present instruction in any program and is interrupt related diversion
from the current sequence of instructions to another sequence of instructions; this sequence of
instructions executes till the return from that or till another interrupt of higher priority

 Nesting the function-calls ─ When a function 1 calls another function 2 and that call another function 3, on
return from 3, the return is to function 2 and return from 2 is to function. Functions are said to be nested.
 The ISR calls in case of multiple interrupt occurrences can be nested orcan be as per priority of
the interrupts

ISR_ Port A _Character
Step f function (vi): Read Port A character.

Reset the status bit so that modem is ready
for next character input (generally resetting
of status bit is automatic without need of
specific instruction for it). Put it in memory
buffer. Memory buffer is a set of memory
addresses where the bytes (characters) are
queued for processing later.
Return from the interrupt service routine.

Out_B routine
• Step g: Call function (vii) to
decrypt the message characters at
the memory buffer and return for
next instruction step h.
• Step h: Call function (viii) to
encode the message character and
return for next instruction step k
• Step k: Call function (ix) to
transmit the encoded character to
Port B
• Return from the function.

INTERRUPT SERVICING MECHANISM
Interrupt vector:
 An interrupt vector is an important part of interrupt service mechanism, which
associates a processor.
 Processor first saves program counter and/or other registers of CPU on
interrupt and then loads a vector address into the program counter.
 Vector address provides either the ISR or ISR address to the processor for the
interrupt source or group of sources or given interrupt type.

Interrupt Vector
System software designer puts the bytes at a ISR_VECTADDR

address.
The bytes are for either the ISR short code or jump instruction to
ISR instruction or ISR short code with call to the full code of the
ISR at an ISR address or Bytes points to an ISR address
Interrupt
Vector
Interrupt Vector
• A memory address to which processor vectors (transfers into

program counter or IP and CS registers in case of 80x86) a new
address on an interrupt for servicing that interrupt.
• The memory addresses for vectoring by the processor are
processor or microcontroller specific.
• Vectoring is as per interrupt handling mechanism, which the
processor provides.
54
Chapter-4 L07: "Embedded Systems - " , Raj Kamal, Publs.: McGraw-Hill Education 2008
Processor Vectoring to an ISR_ VECTADDR
• On an interrupt, a processor vectors to a new address,
ISR_VECTADDR.
• Vector means the program counter (PC), which was going to have the
program or routine executing at instruction address of next instruction,
now saves that address on stack (or in some CPU register, called link
register) and processor loads the ISR_VECTADDR into the PC.
• When PC saves on the stack, the stack pointer register of CPU
provides the address of memory stack.
55
Link Register in certain Processors
A part of the CPU register set
The PC saves at link register (in place of stack) before the
processor vectors to an address by loading new value in PC
Return from ISR

Because the PC is saved at stack or link register before vectoring,
it enables return from the ISR later on an RETI (return from
interrupt) instruction
56
ISR_VECTADDR BASED ADDRESSING MECHANISM
• A system has the internal devices like the on-chip timer and on-chip
A/D converter.
• In a given microcontroller, each internal device interrupt source or
source group has separate ISR_VECTADDR address.
• Each external interrupt pins have separate ISR_VECTADDR,
example,8051.
57
Commonly used method
• The internal device (interrupt source or interrupt source group) in

microcontroller auto generates the corresponding interrupt- vector
address, ISR_VECTADDR.
• These vector addresses specific for a specific microcontroller or
processor with that internal device.
• An internal hardware signal from the device is sent for interrupt
58
source in device interrupts source group

Two types of handling mechanisms in processor hardware
1. There are some processors, which use ISR_VECTADDR directly

as ISR address and processor fetches from there the ISR
instruction, for example, ARM or 8051
2. There are some processors, which use ISR_VECTADDR

indirectly as ISR address and processor fetches the ISR address
from the bytes saved at the ISR_VECTADDR, for example,
59
80x86
ISR_VECTADDRs for hardware
interrupt sources or source-groups
ISR_VECTADDR1 From a vector
address either the 4
or 8-byte short ISR
ISR_VECTADDR2 executes or a Jump
Devices vector instruction executes
addresses of for the long
interrupts from ISR_VECTADDR3 program to ISR
the hardware codes starting
interrupt sources address
ISR_VECTADDR4
ISR_VECTADDR5 60
8051 Interrupt Vector
Addresses
INT0 0x0003 At vector
T0 address
0x000B
the 8-byte
INT1 0x0013 short ISR
executes
T1 0x001B and that
may call a
Serial 0x0023 long
routine
T2 0x002B
8051 vector addresses of interrupts from

2008 the hardwChaaprteer-i4nLt0e7:r"rEumpbetddseoduSyrscet emss .-" , 12
Raj Kamal,
Publs.: McGraw-Hill Education
80x86 Processor Mechanism
• A software interrupt instruction, for example, Int n explicitly also
defines type of interrupt and the type defines the
ISR_VECTADDR
• Type value multiplied by 0x00004 gives the vectoring address
from where the processor fetches the four bytes to compute the
ISR addresss for executing the ISR
62
80x86 Steps on INT n Innstruction or on
interrupt of
type n
Processor finds At ISR_VECTADDRn
the ISR vector two bytes are for IP and
INT n address from the two for CS
four bytes at
Interrupt ISR_VECTADD
Rn
Which computes Fetch IP and CS
from (n  of ISR after saving
0x00004) present IP and CS
on stack
Execute from
ISR address 63
ARM processor
Mechanism
1. In a certain processor architecture, for
example, ARM, the software instruction
SWI does not explicitly defines the type of
interrupt for generating different vector
address and instead there is a common
ISR_VECTADDR for each exception or
signal or trap generated using SWI
instruction.
64
ARM processor Mechanism
2. ISR that executes after vectoring has to
find out which exception caused the
processor to interrupt and program
diversion. Such a mechanism in processor
architecture results in provisioning for
the unlimited umber of exception
handling routines in the system with
common an interrupt vector address.
ARM processor provisions for such a
mechanism 65
ISR_VECTADDR with common vector addresses for
different exceptions, traps and signals using SWI
instruction in ARM
From the common
Common vector ISR (SWI handler)
vector address, from vector address, the
address for
call to required SWI
software here program flows
handler routine is
interrupts from using 4 byte jump
instruction to made as well as
SWI instruction
handler input
another common
parameter address is
vector address for
all SWI handlers computed
Maximum 224 ISR and

their parameter table 66
addresses
ARM SWI n instruction [n is 24
bits]
ARM ISR (SWI handler) From that common
Instruction vector address = vector address,
SWI 8-bit 0x00000008. using 24 bits, the
opcode and From call to required
24 bits for here program flows SWI handler
computation to another common routine is made as
of ISR and vector address for all well as handler
parameter the SWI handlers input parameter or
addresses parameter table
address is
Maximum 224 ISR and their computed
parameter tableChaadptder-r4eLs0s7:e"sEmbedded Systems - " Raj Kamal,
2008 18
Publs.: McGraw-Hill Education
,
Interrupt Vector
Table
• Facilitates the service of the multiple
interrupting sources for each
internal device.
• Each row of table has an ISR_VECTADDR
and the bytes to be saved at the
ISR_VECTADDR.
• Vector table location in memory depends on
the processor.
68
Interrupt Vector
Table
• System software designer must provide for putting
the bytes at each ISR_VECTADDR address.
The bytes are for either
• the ISR short code or jump instruction to ISR
instruction or
• ISR short code with call to the full code of the ISR
at an ISR address or
• Bytes points to an ISR address
69
n hardware and software
interrupt sources
and n entries in
vector table
ISR 1 address ISR_VECTADDR int 1 Table start
pointer address
ISR_VECTADDR int 2
ISR_VECTADDR int n  1
ISR n address ISR_VECTADDR int n
pointer
Lookup table for n addresses of handlers for exceptions,

traps, and device interrupts
70
Interrupt Vector
Table
• At higher memory addresses, 0xFFC0 to
0xFFFB in 68HC11
• At lowest memory addresses 0x0000 to
0x03FF in 80x86 processors.
• Starts from lowest memory addresses
0x00000000 in ARM7.
71
Device driver definition

A device driver has a set of routines (functions) used by a high-level language programmer,
which does the interaction with the device hardware, sends control commands to the device,
communicates data to the device and runs the codes for reading device data .

Each device in a system needs device driver routine with number of device functions.
• An ISR relates to a device driver command (device-function). The device driver uses SWI to call
the related ISR (device-function routine)
• The device driver also responds to device hardware interrupts.

Device driver generic commands

• A programmer uses generic commands for device driver for using a device. The operating system
provides these generic commands.
• Each command relates to an ISR. The device driver command uses an SWI to call the related ISR device-
function routine)
Generic functions
• Generic functions used for the commands to the device are device create ( ), open ( ), connect ( ), bind ( ),
read ( ), write ( ), ioctl ( ) [for IO control], delete ( ) and close ( ).

Device driver code

Different in different operating system.
Same device may have different code for the driver when system is using different operating system

Device driver
Does the interrupt service for any event related to the device and use the system and IO buses required
for the device service.
Device driver can be considered software layer between an application program and the device

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ADITYA ENGINEERING COLLEGE (A)

EMBEDDED FIRMWARE DESIGN

At the end of the Course, Student will be able to:

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

Embedded Firmware Design Approaches

At the end of this lecture, Student will be able to:

LO 1 :Understand the various approaches for design of Embedded Firmware

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

• The embedded firmware is responsible for controlling the various

• The embedded firmware is the master brain of the embedded system.

• The embedded firmware imparts intelligence to an Embedded system.

• It is a one time process and it can happen at any stage.

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

• In case of hardware breakdown , the damaged component may need to

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

• The embedded firmware is usually stored in a permanent memory

• Designing Embedded firmware requires understanding of the

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

Embedded Firmware design approaches

 The Super loop based approach(Conventional Procedural Based Firmware Design)

The decision on which approach needs to be adopted for firmware development is

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

The Super loop based approach

The Super loop based firmware development approach is Suitable for

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

A typical super loop implementation will look like:

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

 Simple and straight forward design.

 Reduced memory footprint.

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

Embedded OS based Approach

 A Real Time Operating System (RTOS)

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

Embedded Firmware development languages

At the end of this lecture, Student will be able to:

LO 1 :Learn Various development languages to design Embedded Firmware

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

Embedded firmware Development Languages

2. High Level Language

3. Mix of Assembly & High level Language

• ‘Machine language’ is a processor understandable language

• Machine language is a binary representation and it consists of 1s and 0s .

• Assembly language and machine languages are processor/controller dependent

• An Assembly language program written for one processor/controller family will

• Assembly language programming is the process of writing processor specific

•The general format of an assembly language instruction is an Opcode followed by

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

• Assembly language instructions are written one per line

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

Assembly Language – Source File to Hex File Translation

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

3.Low level Hardware Access:

4.Code Reverse Engineering:

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23

 More lines of assembly code is required for performing a simple action.

Embedded Systems K.Pavani,Sr.Assistant Professor,Department of ECE 4/25/23