TODAY’S LECTURE

 Unconditional branch instruction

 Call instructions and Stack
 Stack Pointer (SP)
 Pipelining
 Unconditional branch instruction
▪ Control is transferred unconditionally
to the target location (at ROM)
▪ Two unconditional branches
▪ GOTO
▪ BRA
▪ Decide which to use is depend on the
target address
 GOTO( LONG JUMP)
▪ It can go to any memory location in the 2M
address space of the PIC 18.
▪ Its 4-Byte (32 bit) instruction
▪ 12 bit → Op-code
▪ 20 bit → Address
▪ The 20-bit target address allow addressing
1M of memory location (00000-FFFFF),
instead of 2M !!!
▪ Some of the PIC 18 family members have
only 4k-32k of ROM. For this reason there
is another 2-byte instruction (BRA).
 BRA (branch)
▪ This is 2-byte (16 bit ) instruction
• First 5 bit → op-code
• Lower 11 bit → relative address of the target
000-FFFH is divided into forward and
backward jumps
▪ If the jump is forward, then target address
is positive.
▪ If the jump is backward then the target
address is negative.
▪ The 2-byte instruction is preferred
because it take less ROM space.
 Branching
▪ GOTO to itself using $ sign
▪ HERE GOTO HERE
▪ GOTO $
▪ BRA $
 Call Instructions and Stack
▪ CALL instruction is used to call a
subroutine.
▪ Subroutines are often used to perform
tasks required to performed frequently.
▪ In the PIC18 there are two instruction for
call
▪ CALL (long call)
▪ RCALL (relative call)
 CALL Instruction
▪ This is 4-Byte(32-bit) instruction
▪ 12 bit → Op-code
▪ 20 bit → target subroutines address.
▪ To make sure the PIC knows where to come back
after execution of the called subroutines, the
microcontroller automatically saves on the stack
the address of the instruction immediately
below the CALL.
▪ After finishing execution of the subroutine, the
instruction RETURN transfers control back to
caller.
Stack and stack pointer in the PIC18
▪ The Stack is read/write memory (RAM) used
by the CPU to store some very critical
information temporarily.
▪ The information can be address or data.
▪ The stack is 21-bit.
▪ The Stack Pointer (SP) is register used to
access the stack
▪ SP is 5-bit, this give use 32 location each 21bit
wide
▪ When the PIC18 is powered up , the SP
register contains value 0.
 Stack Pointer (SP)
▪ The stack location 1 is the first location
used to stack , because SP point to last-
used location.
▪ The location 0 of the stack is not
available and we have only 31 stack
location in the PIC18
Stack Pointer (SP)
 Stack Pointer (SP)
▪ The storing of CPU information such as
PC on the stack is called PUSH, and
loading back the contents into CPU
register is called POP.
▪ Push in the stack
▪ As data is pushed onto the stack, the
stack pointer is incremented.
▪ For every program counter saved on the
tack, SP is incremented only once.
 Stack Pointer (SP)
▪ Popping from the stack
▪ Popping the contents of the stack back
into a given register such as program
counter is the opposite of pushing.
▪ When the RETURN instruction at the end
of the subroutine is executed, the top
location of the stack is copied back to the
program counter.
▪ The stack pointer is decremented.
▪ The Stack is (LIFO) memory.
Calling many Subroutines form the Main
 RCALL (Relative Call)
▪ 2-Byte instruction
▪ The target address must be within 2K
▪ 11 bits of the 2 Byte is used
▪ Save a number of bytes
PIC18 Time Delay and Instruction Pipeline
Two factors can affect the accuracy of the delay
1. The duration of the clock period, which is
function of the Crystal frequency
▪ Connected to OSC1 and OSC2
2. The instruction cycle duration
▪ Most of the PIC18 instructions consumes 1
cycle
▪ Use Harvard Architecture
▪ Use RISC Architecture
▪ Use the pipeline concept between fetch and
execute.
 Pipelining
▪ The idea of pipelining in its simplest
from to allow the CPU to Fetch and
execute at the same time.
 PIC multistage execution pipeline
▪ Super-pipelining is used to speed up
execution of instruction.
▪ The Process of executing Instruction is
split into many small steps that are
executed in parallel. So the exe. Of
many instruction is overlapped.
▪ Limited to the slowest step
 PIC multistage execution pipeline
▪ In PIC18, the execution unit takes 4
clock periods of the oscillator.
PIC multistage execution pipeline
Instruction Cycle Execution
 Instruction Cycle time for the PIC
▪ Instruction cycles : is a certain amount of the
time for the CPU to execute an instruction.
▪ Because all instructions in the PIC are either
2-byte of 4-byte, most instruction take one or
two instruction cycles to execute.
▪ Instruction Cycle depends on the freq. of
oscillator
▪ Clock source: Crystal oscillator and on-chip
circuitry
▪ One instruction cycle consists of four
oscillator period.
 Example
▪ Find the period of the instruction cycle
you chose 4 MHz crystal? And what is
required time for fetching an
instruction?
▪ Solution
▪ 4 MHz/4 =1 MHz
▪ Instruction Cycle = 1/1MHz = 1 μsec
▪ Fetch cycle = 1 x 1 μsec = 1 μsec
 Branch Penalty
▪ For the concept of pipelining to work, we
need a buffer or queue in which an instruction
is perfected and ready to be executed.
▪ In some cases, the CPU must flush the queue
.. Why ???
▪ When the branch instruction is executed , the
CPU starts to fetch codes from the new
memory location.
▪ In this case, the execution unit must wait until
fetches the new instruction (Branch Penalty)
 Branch Penalty
▪ For this reason there are some
instruction take more than one
instruction cycle such as GOTO,
BRA,CALL and all conditional branch
such as BNZ, BC …
▪ The conditional branch can take one
instruction cycle if it does not jump.
 Delay Calculation of PIC18
▪ The delay of subroutines consist of two
parts:
▪ Setting counter.
▪ Loop
▪ Most of time delay is performed by
body of loop
 Quiz
▪ True of False
1. On power-up the PIC uses location 1 as the
first location of the stack.
2. The RCALL target address can be any ware
in the 2M address space.
3. In the PIC18, the instruction cycle lasts 4
clock periods of the crystal frequency.
4. BRA and CALL will always take 2 instruction
cycles.
5. The BNZ instruction will always take 2
instruction cycles.
ANY QUESTIONS?

Anyone willing to present?

▪Time allowed : 5 mins
▪Topic : Any
▪Bonus Points : +3
 References
▪ Chapter 3, ‘Brach Call and Time Delay Loops’
▪ PIC Microcontrollers and Embedded Systems by
Muhammad Ali Mazidi
▪ Wazen M. , Embedded System , Spring 2011.
▪ ‘Introduction to Real Time Embedded Systems’, v2-
IIT Kharagpur
▪ https://ti.tuwien.ac.at/ecs/teaching/courses/mclu/t
heory-material/Microcontroller.pdf