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Ad633 PDF
Ad633 PDF
Ad633 PDF
Analog Multiplier
Data Sheet AD633
FEATURES FUNCTIONAL BLOCK DIAGRAM
4-quadrant multiplication X1
1
Low cost, 8-lead SOIC and PDIP packages X2
00786-023
High impedance unity-gain summing input Y2
Laser-trimmed 10 V scaling reference
Figure 1.
APPLICATIONS
Multiplication, division, squaring
Modulation/demodulation, phase detection
Voltage-controlled amplifiers/attenuators/filters
GENERAL DESCRIPTION
The AD633 is a functionally complete, four-quadrant, analog The AD633 is available in 8-lead PDIP and SOIC packages. It is
multiplier. It includes high impedance, differential X and Y inputs, specified to operate over the 0°C to 70°C commercial temperature
and a high impedance summing input (Z). The low impedance range (J Grade) or the −40°C to +85°C industrial temperature
output voltage is a nominal 10 V full scale provided by a buried range (A Grade).
Zener. The AD633 is the first product to offer these features in
PRODUCT HIGHLIGHTS
modestly priced 8-lead PDIP and SOIC packages.
1. The AD633 is a complete four-quadrant multiplier offered
The AD633 is laser calibrated to a guaranteed total accuracy of in low cost 8-lead SOIC and PDIP packages. The result is a
2% of full scale. Nonlinearity for the Y input is typically less product that is cost effective and easy to apply.
than 0.1% and noise referred to the output is typically less than 2. No external components or expensive user calibration are
100 µV rms in a 10 Hz to 10 kHz bandwidth. A 1 MHz bandwidth, required to apply the AD633.
20 V/µs slew rate, and the ability to drive capacitive loads make 3. Monolithic construction and laser calibration make the
the AD633 useful in a wide variety of applications where device stable and reliable.
simplicity and cost are key concerns. 4. High (10 MΩ) input resistances make signal source
The versatility of the AD633 is not compromised by its simplicity. loading negligible.
The Z input provides access to the output buffer amplifier, enabling 5. Power supply voltages can range from ±8 V to ±18 V. The
the user to sum the outputs of two or more multipliers, increase internal scaling voltage is generated by a stable Zener diode;
the multiplier gain, convert the output voltage to a current, and multiplier accuracy is essentially supply insensitive.
configure a variety of applications. For further information, see
the Multiplier Application Guide.
TABLE OF CONTENTS
Features .............................................................................................. 1 Squaring and Frequency Doubling .............................................9
Applications ....................................................................................... 1 Generating Inverse Functions .....................................................9
Functional Block Diagram .............................................................. 1 Variable Scale Factor .................................................................. 10
General Description ......................................................................... 1 Current Output ........................................................................... 10
Product Highlights ........................................................................... 1 Linear Amplitude Modulator ................................................... 10
Revision History ............................................................................... 2 Voltage-Controlled, Low-Pass and High-Pass Filters............ 10
Specifications..................................................................................... 3 Voltage-Controlled Quadrature Oscillator................................... 11
Absolute Maximum Ratings ............................................................ 4 Automatic Gain Control (AGC) Amplifiers ........................... 11
Thermal Resistance ...................................................................... 4 Model Results .................................................................................. 13
ESD Caution .................................................................................. 4 Examples of DC, Sin, and Pulse Solutions Using Multisim.. 13
Pin Configurations and Function Descriptions ........................... 5 Examples of DC, Sin, and Pulse Solutions Using PSPICE .... 14
Typical Performance Characteristics ............................................. 6 Examples of DC, Sin, and Pulse Solutions Using SIMetrix .. 14
Functional Description .................................................................... 8 Evaluation Board ............................................................................ 16
Error Sources................................................................................. 8 Outline Dimensions ....................................................................... 19
Applications Information ................................................................ 9 Ordering Guide .......................................................................... 20
Multiplier Connections ............................................................... 9
REVISION HISTORY
3/15—Rev. J to Rev. K Renumbered Sequentially ............................................................. 12
Changes to General Description Section ...................................... 1 Changes to Ordering Guide .......................................................... 15
Changes to Figure 12 Caption and Figure 14 Caption ................ 9
Added Model Results Section, Examples of DC, Sin, and 4/11—Rev. G to Rev. H
Pulse Solutions Using Multisim Section, and Figure 24 Changes to Figure 1, Deleted Figure 2 ............................................1
Through Figure 29, Renumbered Sequentially........................... 13 Added Figure 2, Figure 3, Table 4, Table 5 .....................................5
Added Examples of DC, Sin, and Pulse Solutions Using Deleted Figure 9, Renumbered Subsequent Figures .....................6
PSPICE Section, Examples of DC, Sin, and Pulse Solutions Changes to Figure 15.........................................................................9
Using SIMetrix Section, and Figure 30 Through Figure 37 ...... 14 4/10—Rev. F to Rev. G
Added Figure 38 Through Figure 41 ........................................... 15 Changes to Equation 1 ......................................................................6
Changes to Equation 5 and Figure 14 .............................................7
9/13—Rev. I to Rev. J Changes to Figure 21.........................................................................9
Reorganized Layout ............................................................ Universal
Change to Table 1 ............................................................................. 3 10/09—Rev. E to Rev. F
Changes to Figure 4 .......................................................................... 6 Changes to Format ............................................................. Universal
Added Figure 10, Renumbered Sequentially ................................ 7 Changes to Figure 21.........................................................................9
Changes to Figure 15 ........................................................................ 9 Updated Outline Dimensions ....................................................... 11
Changes to Figure 20 ...................................................................... 10 Changes to Ordering Guide .......................................................... 12
Changes to Figure 31 ...................................................................... 14
Added Figure 32.............................................................................. 15 10/02—Rev. D to Rev. E
Edits to Title of 8-Lead Plastic SOIC Package (RN-8) .................1
2/12—Rev. H to Rev. I Edits to Ordering Guide ...................................................................2
Changes to Figure 1 .......................................................................... 1 Change to Figure 13 ..........................................................................7
Changes to Figure 2 .......................................................................... 5 Updated Outline Dimensions ..........................................................8
Changes to Generating Inverse Functions Section ...................... 8
Changes to Figure 15 ........................................................................ 9
Added Evaluation Board Section and Figure 23 to Figure 29,
Rev. K | Page 2 of 20
Data Sheet AD633
SPECIFICATIONS
TA = 25°C, VS = ±15 V, RL ≥ 2 kΩ.
Table 1.
AD633J, AD633A
Parameter Conditions Min Typ Max Unit
TRANSFER FUNCTION
W=
(X1 − X2 )(Y1 − Y2 ) + Z
10 V
MULTIPLIER PERFORMANCE
Total Error −10 V ≤ X, Y ≤ +10 V ±1 ±21 % full scale
TMIN to TMAX ±3 % full scale
Scale Voltage Error SF = 10.00 V nominal ±0.25% % full scale
Supply Rejection VS = ±14 V to ±16 V ±0.01 % full scale
Nonlinearity, X X = ±10 V, Y = +10 V ±0.4 ±11 % full scale
Nonlinearity, Y Y = ±10 V, X = +10 V ±0.1 ±0.41 % full scale
X Feedthrough Y nulled, X = ±10 V ±0.3 ±11 % full scale
Y Feedthrough X nulled, Y = ±10 V ±0.1 ±0.41 % full scale
Output Offset Voltage2 ±5 ±501 mV
DYNAMICS
Small Signal Bandwidth VO = 0.1 V rms 1 MHz
Slew Rate VO = 20 V p-p 20 V/µs
Settling Time to 1% ΔVO = 20 V 2 µs
OUTPUT NOISE
Spectral Density 0.8 µV/√Hz
Wideband Noise f = 10 Hz to 5 MHz 1 mV rms
f = 10 Hz to 10 kHz 90 µV rms
OUTPUT
Output Voltage Swing ±111 V
Short Circuit Current RL = 0 Ω 30 401 mA
INPUT AMPLIFIERS
Signal Voltage Range Differential ±101 V
Common mode ±101 V
Offset Voltage (X, Y) ±5 ±301 mV
CMRR (X, Y) VCM = ±10 V, f = 50 Hz 60 1
80 dB
Bias Current (X, Y, Z) 0.8 2.01 µA
Differential Resistance 10 MΩ
POWER SUPPLY
Supply Voltage
Rated Performance ±15 V
Operating Range ±81 ±181 V
Supply Current Quiescent 4 61 mA
1
This specification was tested on all production units at electrical test. Results from those tests are used to calculate outgoing quality levels. All minimum and maximum
specifications are guaranteed; however, only this specification was tested on all production units.
2
Allow approximately 0.5 ms for settling following power on.
Rev. K | Page 3 of 20
AD633 Data Sheet
ESD CAUTION
Rev. K | Page 4 of 20
Data Sheet AD633
X2 2 A 7 W Y2 2 1 7 X1
10V
1
Y1 3 10V 6 Z –VS 3 6 +VS
A
1
Y2 4 5 –VS Z 4 5 W
AD633JN/AD633AN AD633JR/AD633AR
00786-002
00786-001
(X1 – X2)(Y1 – Y2) (X1 – X2)(Y1 – Y2)
W= +Z W= +Z
10V 10V
Table 4. 8-Lead PDIP Pin Function Descriptions Table 5. 8-Lead SOIC Pin Function Descriptions
Pin No. Mnemonic Description Pin No. Mnemonic Description
1 X1 X Multiplicand Noninverting Input 1 Y1 Y Multiplicand Noninverting Input
2 X2 X Multiplicand Inverting Input 2 Y2 Y Multiplicand Inverting Input
3 Y1 Y Multiplicand Noninverting Input 3 −VS Negative Supply Rail
4 Y2 Y Multiplicand Inverting Input 4 Z Summing Input
5 −VS Negative Supply Rail 5 W Product Output
6 Z Summing Input 6 +VS Positive Supply Rail
7 W Product Output 7 X1 X Multiplicand Noninverting Input
8 +VS Positive Supply Rail 8 X2 X Multiplicand Inverting Input
Rev. K | Page 5 of 20
AD633 Data Sheet
0 90
CL = 1000pF
OUTPUT RESPONSE (dB)
80
CL = 0.01µF 70
CMRR (dB)
–10 TYPICAL
FOR X, Y
60 INPUTS
50
–20
NORMAL 40
CONNECTION
00786-003
30
00786-006
–30 20
10k 100k 1M 10M 100 1k 10k 100k 1M
FREQUENCY (Hz) FREQUENCY (Hz)
700 1.5
1.0
500
400
0.5
300
00786-007
00786-004
200 0
–60 –40 –20 0 20 40 60 80 100 120 140 10 100 1k 10k 100k
TEMPERATURE (°C) FREQUENCY (Hz)
Figure 5. Input Bias Current vs. Temperature (X, Y, or Z Inputs) Figure 8. Noise Spectral Density vs. Frequency
14 1k
PEAK POSITIVE OR NEGATIVE SIGNAL (V)
12 Y-FEEDTHROUGH
100
OUTPUT, RL ≥ 2kΩ
10 X-FEEDTHROUGH
10
ALL INPUTS
8
1
6
00786-005
00786-008
4 0.1
8 10 12 14 16 18 20 10 100 1k 10k 100k 1M 10M
PEAK POSITIVE OR NEGATIVE SUPPLY (V) FREQUENCY (Hz)
Figure 6. Input and Output Signal Ranges vs. Supply Voltages Figure 9. AC Feedthrough vs. Frequency
Rev. K | Page 6 of 20
Data Sheet AD633
3
1
OUTPUT (±mV)
−1
−2
−3
00786-009
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
TIME (Minutes)
Figure 10. Typical VOS vs. Time, For Five Minutes Following Power Up
Rev. K | Page 7 of 20
AD633 Data Sheet
FUNCTIONAL DESCRIPTION
The AD633 is a low cost multiplier comprising a translinear ERROR SOURCES
core, a buried Zener reference, and a unity-gain connected Multiplier errors consist primarily of input and output offsets,
output amplifier with an accessible summing node. Figure 1 scale factor error, and nonlinearity in the multiplying core. The
shows the functional block diagram. The differential X and Y input and output offsets can be eliminated by using the optional
inputs are converted to differential currents by voltage-to-current trim of Figure 11. This scheme reduces the net error to scale
converters. The product of these currents is generated by the factor errors (gain error) and an irreducible nonlinearity
multiplying core. A buried Zener reference provides an overall component in the multiplying core. The X and Y nonlinearities
scale factor of 10 V. The sum of (X × Y)/10 + Z is then applied are typically 0.4% and 0.1% of full scale, respectively. Scale
to the output amplifier. The amplifier summing Node Z allows factor error is typically 0.25% of full scale. The high impedance
the user to add two or more multiplier outputs, convert the Z input should always reference the ground point of the driven
output voltage to a current, and configure various analog system, particularly if it is remote. Likewise, the differential X
computational functions. and Y inputs should reference their respective grounds to
Inspection of the block diagram shows the overall transfer realize the full accuracy of the AD633.
function is +VS
W=
(X1 − X2 )(Y1 − Y2 ) + Z (1) ±50mV
300kΩ
10 V 50kΩ TO APPROPRIATE
INPUT TERMINAL
1kΩ (FOR EXAMPLE, X2, Y2, Z)
00786-010
–VS
Rev. K | Page 8 of 20
Data Sheet AD633
APPLICATIONS INFORMATION
The AD633 is well suited for such applications as modulation +15V
R E2
applications show the pin connections for the AD633JN (8-lead 2 X2 W 7
R1
W=
10V
AD633JN 1kΩ
PDIP), which differs from the AD633JR (8-lead SOIC). 3 Y1 Z 6
C
R2
MULTIPLIER CONNECTIONS 4 Y2 –VS 5 3kΩ
00786-013
0.1µF
and Y inputs normally have their negative nodes grounded, but –15V
they are fully differential, and in many applications, the grounded Figure 14. Bounceless Frequency Doubler (See the Model Results Section)
inputs may be reversed (to facilitate interfacing with signals of a
particular polarity while achieving some desired output polarity), At ωo = 1/CR, the X input leads the input signal by 45° (and is
or both may be driven. attenuated by √2), and the Y input lags the X input by 45° (and
+15V
is also attenuated by √2). Because the X and Y inputs are 90° out of
phase, the response of the circuit is (satisfying Equation 3)
0.1µF
1 E
( )E( )
+ 1 X1 +VS 8
W=
(10 V ) 2 sin ω0t + 45° 2 sin ω0t + 45°
X
INPUT (X1 – X2)(Y1 – Y2)
– 2 X2 W 7 W= +Z
10V
AD633JN 2
E
( )
+ 3 Y1 Z 6 OPTIONAL SUMMING
=
(40 V ) sin 2 ω t (4)
Y INPUT, Z
INPUT 0
– 4 Y2 –VS 5
0.1µF
00786-011
+15V +15V
–15V 0.01µF 0.1µF
1 X1 +VS 8
Figure 13. Connections for Squaring 0.1µF
10kΩ 7 2 X2 W 7
When the input is a sine wave E sin ωt, this squarer behaves as a E < 0V 2
AD633JN
AD711 Y1 Z 6
frequency doubler, because
6 3
1N4148 –15V
3
(E sin ωt )
4 4 Y2 –VS 5
2 2
=
E
(1 − cos 2 ωt ) (2) 0.1µF
0.1µF
10 V 20 V
000786-014
–15V W = √ –(10V)E
Equation 2 shows a dc term at the output that varies strongly
Figure 15. Connections for Square Rooting
with the amplitude of the input, E. This can be avoided using
the connections shown in Figure 14, where an RC network is
used to generate two signals whose product has no dc term. It
uses the identity
cos θ sin θ =
1
(sin 2 θ ) (3)
2
Rev. K | Page 9 of 20
AD633 Data Sheet
Likewise, Figure 16 shows how to implement a divider using a This arrangement forms the basis of voltage-controlled integrators
multiplier in a feedback loop. The transfer function for the and oscillators as is shown later in this section. The transfer
divider is function of this circuit has the form
1 X1 X2Y1 Y2
W 10 V
E
(6) IO (7)
EX R 10 V
R
10kΩ LINEAR AMPLITUDE MODULATOR
+15V +15V The AD633 can be used as a linear amplitude modulator with no
0.1µF 0.1µF external components. Figure 19 shows the circuit. The carrier
EX 1 X1 +VS 8
R and modulation inputs to the AD633 are multiplied to produce
10kΩ X2 W 7
E 2
7 2 a double sideband signal. The carrier signal is fed forward to the
AD633JN
AD711 6 3 Y1 Z 6 Z input of the AD633 where it is summed with the double
0.1µF
3
4 4 Y2 –VS 5
sideband signal to produce a double sideband with the carrier
0.1µF
output.
+15V
–15V
–15V 00786-015
E 0.1µF
W' = –10V MODULATION +
EX 1 X1 +VS 8
INPUT
Figure 16. Connections for Division ±EM – EM
2 X2 W 7 W = 1+ EC sin ωt
10V
AD633JN
VARIABLE SCALE FACTOR CARRIER 3 Y1 Z 6
INPUT
EC sin ωt –VS 5
In some instances, it may be desirable to use a scaling voltage 4 Y2
0.1µF
other than 10 V. The connections shown in Figure 17 increase
00786-018
the gain of the system by the ratio (R1 + R2)/R1. This ratio is –15V
limited to 100 in practical applications. The summing input, S, Figure 19. Linear Amplitude Modulator
can be used to add an additional signal to the output, or it can
VOLTAGE-CONTROLLED, LOW-PASS AND HIGH-
be grounded.
PASS FILTERS
+15V
Figure 20 shows a single multiplier used to build a voltage-
0.1µF
+ 1 X1 +VS 8 controlled, low-pass filter. The voltage at Output A is a result of
X
INPUT
– (X1 – X2)(Y1 – Y2) R1 + R2 filtering ES. The break frequency is modulated by EC, the control
2 X2 W 7 W= +S
AD633JN R1 10V R1 input. The break frequency, f2, equals
+ 3 Y1 Z 6 1kΩ ≤ R1, R2 ≤ 100kΩ
Y
INPUT EC (8)
– 4 Y2 –VS 5 R2 f2
0.1µF 10 ( 2 RC )
S
00786-016
R 10V 1 10RC
AD633JN –15V T2 = =
+ 3 Y1 Z 6 1kΩ ≤ R ≤ 100kΩ ω2 EC
Y
INPUT Figure 20. Voltage-Controlled, Low-Pass Filter
– 4 Y2 –VS 5
0.1µF
The voltage at Output B, the direct output of the AD633, has the
00786-017
D1 D3
1N914 1N914
(10V) cos ωt
D2 D4
1N914 1N914 +15V
0.1µF +15V C2 R4
1 X1 +VS 8 0.01µF 16kΩ
R1
1kΩ 0.1µF
2 X2 W 7 1 X1 +VS 8 R3
R2 330kΩ
AD633JN 16kΩ
EC 3 Y1 Z 6 2 X2 W 7 (10V) sin ωt
C1 AD633JN R5
4 Y2 –VS 5 0.01µF 3 Y1 Z 6 16kΩ
0.1µF 0.1µF C3
4 Y2 –VS 5 0.01µF
–15V
00786-021
EC
–15V f= = kHz
10V
Rev. K | Page 11 of 20
AD633 Data Sheet
R2 R3 R4
1kΩ 10kΩ 10kΩ
0.1µF 8 C1
2 1µF
1 X1 +VS 8 1/2 1 EOUT
AD712 R5
2 X2 W 7 3 10kΩ
AD633JN
Y1 Z 6 A1 R6
E 3
1kΩ
4 Y2 –VS 5
+15V
1 CC COMMON 8
0.1µF
0.1µF
2 VIN +VS 7
–15V
AD736
C2 3 CF OUTPUT 6
0.02µF 0.1µF
4 –VS CAV 5
C3 R10
0.2µF 10kΩ
–15V
C4
A2 33µF
R9 1N4148 6
10kΩ 1/2 +15V
7
AD712 OUTPUT
5 R8
4 50kΩ LEVEL
0.1µF ADJUST
00786-022
–15V
Rev. K | Page 12 of 20
Data Sheet AD633
MODEL RESULTS
Circuit simulation using SPICE models embedded in various
application formats such as PSPICE, Multisim, and SIMetrix is a
popular and efficient method of assessing the integrity of a
circuit before creating the printed circuit board in which the
circuits are ultimately used. Although impossible to
demonstrate all of the multiplier functions in every available
program, Figure 24 through Figure 41 demonstrate how the
00786-126
schematic and graph for simple dc, sin(x), and pulse
applications appear in three popular SPICE programs. If a
Figure 26. Frequency Doubler Circuit Schematic Created in Multisim
simulator is not shown here, a good way to progress is to start
with a basic dc circuit to verify that the circuit converges and
then continue with waveforms that are more complex. When
analyzing nonlinear devices such as multipliers, the most
common simulation issue is convergence, the iterative process
by which SPICE seeks the initial dc bias condition before
completely solving the circuit and displaying a graph.
00786-127
EXAMPLES OF DC, SIN, AND PULSE SOLUTIONS
USING MULTISIM Figure 27. Frequency Doubler Response Graph Displayed in Multisim
00786-124
00786-128
Figure 24. Circuit to Multiply Two Integers Schematic Created in Multisim
Figure 28. Pulse Circuit Schematic Created in Multisim
00786-125
00786-129
Figure 25. Circuit to Multiply Two Integers Response Graph Displayed in Multisim
(2 V × 4 V)/10 V = 0.8 V
Figure 29. Pulse Circuit Response Graph Displayed in Multisim
Rev. K | Page 13 of 20
AD633 Data Sheet
EXAMPLES OF DC, SIN, AND PULSE SOLUTIONS
USING PSPICE
00786-134
00786-130
Figure 34. Pulse Circuit Schematic Created in PSPICE
Figure 30. Simple Circuit Schematic Created in PSPICE
00786-135
00786-131
00786-136
Figure 32. Frequency Doubler Circuit Schematic Created in PSPICE
Figure 36. Simple Circuit Schematic Created in SIMetrix
00786-133
00786-137
Rev. K | Page 14 of 20
Data Sheet AD633
00786-138
00786-140
Figure 38. Frequency Doubler Circuit Schematic Created in SIMetrix
00786-139
00786-141
Figure 41. Pulse Circuit Response Displayed in SIMetrix
Rev. K | Page 15 of 20
AD633 Data Sheet
EVALUATION BOARD
The evaluation board of the AD633 enables simple bench-top
experimenting to be performed with easy control of the AD633.
Built-in flexibility allows convenient configuration to
accommodate most operating configurations. Figure 42 is a
photograph of the AD633 evaluation board.
00786-026
00786-024 Figure 43. Component Side Copper
00786-027
an active signal source, to ground, or to a test loop connected
directly to the device pin for direct measurements, such as bias
Figure 44. Circuit Side Copper
current. Inputs may be connected single ended or differentially,
but must have a dc path to ground for bias current. If the
impedance of an input source is non-zero, an equal value
impedance must be connected to the opposite polarity input to
avoid introducing additional offset voltage.
The AD633-EVALZ can be configured for multiplier or divider
operation by switch S1. Refer to Figure 16 for divider circuit
connections.
Figure 43 through Figure 46 are the signal, power, and ground-
plane artworks, and Figure 47 shows the component and circuit
side silkscreen. Figure 48 shows the assembly.
00786-028
Rev. K | Page 16 of 20
Data Sheet AD633
00786-029
00786-031
Figure 46. Inner Layer Power Plane Figure 48. AD633-EVALZ Assembly
00786-030
GND G1 G2 G3 G4 G5 G6
+V −V
C5 + C6
10µF 10µF
25V + 25V
+V −V
Y1_IN
D X2_TP X2_IN
IN FUNCT(1) IN
GND SEL_Y1 SEL_X2 GND
M
TEST Y1_TP TEST
Y2_IN
Y2_TP X1_TP X1_IN
IN AD633ARZ IN (DENOM)
1 8 R1
GND SEL_Y2 Y1 DUT1 X2 SELX1 GND 100Ω
2 7
Y2 X1
TEST TEST
3 6 +V
–VS +VS X2_IN
+V
–VS 4 5
C1 Z W C2 C3
0.1µF 0.1µF 7 0.1µF
3
+
Z_IN R2 Z2 6
Y2_TP
IN D 10kΩ 2 AD711 FUNCTION SWITCH – S1
SEL_Y2 –
GND MULTIPLY:
FUNCT(2) M 4 [(X1-X2)(Y1-Y2)/10V] + Z
TEST R3 C4
NOM_TP 10kΩ 0.1µF DIVIDE:
−V −10V (NUM/DENOM)
NUMERATOR
D
S1
OUT
00786-032
M
OUT_TP
Rev. K | Page 17 of 20
AD633 Data Sheet
POWER SUPPLY
X INPUT DC
VOLTAGE
Y INPUT DC
VOLTAGE OUT – DMM
00786-033
Figure 50. AD633-EVALZ Configured for Bench Experiments
Rev. K | Page 18 of 20
Data Sheet AD633
OUTLINE DIMENSIONS
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
8 5 0.280 (7.11)
0.250 (6.35)
1 0.240 (6.10)
4
0.325 (8.26)
0.310 (7.87)
0.100 (2.54) 0.300 (7.62)
BSC 0.060 (1.52) 0.195 (4.95)
0.210 (5.33) MAX 0.130 (3.30)
MAX 0.115 (2.92)
0.015
0.150 (3.81) (0.38) 0.015 (0.38)
0.130 (3.30) MIN GAUGE
0.115 (2.92) PLANE 0.014 (0.36)
SEATING
PLANE 0.010 (0.25)
0.022 (0.56) 0.008 (0.20)
0.005 (0.13) 0.430 (10.92)
0.018 (0.46) MIN MAX
0.014 (0.36)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
070606-A
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
8 5
4.00 (0.1574) 6.20 (0.2441)
3.80 (0.1497) 1 5.80 (0.2284)
4
Rev. K | Page 19 of 20
AD633 Data Sheet
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD633ANZ −40°C to +85°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8
AD633ARZ −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD633ARZ-R7 −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8
AD633ARZ-RL −40°C to +85°C 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel R-8
AD633JN 0°C to 70°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8
AD633JNZ 0°C to 70°C 8-Lead Plastic Dual-in-Line Package [PDIP] N-8
AD633JR 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD633JR-REEL 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel R-8
AD633JR-REEL7 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8
AD633JRZ 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N] R-8
AD633JRZ-R7 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N], 7" Tape and Reel R-8
AD633JRZ-RL 0°C to 70°C 8-Lead Standard Small Outline Package [SOIC_N], 13" Tape and Reel R-8
AD633-EVALZ Evaluation Board
1
Z = RoHS Compliant Part.
Rev. K | Page 20 of 20