dvdr3570h Service Manual PDF

HDD & DVD Recorder DVDR3570H/75/97
DVDR3590H//75/97
CLASS 1
LASER PRODUCT
Contents Page Contents Page

1 Technical Specifications and Connection 7 Circuit Diagrams and PWB Layout 103
Facilities 2 Analog Circuit Diagrams 103
2 Safety Information, General Notes & Lead Analog Layout Diagrams 106
Free Requirements 5 Front Circuit Diagrams 108
3 Directions for Use 7 Front Display/Connector Layout Diagrams 110
4 Mechanical Instructions 10 Front Standby Circuit & Layout Diagrams 111
5 Firmware Upgrading, Diagnostic Software, LecoPlus INIT Circuit & Layout Diagrams 112
Alignment and Test Procedures 14 Digital Circuit Diagrams 113
6 Block Diagrams,Waveforms, Wiring Diagram 95 Digital Layout Diagrams 121
Overall block diagram 95 HDMI Circuit Diagrams 123
Wiring diagram 96 HDMI Layout Diagrams 127
Waveforms of Analog Board 97 8 IC Internal Block Diagrams 129
Waveforms of Digital Board 98 Analog Board 129
Waveforms of HDMI Board 99 Digital Board 131
Test Points Overview for HDMI Board 100 HDMI Board 140
Test Points Overview for Analog Board 101 9 Exploded view & Service parts list 158
Test Points Overview for Digital Board 102 Exploded View of the set 158
Service parts list 159
Revision list 160
©Copyright 2007 Philips Consumer Electronics B.V. Eindhoven, The Netherlands.

All rights reserved. No part of this publication may be reproduced, stored in a
retrieval system or transmitted, in any form or by any means, electronic,
mechanical, photocopying, or otherwise without the prior permission of Philips.
Published by KC-TE 0718 V&MA Printed in the Netherlands Subject to modification EN 3139 785 32803
Version 1.3
EN 2 1. 3139 785 32801 Technical Specifications and Connection Facilities
1. Technical Specifications and Connection Facilities
1.1 PCB Locations
HDMI
Analog Board
PSU Board
Board
Basic Engine Digital Board

HDD
Standby Board (Behind

the Front Cabinet) Front Board (Behind the
Front Cabinet)
1.2 General: Audio Performance:
Audio analogue Mono :

Power supply : 220-240V, ~50 Hz
Frequency Response relative to
1 kHz : 0 ± 3dB
Power consumption
(100 Hz to 12 kHz)
DVDR3570H : 28 W
S/N unweighted : ≥ 40dB (Quasi peak,
DVDR3590H : 32 W
22 Hz – 22 kHz)
Standby power consumption : < 3.7 W
S/N weighted : ≥ 45dB (Quasi peak,
CCIR 468)
1.3 RF Tuner (Analogue) Harmonic distortion at 1 kHz : ≤ 1.5% (FM: ± 25 kHz)
Harmonic distortion at 1 kHz : ≤2%
Test equipment: Fluke 54200 TV Signal generator (AM: m = 54% L/L’)
Test streams: Philips Standard test pattern
Audio NICAM Stereo/Dual :
1.3.1 System Frequency Response relative to
1 kHz : 0 ± 3dB
B/G, I, L/L’, D/K (40 Hz to 15 kHz)
S/N unweighted : ≥ 65dB (Quasi peak,
1.3.2 RF - Loop Through: 22 Hz – 22 kHz)
S/N weighted : ≥ 70dB (Quasi peak,
Frequency range : 43 MHz – 860 MHz CCIR 468)
Gain (ANT IN – ANT OUT) Harmonic distortion at 1 kHz : ≤ 0.5% (Headroom:
without amplifier : -4dB ± 2dB System I – 21.1dB,
Gain (ANT IN – ANT OUT) all others – 16.5dB)
with amplifier : From 2dB + 3dB until Channel Separation : ≥ 45dB
2dB – 2dB
1.3.4 Tuning
1.3.3 Receiver:
Tuning Frequency Range : 45.25 MHz – 857 MHz
Output of Cinch connector to be used for measurements Antenna Level for 40dB luminance
(direct output from front end) S/N (video unweighted) at 75Ω : ≤ 40dBμV (High End)
≤ 60dBμV (Low End)
Video Performance:
Automatic Search Tuning:
Frequency Response : 0 ± 4dB (0 to 4.4 MHz) Scanning time auto search without
RF Signal : < 2.5 min.
Group Delay : 0 ± 150 n sec (Typical 3 minutes)
(0 to 4.4 MHz) Stop level (vision carrier) : ≥ 40dBμV
Maximum tuning error during
operation (drift) : ± 100 kHz
Maximum tuning error of a recalled
program : ± 62.5 kHz
Technical Specifications and Connection Facilities 3139 785 32801 1. EN 3
Tuning Principles: 1.5 Digital Inputs / Outputs

Automatic system recognition
Manual Selection in “Store” mode 1.5.1 CAM 2 DV IN (IEEE 1394 Digital Video Input)
Storage of frequencies at each random
position number Implementation Standard according:
IEEE Std 1394-1995
1.4 Analog Inputs / Outputs IEC61883 - Part1
IEC61883 - Part 2 SD-DVCR (02-01-1997)
1.4.1 Audio/Video Front Input Connectors
Specification of consumer use digital VCR’s using 6.3mm
(CAM 1) AUDIO – Cinch (L/R): magnetic tape – dec.1994
Input voltage : 2.2Vrms max Mechanical connection according to Annex of IEC 61883-1
Input impedance : > 10kΩ
1.5.2 (AUDIO OUT) COAXIAL DIGITAL OUT – Cinch
(CAM1) VIDEO – Cinch:
Input voltage : 1Vpp ± 3dB LPCM : according IEC 60958
Input impedance : 75Ω MPEG 1, MPEG 2, AC3 : according IEC 61937
DTS : according IEC 61937 +
1.4.2 Audio/Video Rear Input Connectors addendum
AUDIO IN (AUDIO 1/2) – Cinch (L/R): 1.5.3 USB
Input voltage : 2.2Vrms max
Input impedance : > 10kΩ Compatibility : USB 2.0
Type of connector : Series A Connector
CVBS IN (VIDEO IN) – Cinch:
Input voltage : 1Vpp ± 3dB 1.5.4 HDMI Output
Input impedance : 75Ω
Compatibility : HDMI version 1.1
S-VIDEO IN (VIDEO IN) – Hosiden: Type of connector : Type A connector
According to IEC 933-5 (19 pins)
Superimposed DC-level on pin 4 (load > 100kΩ)
< 2.4V is detected as 4:3 aspect ratio
> 3.5V is detected as 16:9 aspect ratio 1.6 Video Performance
Input voltage Y : 1Vpp ± 3dB 1.6.1 SNR

Input impedance Y : 75Ω
Input voltage C : 300mVpp ± 3dB PAL
Input impedance C : 75Ω RGB CVBS Y/C
COMPONENT VIDEO IN – Cinch (Y/Pb/Pr): ≥ 55 dB Lumincance: ≥ 55 dB Y: ≥ 57 dB
According to EIO-770-I-A, EIA-770-2 Chroma: ≥ 55 dB (AM) C: ≥ 57 dB (AM)
≥ 52 dB (PM) ≥ 54 dB (PM)
1.4.3 Audio/Video Output Connectors
NTSC
(AUDIO OUT) AUDIO – Cinch (L/R):
Y Pb Pr CVBS Y/C
Output voltage : 2Vrms max
Output impedance : > 10kΩ ≥ 55 dB Lumincance: ≥ 55 dB Y: ≥ 55 dB
Chroma: ≥ 54 dB (AM) C: ≥ 54 dB (AM)
(VIDEO OUT) CVBS OUT– Cinch: ≥ 54 dB (PM) ≥ 54 dB (PM)
Output voltage : 1Vpp ± 3dB
Output impedance : 75Ω
1.6.2 Bandwidth
(VIDEO OUT) S-VIDEO OUT - Hosiden:
According to IEC 933-5 PAL
Superimposed DC-level on pin 4 (load > 100kΩ)
RGB CVBS Y/C
< 2.4V is detected as 4:3 aspect ratio
> 3.5V is detected as 16:9 aspect ratio 0.5 to 4 MHz:+1dB/ 0.5 to 4 MHz:+1dB/ Y:4.8MHz-3dB
-2dB -2dB
Output voltage Y : 1Vpp ± 3dB
4.8 MHz:-3dB 4.8 MHz:-3dB C:700 kHz
Output impedance Y : 75Ω
Output voltage C : 300mVpp ± 3dB 5.8 MHz:-6dB 5.8 MHz:-6dB
Output impedance C : 75Ω
NTSC
COMPONENT VIDEO OUT – Cinch (Y/Pb/Pr):
YPbPr CVBS Y/C
According to EIA-770-1-A, EIA-770-2-A
4.2 MHz:-3dB 4.2 MHz:-3dB Y:4.2MHz-3dB
5.8 MHz:-6dB 5.8 MHz:-6dB C:≥ 700 kHz
With Pscan: 8.4MHz
-3dB
EN 4 1. 3139 785 32801 Technical Specifications and Connection Facilities
1.7 Audio Performance CDDA (PCM) 1.11 Supported Disc Types and Media Speed for
Recording
1.7.1 Cinch Output Rear
Output voltage : 1.8Vrms ± 2dB Disc Media Speeds

Channel unbalance : < 0.22dB DVD+R 1x - 16x
Crosstalk 1kHz : > 110 dB
Crosstalk 16Hz – 20kHz : > 110 dB DVD+RW 2.4x - 8x
Signal to noise ratio (unweighted) DVD-R 1x - 16x
20Hz – 20kHz bandwidth limited : > 95dB (mute)
DVD-RW 2.4x - 4x
Signal to noise ratio (A-weighted)
RMS 20Hz – 20kHz DVD+R DL 2.4x
bandwidth limited : > 112dBA (mute)
Dynamic range 1kHz : > 90dB
Distortion and noise 1kHz : > 85dB 1.12 Diversity Matrix
Distortion and noise 16Hz – 20kHz : > 78dB
Mute (spin-up, pause, access) : > 78dB
DVDR3570H DVDR3590H
1.8 Dimension and Weight Hard Disk capacity 160 GB 250 GB
Set Dimension W x H x D : 435 x 43 x 324 mm

Net Weight : 3.8 kg
1.9 Laser Output Power & Wavelength

1.9.1 DVD
Output power during reading : 1.0mW

Output power during writing : 69mW
Wavelength : 658nm (at 25 °C)
1.9.2 CD
Output power : 1.2mW

Wavelength : 783nm (at 25 °C)
1.10 Playability
Video Playback
1. Playback Media: x
CD-R/CD-RW, DVD+R/+RW,
DVD-R/-RW, DVD-Video, Video
CD/SVCD, DVD+R DL, DVD-R
DL, USB flash drive
2. Compression Formats: x
MPEG2, MPEG1, DivX 3.11, DivX
4.x, DivX 5.x, DivX 6.0, MPEG4
Audio Playback
1. Playback Media: x
Audio CD, CD-R/RW, DVD+R DL,
DVD+R/+RW, DVD-R/-RW, MP3-
CD, MP3-DVD, USB flash drive,
WMA-CD
2. Compression Format: x
Dolby Digital, MP3, MPEG2
Multichannel, PCM, WMA
3. MPEG1 bit rates: 64-384 kbps x
and VBR
Still Picture Playback
1. Playback Media: CD-R/RW, x
DVD+R DL, DVD+R/+RW, DVD-
R/-RW, Picture CD, USB Digital
Camera (PTP), USB flash drive
2. Picture Compression Format: x
JPEG, JPEG digital camera
photos
3. Picture enhancement: Slideshow x
with MP3 playback, Create
albums, Rotate, Slideshow with
music playback, Zoom
Safety Information, General Notes & Lead Free Requirements 3139 785 32801 2. EN 5
2. Safety Information, General Notes & Lead Free Requirements

2.1 Safety Instructions 2.2 Warnings
2.1.1 General Safety 2.2.1 General
Safety regulations require that during a repair: • All ICs and many other semiconductors are susceptible to
• Connect the unit to the mains via an isolation transformer. electrostatic discharges (ESD, ). Careless handling
• Replace safety components, indicated by the symbol , during repair can reduce life drastically. Make sure that,
only by components identical to the original ones. Any during repair, you are at the same potential as the mass
other component substitution (other than original type) of the set by a wristband with resistance. Keep
may increase risk of fire or electrical shock hazard. components and tools at this same potential.
Available ESD protection equipment:
Safety regulations require that after a repair, you must return – Complete kit ESD3 (small tablemat, wristband,
the unit in its original condition. Pay, in particular, attention to connection box, extension cable and earth cable)
the following points: 4822 310 10671.
• Route the wires/cables correctly, and fix them with the – Wristband tester 4822 344 13999.
mounted cable clamps. • Be careful during measurements in the live voltage
• Check the insulation of the mains lead for external section. The primary side of the power supply, including
damage. the heatsink, carries live mains voltage when you
• Check the electrical DC resistance between the mains connect the player to the mains (even when the
plug and the secondary side: player is ‘off’!). It is possible to touch copper tracks and/
1. Unplug the mains cord, and connect a wire between or components in this unshielded primary area, when
the two pins of the mains plug. you service the player. Service personnel must take
2. Set the mains switch to the ‘on’ position (keep the precautions to prevent touching this area or components
mains cord unplugged!). in this area. A ‘lightning stroke’ and a stripe-marked
3. Measure the resistance value between the mains printing on the printed wiring board, indicate the primary
plug and the front panel, controls, and chassis side of the power supply.
bottom. • Never replace modules, or components, while the unit is
4. Repair or correct unit when the resistance ‘on’.
measurement is less than 1 MΩ.
5. Verify this, before you return the unit to the customer/ 2.2.2 Laser
user (ref. UL-standard no. 1492).
6. Switch the unit ‘off’, and remove the wire between the • The use of optical instruments with this product, will
two pins of the mains plug. increase eye hazard.
• Only qualified service personnel may remove the cover or
2.1.2 Laser Safety attempt to service this device, due to possible eye injury.
• Repair handling should take place as much as possible
This unit employs a laser. Only qualified service personnel with a disc loaded inside the player.
may remove the cover, or attempt to service this device (due • Text below is placed inside the unit, on the laser cover
to possible eye injury). shield:
Laser Device Unit CAUTION VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID EXPOSURE TO BEAM
Type : Semiconductor laser ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING VED ÅBNING UNDGÅ UDSÆTTELSE FOR STRÅLING
ADVARSEL SYNLIG OG USYNLIG LASERSTRÅLING NÅR DEKSEL ÅPNES UNNGÅ EKSPONERING FOR STRÅLEN
GaAlAs VARNING SYNLIG OCH OSYNLIG LASERSTRÅLNING NÄR DENNA DEL ÄR ÖPPNAD BETRAKTA EJ STRÅLEN
VARO! AVATTAESSA OLET ALTTIINA NÄKYVÄLLE JA NÄKYMÄTTÖMÄLLE LASER SÄTEILYLLE. ÄLÄ KATSO SÄTEESEEN
Wavelength : 650 nm (DVD) VORSICHT SICHTBARE UND UNSICHTBARE LASERSTRAHLUNG WENN ABDECKUNG GEÖFFNET NICHT DEM STRAHL AUSSETSEN
DANGER VISIBLE AND INVISIBLE LASER RADIATION WHEN OPEN AVOID DIRECT EXPOSURE TO BEAM
: 780 nm (VCD/CD) ATTENTION RAYONNEMENT LASER VISIBLE ET INVISIBLE EN CAS D’OUVERTURE EXPOSITION DANGEREUSE AU FAISCEAU
Output Power : 20 mW
(DVD+RW writing) Figure 2-2
: 0.8 mW
(DVD reading)
: 0.3 mW
(VCD/CD reading)
Beam divergence : 60 degree
CLASS 1
LASER PRODUCT
Figure 2-1
Note: Use of controls or adjustments or performance of

procedure other than those specified herein, may result in
hazardous radiation exposure. Avoid direct exposure to beam.
EN 6 2. 3139 785 32801 Safety Information, General Notes & Lead Free Requirements
2.3 Lead Free Requirement • Special information for BGA-ICs:

- always use the 12nc-recognizable soldering temperature
Information about Lead-free produced sets profile of the specific BGA (for de-soldering always use
the lead-free temperature profile, in case of doubt)
Philips CE is starting production of lead-free sets from - lead free BGA-ICs will be delivered in so-called ‘dry-
1.1.2005 onwards. packaging’ (sealed pack including a silica gel pack) to
protect the IC against moisture. After opening, dependent
INDENTIFICATION: of MSL-level seen on indicator-label in the bag, the
BGA-IC possibly still has to be baked dry. (MSL=Moisture
Sensitivity Level). This will be communicated via AYS-
Regardless of special logo (not always indicated) website.
Do not re-use BGAs at all.
One must treat all sets from 1 Jan 2005 onwards, according
next rules. • For sets produced before 1.1.2005 (except products of
2004), containing leaded solder-alloy and components,
Example S/N:
all needed spare-parts will be available till the end of the
service-period. For repair of such sets nothing changes.
• On our website www.atyourservice.ce.Philips.com you

find more information to:
 BGA-de-/soldering (+ baking instructions)

 Heating-profiles of BGAs and other ICs used in Philips-
sets
You will find this and more technical information within the
“magazine”, chapter “workshop news”.
Bottom line of typeplate gives a 14-digit S/N. Digit 5&6 is the year, digit 7&8 is
the week number, so in this case 1991 wk 18
For additional questions please contact your local repair-helpdesk.
So from 0501 onwards = from 1 Jan 2005 onwards
Important note: In fact also products of year 2004 must be treated in this way as long as you
avoid mixing solder-alloys (leaded/ lead-free). So best to always use SAC305 and the higher
temperatures belong to this.
Due to lead-free technology some rules have to be respected by the

workshop during a repair:
• Use only lead-free solder alloy Philips SAC305 with

order code 0622 149 00106. If lead-free solder-pate
is required, please contact the manufacturer of your
solder-equipment. In general use of solder-paste within
workshops should be avoided because paste is not easy
to store and to handle.
• Use only adequate solder tools applicable for lead-free
solder alloy. The solder tool must be able
o To reach at least a solder-temperature of 400°C,
o To stabilize the adjusted temperature at the solder-tip
o To exchange solder-tips for different applications.
• Adjust your solder tool so that a temperature around
360°C – 380°C is reached and stabilized at the solder
joint. Heating-time of the solder-joint should not exceed
~ 4 sec. Avoid temperatures above 400°C otherwise
wear-out of tips will rise drastically and flux-fluid will be
destroyed. To avoid wear-out of tips switch off un-used
equipment, or reduce heat.
• Mix of lead-free solder alloy / parts with leaded solder
alloy / parts is possible but PHILIPS recommends strongly
to avoid mixed solder alloy types (leaded and lead-free).
If one cannot avoid or does not know whether product is
lead-free, clean carefully the solder-joint from old solder
alloy and re-solder with new solder alloy (SAC305).
• Use only original spare-parts listed in the Service-
Manuals. Not listed standard-material (commodities) has
to be purchased at external companies.
3.
Hard Disk / DVD Recorder DVDR3570H
DVDR3590H Connect Set
1 www.p4c.philips.com 2
Before connecting A Finding the viewin
Select the most suitable connection (A or B) based on
Quick Start Guide the type of device you have and your home set up.
A Press STANDBY-ON on
B Turn on the TV.
You can also refer to the accompanying User Manual for You should see the installa
other possible connections. M
Please select your language.
Defines the languages of all
on-screen menu displays.
A Connecting Recorder and TV B Connecting Recorder and TV

with antenna only with Cable TV or Satellite Receiver
Directions For Use
Next
Television ( rear) Satellite dish/

Television ( rear) Cable TV wall outlet
??
1 Connect ?
???
??
??
?
???
???
C In case you don’t see the r
press the Channel Down b
control repeatedly (or AV,
ant Set up R you see the menu. This is
channel for the recorder.
2
A
Antenna OUT IN
VIDEO AUDIO S-VIDEO RF
R L
3 Enjoy
C D B Start initial installa
da D C
A E Use the recorder’s remote con
CVBS OUT Y CVBS IN
CVBS OUT Y PB
HDMI
L L
CVBS IN
L
PB
HDMI
OUT
L L
B
L OUT
TV-OUT ANTENNA-IN PR PB Y
TV-OUT ANTENNA-IN
PR
PR PB Y
PR R R
screen instructions to complet
R R R
R MAINS
S-VIDEO OUT AUDIO COAXIAL COMPONENT COMPONENT VIDEO IN AUDIO 1 AUDIO 2 S-VIDEO IN
MAINS
VIDEO OUT AUDIO OUT DIGITAL OUT VIDEO OUT EXT 1 EXT 2
S-VIDEO OUT AUDIO COAXIAL COMPONENT COMPONENT VIDEO IN AUDIO 1 AUDIO 2 S-VIDEO IN
VIDEO OUT AUDIO OUT DIGITAL OUT VIDEO OUT EXT 1 EXT 2
E
ant A Select the desired language
What’s in the box? B Philips Recorder (rear) Philips Recorder (rear) screen menu display and pr
CVBS OUT CVBS IN
Y PB L
continue.
The following except of the Quick Use Guide serves as an introduction to the set.
PR R
R C
PAUSE LIVE TV S-VIDEO OUT AUDIO COAXIAL COMPONENT
Directions For Use
AUDIO 1 AUDIO 2 S-VIDEO IN Country selection is

VIDEO OUT AUDIO OUT DIGITAL OUT VIDEO OUT EXT 2 important for TV channels
search.
SUBTITLE AUDIO
INFO SELECT EDIT SCART
Previous Next
Hard Disk/ DVD Recorder Remote Control A Unplug the existing antenna cable from your TV and A Keep the existing antenna connection from the
d connect it to the ANTENNA IN socket on this Cable Box/Satellite Receiver to your TV.
and 2 batteries
recorder. B Connect the CVBS IN and AUDIO IN sockets on B Select the country you live
button to continue.
B Connect an RF antenna cable (supplied) from the the recorder to the corresponding video and audio
TV-OUT socket on this recorder to the output sockets on the Cable Box/Satellite Receiver. T
Antenna In socket on the TV. Alternatively, you may use COMPONENT Select the appropriate TV shape
� according to the TV you have
C Connect a composite cable (supplied) from the VIDEO or S-VIDEO connection. connected.
CVBS OUT socket on this recorder to the video C Connect a composite cable (supplied) from the
3139 785 32801
input socket on your TV. CVBS OUT socket on this recorder to the video
User
D Connect an audio cables (supplied) from the input socket on your TV. Previous Next
Manual
AUDIO OUT sockets on this recorder to the D Connect an audio cables (supplied) from the
audio input sockets on your TV. AUDIO OUT sockets on this recorder to the
E Plug in the power cable from the recorder to an AC audio input sockets on your TV. C Select the appropriate TV
RF antenna cable Audio/Video power outlet want the wide-screen movi
E Plug in the power cable from the recorder to an AC press the Green button to
(connect between cables
3.
power outlet.
recorder and TV)
The Complete Direction for the Use can be downloaded in different languages from the internet site of Philips Customer care Center:
V.
EN 7
Set up Enjoy EN 8
2 3 3.
Finding the viewing channel D Press OK to start automatic analogue channel

A search.
About the Time Shift Buffer About the internal hard disk
A Press STANDBY-ON on the recorder.
Channel search
(TSB) drive
B Turn on the TV. Start Auto search Once you turn on the recorder, the selected TV This recorder’s hard disk drive can be used as a Media
You should see the installation menu. programme will be stored in a temporary hard disk Jukebox, allowing you to store and playback your TV
storage called Time Shift Buffer ‘TSB’. The ‘TSB’ can programmes, videos, music and photos files.
Menu Language
Please select your language. English store up to 6 hours of programmes temporarily.
Defines the languages of all Simpl Chinese Press HOME on the remote control to access your
on-screen menu displays. Trad Chinese
Previous Skip Press INFO to display the Time Shift video bar. contents stored in the { Hard Disk }.
Start time of the Programmes
E Once complete, press the Green button to programme stored in the ‘TSB’
Next continue.
dish/ Now
all outlet Time
Select a record mode
3139 785 32801
22:04:30
??
Time setting is required for
?
???
??
??
?
???
C In case you don’t see the recorder’s setting menu, making recordings. 00 : 00 AM
???
Selected clips for Select an appropriate recording mode is important as it
press the Channel Down button on the TVs remote Present time
recording determines the picture quality and recording time to the
control repeatedly (or AV, SELECT, ° button) until Current time hard disk.
you see the menu. This is the correct viewing of playback
channel for the recorder. A Before recording, press OPTIONS on the
Previous Next Note The contents in the time shift video bar will be
A cleared when you press STANDBY ON (2). remote control.
IN B Select { Settings } in the menu and press OK.
F Enter the correct time in the entry field and press
B Start initial installation OK to confirm. C Move to { Recording } and press � right.
Use the recorder’s remote control and follow the on- D Move to { Record mode } and press � right.
screen instructions to complete the installation. Date
Watch TV – Pause live TV
INS Date setting is required to
E Select a record mode and press OK to confirm.
make recordings. Please 31 01 2007
E make sure it is correct.
Your Philips Recorder allows you to control the TV
A Select the desired language for this recorder’s on-
ar) programme. You can PAUSE it as if you were in control
screen menu display and press the Green button to DVDR3570H
of the live broadcast.
continue. Record Mode
Directions For Use
Country Selection Previous Next

A Turn on your recorder to the live TV mode and
Country selection is AUS Australia press P +/- to select a TV programme.
important for TV channels BMU American B.. HQ (high quality) 23 1 1 hr 55 mins
search. HK Hong Kong SP (standard play) 45 2 3 hrs 40 mins
NZ New Zealand�
B Press PAUSE LIVE TV to suspend it.
G Enter the correct date in the entry field and press SPP (standard play plus) 56 2.5 4 hrs 35 mins
PRC China
C Press PAUSE LIVE TV again to continue. LP (long play) 68 3 5 hrs 30 mins
RC Taiwan OK to confirm.
ROK Korea EP (extended play) 90 4 7 hrs 20 mins
SGP Singapore D To return to live broadcast, press LIVE TV. SLP (super long play) 135 6 11 hrs 5 mins
Previous Next Installataion Complete SEP (super extended play) 180 8 14 hrs 45 mins
the
You have successfully completed the installation
of your recorder. DVDR3590H
ockets on
B Select the country you live and press the Green
System is now ready for use. Colour Softkeys function
button to continue. Record Mode
nd audio
Receiver. Delete Copy Child Lock Protect
Previous Done
TV shape (250GB)
Select the appropriate TV shape 4:3 Panscan
T HQ (high quality) 40 1 1 hr 55 mins
according to the TV you have 4:3 Letterbox
connected. 16:9 Widescreen LIVE TV SP (standard play) 77 2 3 hrs 40 mins
SPP (standard play plus) 96 2.5 4 hrs 35 mins
the
H The installation is completed now, press the Green LP (long play) 115 3 5 hrs 30 mins
OPTIONS EP (extended play) 153 4 7 hrs 20 mins
button to close the menu.
he video SLP (super long play) 230 6 11 hrs 5 mins
SEP (super extended play) 300 8 14 hrs 45 mins
Previous Next
e PAUSE LIVE TV
The colour functions shown on the
o the
C Select the appropriate TV shape in the way you menu can be accessed by pressing the
want the wide-screen movies to be displayed and matching colour coded buttons on the
to an AC remote control. HOME
press the Green button to continue.
INFO
Hard Disk / D
Enjoy
3
Record to hard disk Copy TV programmes or files Start playback Q
A Record current TV programme A Copy TV programmes from hard C Copy files from Disc A Playback from hard disk
disk Copy prohibited contents cannot be copied to this
A Press REC to start recording. It can record up to A Press HOME.
recorder.
6 hours. A Insert a recordable DVD into the recorder.
B Press HDD LIST on the remote control. A Insert a CD/DVD into the recorder. Source Content
Note To set the recording time length, press REC Hard Disk Recordings
repeatedly to extend the recording time in 30-minute Disc Tray Video files
C Select a title to copy and press the Green button B Press HOME and select { Disc Tray }. USB Music
increments, up to 6 hours. Photo
on the remote control for { Copy }. C Use �� keys to reach the title/file you want to
B To stop the recording before the scheduled time, D The making disc copy information appears. Press copy.
press STOP. the Green button again to start copying. D Press the Green button on the remote control for
{ Copy }.
B Select { Hard Disk } and press � right.
Target for copy.
B Copy files from USB Choose destination for copy.
C Select the contents type and press � right.
B Mark a specific content in the Time
To Hard Disk D Use � � � � keys to reach the title/file you want
Shift Buffer for recording You can only copy the data files (MP3, WMA, DivX and
To USB to play and press u to start playback.
JPEG) from your USB device to the recorder’s hard disk
drive or recordable DVD.
E Select the destination for copying and press OK to
A Insert your USB device to the USB port at the front confirm.
B Playback from disc
panel of the recorder. Note Only data files are able to copy to USB device.
21:00 23:30 A Hold down STOP until the disc tray opens. Load a
22:13
B Press USB on the remote control to view the
F Press OK again to start copying. disc and close the disc tray.
Cancel Rec. More Info content menu.
B Press HOME and select { Disc Tray }.
C Use ��
�� keys to reach the file you want to
copy. C Use � � � � keys to reach the title/file you want
A Press � left or � right to search for the scene
D Press the Green button on the remote control for
to play and press u to start playback. What’s
where you want to record.
{ Copy }.
B Press REC to start recording from here. HDD LIST
Target for copy. USB
Note Pressing the Red button will cancel the Choose destination for copy. C Playback from USB device
Directions For Use
recording. To Hard Disk

To Disc
A Insert the USB device to the USB port.
C Press � right to search for the scene to end the B Press USB to show the contents list.
recording, then press STOP. E Select the destination for copying and press OK to HOME C Select the contents type and press � right.
confirm.
Note The title will be marked in red and the D Select a data file (MP3, WMA, DivX and JPEG) and
recording will only take effect when you turn off the Note If select { To Disc }, insert an empty press u to start playback.
recorder. recordable DVD into the recorder.
F Press OK again to start copying.

HDD LIST REC STOP
USB
3139 785 32801
HOME
Need help?
User Manual
See the user manual that came with your Philips Recorder RF antenna ca
REC STOP (connect betwe
Online recorder and T
3.
Go to www.philips.com/welcome
2007 © Koninklijke Philips N.V.
All rights reserved.
12 NC 3139 245 27481
www.philips.com
EN 9
EN 10 4. 3139 785 32801 Mechanical Instructions
4. Mechanical Instructions
Note: The position numbers given here refers to the
Exploded view on chapter 8.
4.1 Dismantling of the DVD Tray cover manually

1) Insert a screwdriver into the slot provided at the bottom
of the set and push in the direction as shown in Figure1 to
unlock before sliding the Tray cover 110 out.
Insulation Sheet Insulation Sheet

1
Figure 4-4: Front Panel Service Position
4.3 Dismantling of the Basic Engine
2 1) Remove 4 mounting screws as shown in figure 5 to

dismantle the Basic Engine. 1007.
Figure 4-1: Unlock the tray loader
2) Remove the Tray cover 110 as shown in Figure 2.
Figure 4-2: Remove the tray cover
Figure 4-5: Basic Engine mounting screw

4.2 Dismantling of the Front Panel
1) Remove 7 screws to loosen Top cover 240.
2) Remove 2 screws to loosen the Plate Front Loader 183
and detach the Front Cabinet Assembly P001 as shown
in Figure 3. The Front Panel Service Position is shown in
Figure 4.
Figure 4-3: Unscrew the screws to detach front panel

Mechanical Instructions 3139 785 32803 4. EN 11
2) Flip the Basic Engine over to remove 4 screws from 2) Service position for PSU Board is given in Figure 8.
the PCB protection plate. Service Position of the Basic
Engine is shown in Figure 6.
Insulation Sheet
Insulation Sheet
Figure 4-6: Basic Engine Service Position
Figure 4-8: PSU Board Service Position

4.4 Dismantling of the PSU Board
1) Remove 3 screws to loosen the PSU Board 1004 as 4.5 Dismantling of the HDD
shown in Figure 7.
1) Remove 4 screws to loosen the HDD assembly (HDD
1005 and HDD Bracket 186 attached together by the
screws 271, for DVDR3590H there also includes HDD
Damper 191 and HDD Suspension Bracket 192) as
shown in figure 9.
Figure 4-7: PSU remove mounting screws
Figure 4-9: Remove mounting screws for HDD
2) Flip over the HDD Assembly to see the mounting screws

271. Remove the screws to dismantle the HDD 1005 from
the HDD assembly.
Notes: Only the special type of screws as described in

Service Parts List must be used for position number 271.
Using improper screws may damage the mounting holes on
the HDD.
.
EN 12 4. 3139 785 32801 Mechanical Instructions
4.6 Dismantling of HDMI Board 4.7 Dismantling of the Digital Board

1) Remove 2 screws to loosen the HDMI Board 1006 and 1) Remove the HDMI Board first, and remove the HDMI
HDMI Shield 190 form the Rear Plate 230. The mounting Bracket 131 by unscrewing one screw.
screws are shown in figure 10. 2) Then remove 4 screws to loosen the Digital Board 1003
as shown in Figure 12.
Figure 4-10: Remove mounting screws for HDMI Board

Figure 4-12: Remove mounting screws for Digital Board
2) Remove the HDMI Shield 190 for HDMI Board Service

Position. The HDMI Board Service Position is shown in
figure 11.
Insulation
Sheet
Figure 4-11: HDMI Board Service Position.

Mechanical Instructions 3139 785 32801 4. EN 13
3) Service position for Digital Board is given in Figure 13. 4.8 Dismantling of the Analog Board
(It may be necessary to remove the Digital Board Bracket
187 and take out the cables beneath it to make it easier to 1) Remove the HDMI Board 1006 with its Shield 190 and
flip over the digital board. Put the insulation sheets under the HDMI bracket 189 first. Remove 3 screws that attach
the PC Boards. Refer to the set-wiring diagram in chapter the Analog Board 1001 to the Frame 161. Remove 6
6 and make it sure to have the correct cable connections more screws that attach the Analog Board 1001 to the
among the PC Boards.) rear panel 230. Then dismantle the Analog Board. It may
be easier to dismantle the Analog Board if the rear panel
230 is detached first by removing 3 more screws.
Insulation 2) Service position for Analogue Board is given in Figure 12.
Sheet
Insulation
Sheet
Figure 4-14: Analogue Board Service Position (Rear Plate 230

detached)
Insulation
Sheet
Figure 4-13: Digital Board Service Position

EN 14 5. 3139 785 32800 Firmware Upgrading & Diagnostic Software
5. Firmware Upgrading and Useful Firmware Hints, Diagnostic

Software, Alignment and Test Procedures
5.1 Firmware Upgrading
5.1.1. Preparation to upgrade firmware
1. Unzip the zip-archive file

2. Start the CD Burning software and create a new CD project (data disc) with the following settings:
File system: Joliet
Format: MODE 2: CDROM XA
Recording mode: SINGLE SESSION (TRACK-AT-ONCE), FINALIZED CD
Note: Long file name is necessary for the preparation of the upgrade disc
3. Place the content of the zip-archive into the root directory of the new CD project.
4. Burn the data onto a blank CDR or CD-RW
5.1.2. Procedure to apply the firmware upgrade:
Notes: There are 2 upgrade processes supported: - Normal Upgrade and Forced Download.
For normal upgrading, power up the set, open the tray, insert the upgrade disc, close the tray and follow the on screen
instruction. For forced download upgrading, follow the procedures described below.
1. Hold the <Record> + <Next> buttons down and Power up the set.
2. The tray opens and set will display:
DOWNLOAD −>……….INSERT DISC
3. Insert the prepared Upgrade CDROM and close the tray.
4. The set will display:
INIT DISC −> DOWNLOAD −>……….
The whole process takes less than 10 minutes
Note: Do not press any buttons or interrupt the mains supply during the upgrading process, otherwise the set may
becomes defective.
5. When the upgrade is completed the tray will open automatically and the set will display:
REMOVE DISC
6. Close the tray and the set will display:
DONE
7. The set will go into Standby mode.
5.1.3. How to read out the firmware version to confirm set has been upgraded:
Notes: In order to check the firmware version of the set, user version info screen should be accessed. Follow the
procedure below for checking user version info screen.
1. Power up the set

2. Press <OPTIONS> button on the Remote control and go to <Settings> option
3. Then go to <Setup> and choose <Version Info> by pressing OK.
4. The TV connected to the set will display the user version info as shown below for checking software version:
Version Info
Royal Philips
DVDR3570H
Software version: 01.00
Please visit our website
www.philips.com/support
for further software
updates and additional information
Developer name: Royal Philips

Product name (xxxx = model number): DVDRxxxxH (DVDR3570H in the example above)
Official SW release number: Software Version (xx.xx = release): xx.xx (01.00 in the example above)
5. Press <OPTIONS> button to exit.
Firmware Upgrading & Diagnostic Software 3139 785 32803 5. EN 15
5.2. Procedure for checking Development Version Info Screen
Notes: For detail software information such as Slash Version, Drive Software Version, etc of the set,
the development version info screen should be accessed.
1) Power up the set

2) Press <OPTIONS> button on the Remote control and go to <Settings> option
3) Then go to <Setup> and choose <Version Info> by pressing OK.
4) When the user version info screen is appeared, press the blue key on the remote control.
5) The TV connected to the set will display the Development Version Info Screen as shown below:
Version Info
(c)PHILIPS 2006 Version Information:

DI L+06_7/751731 SV 11602
BE 52.07.02.15 ASP 1,18,1,10
C1_7 20070224_1659 pro lecoplusleadV2 <void>
EPG: DPMS:P_DPM
Digital Board Info: (DI: Digital Board, L+06_7: Digital Board name, 75: Hardware ID for EU Non EPG, 1731: SW
BUILD ID for recorder application in the example)
Slash Version (xxxxx = version): SV xxxxx (11602 for /51 in the example above)
Drive SW Version (yy.yy = model, xx.xx = version): BE yy.yy.xx.xx (Model 52.07, Version 02.15 in the example)
ASP Software and VFD Driver Version Number: (1,18: ASP software version number, 1,10: version number of
VFD Driver
Detailed Build Information: (C1_7: Branch Information, 2007: year, 02: month, 24: date, 16: Hour, 59: minute in
the above example)
EPG: DPMS:P_DPM (internal to the recorder application.)
5.3 Procedure for Formatting HDD drive

1) Press and Hold the <Previous> + <Stop> key combination while powering on the mains.
2) The set will start to display “FMT KEY”, and then it will show “FMT HDD” while formatting HDD.
3) If the formatting is completed successfully, the set will display “FMT DONE”. If the formatting is failed, it will show “FMT FAIL”
Notes: Do not power off the set immediately when the “FMT DONE” is seen. Wait until the time or - - : - - is displayed before powering
off the set.
5.4. Procedure to Virginize the set
Notes: All the user information will be lost after virginizing the set. Follow the procedure below to virginize the set.
1) Press and hold down the Standby key on the front while connecting to the power outlet.
2) Release the keys when the scrolling messages appear on VFD.
3) Press standby key again and follow the instructions when the set wakes up.
5.5 HDD replacement procedure.

When a defective HDD is replaced by a brand new HDD,
1. Install the new HDD.

2. Upgrade the software (forced download) with the upgrade disc to the latest software (follow the procedures described in 5.1.2)
3. Format the HDD (follow the procedures described in 5.3)
The HDD is ready to use. Some of the user information may be lost after HDD Replacement.
Diagnostic Software
Due to the complexity of the DVD recorder, the time to find a 5.5.2 Structure
defect in the recorder can become long. To reduce this time,
the recorder has been equipped with Diagnostic and Service
software (DS). Th e DS offers functionality to diagnose the Unplug the power cord
DVDR hardware and te sts the following: Hold key <PLAY> pressed
• Interconnections between components while you plug the recorder
• Accessibility of components
• Functionality of the audio and video paths
During the test, the display will show
This functionality can be accessed via several interfaces: the a sequence of nuclei under test
1. End user/Dealer script interface

2. Command Interface
NO
SET O.K.?
5.6 End User/Dealer Script Interface YES
5.6.1 Description
The End user/Dealer script interface gives a diagnosis on a

stand alone DVD recorder. During this mode, a number of To exit DEALER SCRIPT, unplug the power cord
hardware tests (nuclei) are automatically executed to check if TR 18029_001

the recorder is faulty. The diagnosis is simply a "fail" or "pass" 120304
message. If the message "FAIL" appears on the display, there
is apparently a failure in the recorder. If the message "PASS" Figure 5-1
appears, the nuclei in this mode have been executed
successfully. There can be still a failure in the recorder The End use/Dealer script executes all diagnostic nuclei that
because the nuclei in this mode do not cover the complete do not need any user interaction and are meaningful on a
functionality of the recorder. standalone DVD recorder.
5.6.2 Contents
Included tests: 1. DS_CHR_DEVTYPEGET_NUC

2. DS_SDRAM_WRITEREADFAST_NUC
3. DS_FLASH_DEVTYPEGET_NUC
4. DS_FLASH_CHECKSUMPROGRAM_NUC
5. DS_VIP_COMMUNICATION_NUC
6. DS_VIP_DEVTYPEGET_NUC
7. DS_DVIO_LINKDEVTYPEGET_NUC
8. DS_DVIO_PHYCOMMUNICATION_NUC
9. DS_DVIO_PHYDEVTYPEGET_NUC
10. DS_BE_COMMUNICATIONECHO_NUC
11. DS_BE_VERSIONGET_NUC
12. DS_SYS_HARDWAREVERSIONGET_NUC
13. DS_SYS_SOFTWAREVERSIONBOOTGET_NUC
14. DS_SYS_SOFTWAREVERSIONDOWNLOADGET_NUC
15. DS_SYS_SOFTWAREVERSIONAPPLGET_NUC
16. DS_SYS_DVIDNUMBERGET_NUC
17. DS_SYS_SLASHVERSIONGET_NUC
18. DS_SYS_SETTINGSDISPLAY_NUC
19. DS_SYS_BUILDINFOGET_NUC
20. DS_ASP_COMM_NUC
21. DS_ASP_VERSION_NUC
22. DS_FRE_COMM_NUC
23. DS_HDD_COMMUNICATION_NUC
24. DS_HDD_VERSION_NUC
25. DS_USB_DEVTYPEGET_NUC
5.7 Menu and Command Mode Interface
5.7.1 Nuclei Numeration 5.7.2 Error Handling
Each nucleus has a unique number of four digits. This number Each nucleus returns an er ror code. This c ode contains six
is the input of the command mode. numerals, which means:
[ XX YY ] [ XX YY ZZ ]
Error code
Nucleus number Nucleus number
Nucleus group number Nucleus group number
CL 06532152_013.eps
CL 06532152_012.eps 051200
051200
Figure 5-2 Figure 5-3
The nucleus group number s and nucleus numbers are the

Group number Group name
same as above.
0 Scripts
1 Codec (e.g. LeCo+) 5.7.3 Command Mode Interface
2 Boot EEPROM*
3 NVRAM (EEPROM of FLASH)* Set-Up Physical Interface Component s
4 SDRAM (or DDR-RAM) Hardware required:
• Service PC
5 FLASH
• one free COM port on the Service PC
6 Video Input Processor • special cable to connect DVD recorder to Ser vice PC
7 DVIO The service PC must have a terminal emulation program (e.g.
9 Basic Engine Hyperterminal) installed and must have a free COM port (e.g.
12 System COM1). Activate the terminal emulation program and check
that the port settings for the free COM port are: 19200 bps, 8
15 HDMI
data bits, no parity, 1 stop bit and no flow control. The free COM
16 Analogue Slave Processor port must be connected via a special cable to the RS232 port
20 Front End of the DVD recorder. This special cable will also connect the
21 Hard Disk test pin, which is available on the connector, to ground (i.e.
22 DTTM* activate test pin).
Code number of PC interface cable: 3122 785 90017
23 USB
Activation of Diagnostic Software

* Not applicable for DVDR3570H, 1. Pull the mains cord from the recorder and reconnect it
again (reboot).
2. The next welcome message will appear on the PC:
Welcome screen D&S program
Figure 5-4
Now, the prompt 'DS:>' will appear. The diagnostic software is

now ready to receive commands. The com mands that can be
given are the numbers of the nuclei. If you see above shown
screen, continue with paragraph 'Nuclei Codes'.
3. It is possible that the next messages will appear when Enter "Y" to program a safe string. With this automatically
starting the DVD+RW for the first time generated string the board will work in principle but it has to be
checked if all board settings were detected correctly.
Error messages D&S program
Diversity String Input
4. Execute nucleus 1226 to enter the string. Please see

chapter 8 for details
Nucleus 1226 execution with string
Figure 5-5a
Error messages D&S program
Figure 5-6
5. To check if the hardware info is filled correctly, you can

execute nucleus 1228.
Nucleus 1228 info example
Figure 5-5b
In these cases, the boot EEPROM of the Digital Board does not
contain the required string with the hardware information. To
update the Digital Board with the correct string, nucleus 1226
must be executed.
See next section 'Diversity String Input'.

There can also be the next error message.
Figure 5-7
6. Exit the 'Terminal' program.
7. Reboot the DVD recorder to allow the software to start.
Figure 5-5c
Command overview Digital Board

Below you will find an overview of the nuclei, their numbers,
and their error codes. This overview is preliminary and
subject to modifications.
Codec Host Controller (CHR)
Nucleus Name DS_CHR_DevTypeGet

Nucleus Number 100
Description Retrieves the device id, the module ids and revisions of the Codec and returns
them to the stdout port.
Technical - Determine the codec id by means of comparing version ids of the modules.
- Read the module-id register of every module and display it to the user.
Execution Time Less than 1 second.
User Input None
Error Number Description
10000 Getting the information succeeded
10001 Wrong codec id detected
Example DS:> 100
010000:
Device ID 7300
Codec ID PNX7350
F-BCU (0x0102) 4.0 INTC (0x011d) 3.0
SIF (0xa04b) 2.0
BOOT (0x010a) 3.1 CONFIG (0x013f) 5.0 RESET (0x0123) 5.0
CLOCK (0x013e) 7.0 DEBUG (0x0116) 0.1 UART0 (0x0107) 1.2
UART1 (0x0107) 1.2
I2C0 (0x0105) 0.1 I2C1 (0x0105) 0.1 GPIO (0x013c) 3.1
SYNC (0x013a) 4.0
OSD (0x0136) 1.0 SPU (0xa00e) 1.1 MIXER (0x0137) 3.0
DENC (0x0138) 5.0 CCIR (0x0139) 2.1 VDEC (0x0133) 1.0
PARSER (0xa00d) 0.0 DV (0xa00c) 0.0
IDE0 (0xa009) 1.2 IDE1 (0xa009) 1.2 SGDX (0xa008) 4.0
BYTE (0xa00b) 1.0 OUTPUT (0xa003) 8.0 ACOMP (0xa000) 8.0
VFE (0xa001) 8.0 VCOMP (0xa002) 8.0 SCR (0xa004) 8.0
SIFF (0xa011) 3.0
PSCAN (0xa05d) 0.1
ADEC (0x0134) 1.1 IR (0x0131) 2.0 AOI (0xa08c) 0.0
PIP (0xa04d) 1.0 AVLINK (0x3601) 2.1 USBLINK(0xa08e) 0.0
MSVD (0xa087) 0.0 FEBCU (0xa05e) 1.0 BM (0xa085) 0.0
BMI (0xa084) 0.0 DISP (0xa04d) 1.0
Test OK @
Nucleus Name DS_CHR_TestImageOn

Nucleus Number 101
Description Generates a test-image of a selected video standard on selected video output
on the digital board. When no input is given, the default values will be used (see
user input description below). Make sure to use the proper nuclei to route the
video signal on the VIP to get the video signal to the proper output.
Technical - Validate the user input.
- Initialise the SYNC module.
- Initialise the DISPLAY module.
- Initialise the MIXER module.
- Initialise the DENC module.
- Set the selected video standard.
- Generate the selected test image in memory.
- Start the DISPLAY module.
- Start the MIXER module.
- Start the DENC module according to the selected test image id.
Execution Time 6 seconds.
User Input The user has to decide which test image, video standard and video output must
be used: < Test image id > < Video standard > < Video output >
Test image id:

0 VERTICAL_COLOURBAR (default)
1 HORIZONTAL_COLOURBAR
2 WHITE
3 YELLOW
4 CYAN
5 GREEN
6 MAGENTA
7 RED
8 BLUE
9 BLACK
10 GRAY
11 TEST_IMAGE_FOR_PROGRESSIVE_SCAN
Video standard:
PAL Standard PAL 50 Hz (default)
NTSC Standard NTSC 60 Hz
Video output:
ALL CVBS and YC and RGB signals are enabled (default)
ALL_RGB CVBS and YC and RGB signals are enabled (default)
ALL_YUV CVBS and YC and YUV signals are enabled
CVBS CVBS signal is enabled
YC YC signal are enabled
RGB CVBS, and RGB signals are enabled
YUV YUV signals are enabled
PSCAN Progressive scan is enabled

10100 Generating the test image succeeded.
10101 Invalid input was provided.
10102 The Codec SYNC-module cannot be initialised.
10103 The Codec MIXER-module cannot be initialised.
10104 The Codec VPP-module cannot be initialised.
10105 The Codec DENC-module cannot be initialised.
10106 The digital board hardware information is corrupt
Example DS:> 101
010100:
Test OK @
DS:> 101 0 pal cvbs

010100:
Test OK @
DS:> 101 4 ntsc yc

010100:
Test OK @
Nucleus Name DS_CHR_TestImageOff

Nucleus Number 102
Description Switches the test-image off.
Technical - Stop the DENC module.
User Input None
10200 Stopping the test image generation succeeded
10201 The Codec DENC-module failed.
Example DS:> 102
010200:
Test OK @
Nucleus Name DS_CHR_SineOn

Nucleus Number 103
Description Generate an audio sine signal on the audio output of the digital board.
Note: Left channel 6kHz, right channel 12 kHz sine. Make sure to route the
signal first.
When ‘SPDIF’ is entered as a parameter, the SPDIF path will be activated
correctly to generate a PCM sine wave on the digital audio output.
Technical - De-mute the analogue board
- Set fifo parameters for audio
- Set the volume
- Set the I2S outputs and configuration paths
- Set the decoder mode
- Configure the audio decoder
- Put the AC3 audio in the fifo
- Send ‘prepare’ command to the audio decoder
- Send ‘play’ command to the audio decoder
Execution Time Less than 1 second
User Input None or ‘SPDIF’
10300 The sine signal was successfully generated
10301 The analogue board could not be de-muted
10302 The audio decoder did not initialise
10303 The dsp2 (DUET) of the audio decoder did not configure
10304 The dsp1 (PALM) of the audio decoder did not configure
10305 There was a delay-error before starting
10306 Wrong input was given to the decoder function
10307 Wrong input was given to the decoder function @@@@@
10308 The audio decoder did not get into the ‘prepared’ state
Example DS:> 103
010300:
Test OK @
DS:> 103 spdif

010300:
Test OK @
Nucleus Name DS_CHR_SineOff

Nucleus Number 104
Description Stop generating the audio sine signal
Technical - Reset the audio block of the Codec
User Input None
10400 Switching off the audio sine signal succeeded
10401 Failed to reset the audio decoder
Example DS:> 104
010400:
Test OK @
Nucleus Name DS_CHR_SineBurst

Nucleus Number 105
Description Generate an audio sine signal on the audio output of the digital board for 4
seconds.
Note: Left channel 6kHz, right channel 12 kHz sine with some known hick-ups
Technical - Call the DS_CHR_SineOn nucleus
- Delay for 4 seconds
- Call the DS_CHR_SineOff nucleus
Execution Time 4 seconds
User Input None
10500 The sine signal burst was successfully generated
10501 The delay did not succeed during the burst
10502 The audio sine could not be generated
Example DS:> 105
010500:
Test OK @
Nucleus Name DS_CHR_MuteOn

Nucleus Number 106
Description Mute the audio outputs of the digital board
Technical - Send the ‘Mute’ command to the audio decoder
- Activate the ‘audio mute’ PIO pin
User Input “PIO” to just use the PIO pin mute. When muting using this, also de-mute using
this as this works ‘paired’.
10600 Muting the audio succeeded
10601 Muting the audio through the PIO-pin failed
Example DS:> 106
010600:
Test OK @
DS:> 106 PIO

010600:
Test OK @
Nucleus Name DS_CHR_MuteOff

Nucleus Number 107
Description De-mute the audio outputs of the digital board
Technical - Send the ‘DeMute’ command to the audio decoder
- Deactivate the ‘audio mute’ PIO pin
Execution Time “PIO” to just use the PIO pin de-mute. Only de-mute using this when you muted
using the PIO parameter, as this works ‘’paired.
User Input None
10700 De-muting the audio succeeded
10701 De-muting the audio through the PIO-pin failed
Example DS:> 107
010700:
Test OK @
DS:> 107 PIO

010700:
Test OK @
Nucleus Name DS_CHR_MacroVisionOn

Nucleus Number 110
Description Turn on MacroVision.
Technical - Set some registers of the DENC module in the Codec.
User Input None
11000 Turning on MacroVision succeeded
11001 Turning on MacroVision failed
Example DS:> 110
011000:
Test OK @
Nucleus Name DS_CHR_MacroVisionOff

Nucleus Number 111
Description Turn off MacroVision.
Technical - Set some registers of the DENC module in the Codec.
User Input None
11100 Turning off MacroVision succeeded
11101 Turning off MacroVision failed
Example DS:> 111
011100:
Test OK @
Nucleus Name DS_CHR_Peek

Nucleus Number 112
Description Peek a value on a specified address
Technical - Check the user input
- Read out the address specified
- Check whether the address to be read is aligned on 4 bytes
User Input The address to peek on
11200 Peeking on the specified address succeeded
11201 Peeking on the specified address failed, wrong user input
11202 Peeking on the specified address failed due to misalignment
Example DS:> 112 0xa0700000
011200: Value read = 0x000001BD
Test OK @
Nucleus Name DS_CHR_Poke

Nucleus Number 113
Description Poke a value on a specified address
- Change the value on the address specified
- Check whether the address to be modified is aligned on 4 bytes
User Input The address to poke and the value: <address><value>
11300 Poking the specified address succeeded
11301 Poking the specified address failed, wrong user input
11302 Poking the specified address failed due to misalignment
Example DS:> 113 0xa0700000 0xaabbccdd
011300:
Test OK @
Nucleus Name DS_CHR_INT_PICInterrupts

Nucleus Number 114
Description Test all interrupts of the priority interrupt controller
Technical - Install interrupt handlers
- Generate interrupts
- Test whether all interrupts were received
User Input -
11400 Testing all the PIC interrupts succeeded
11401 Testing all the PIC interrupts failed
Example DS:> 114
011400:
Test OK @
Nucleus Name DS_CHR_DMA_TestDMA

Nucleus Number 115
Description Test the memory to memory DMA transfer
Technical - Create a block with known data in memory
- Copy this block to the consecutive area using 4 different DMAs
- Check whether all DMAs transferred the data properly
Execution Time Less than 2 seconds.
User Input -
11500 The testing of the DMAs succeeded
11501 The initialisation of the DMAs failed for one or more DMA
11502 One or more DMAs failed the test
Example DS:> 115
011500:
Test OK @
Nucleus Name DS_CHR_PioGet

Nucleus Number 116
Description Get a value from a PIO pin
Technical - Decode user input
- Read the PIO input register of the codec and return the requested pio line
value
User Input <PIN>
where PIN is the pio pin to get (0..31)
11600 Getting PIO value succeeded
11601 Invalid parameter
Example DS:> 116 15
011600: Value read = 0x1
Test OK @
Nucleus Name DS_CHR_PioSet

Nucleus Number 117
Description Set a value on a PIO pin. Make sure that the pin is configured as output first
- Update the PIO output register of the codec
User Input <PIN> <VALUE>
where PIN is the pio pin to set (0..31)
and VALUE the value of the pin (0..1)
11700 Setting PIO value succeeded
Example DS:> 117 15 0
011700:
Test OK @
Nucleus Name DS_CHR_PioConfig

Nucleus Number 118
Description Configure a PIO pin
- Update the PIO configuration register of the codec
User Input <PIN> <DIR>
where PIN is the pio pin to set (0..31)
and DIR the direction of the pin (0=IN 1=OUT)
11800 Setting PIO configuration succeeded
Example DS:> 118 14 0
011700:
Test OK @
SDRAM (SDRAM OR DDR-RAM)

Nucleus Name DS_SDRAM_WriteRead
Nucleus Number 400
Description Check all data lines, address lines and memory locations of the RAM
Technical - Test the data bus
- Test the address bus
- Test the integrity of the device itself (memory locations)
Execution Time 11 seconds for 32 Mb
23 seconds for 64 Mb
User Input None
40000 The write-read test succeeded
40001 The data bus contains an error
40002 The address bus contains an error
40003 The RAM itself contains an error
Example DS:> 400
040000:
Test OK @
Nucleus Name DS_SDRAM_WriteReadFast

Nucleus Number 401
Description Check all data lines and address lines of the RAM
Technical - Test the data bus
- Test the address bus
User Input None
40100 The write-read test succeeded
40101 The data bus contains an error
40102 The address bus contains an error
Example DS:> 401
040100:
Test OK @
Nucleus Name DS_SDRAM_Write

Nucleus Number 402
Description Write to a specific un-cached memory address
Technical - Decode the user input and check its ranges and alignment on 4 bytes
- Write the data to the RAM
User Input 1. The location that must be modified
(RAM starts at address 0xA0000000)
2. The value to put on the selected location
40200 Writing to the RAM succeeded
40201 Writing to the RAM failed; Wrong user input
40202 Address is not dividable by 4
Example DS:> 402 0xa1000010 0xad112222
040200:
Test OK @
Nucleus Name DS_SDRAM_Read

Nucleus Number 403
Description Read from a specific un-cached memory address
Technical - Decode the user input and check the ranges
- Read from the RAM and return this info to the user
User Input The location from which the data must be read
(RAM starts at address 0xA0000000)
40300 Reading from the RAM succeeded
40301 Reading from the RAM failed; Wrong user input
Example DS:> 403 0xa1000010
040300: Value read = 0xAD112222
Test OK @
Nucleus Name DS_SDRAM_DmaWriteRead

Nucleus Number 404
Description Write a pattern to the entire RAM using DMA and check the data
Technical - Check if the Stack pointer is not in the write range
- Clear a 64kb block and then fill it with a pattern
- Initialise the DMA controller and write the data to the SDRAM
- Then check if all the data was written correctly (except descriptor tables)
- Repeat the process 4 times with 4 different patterns
User Input None.
40400 Writing to the RAM succeeded
40401 Stack area definition ERROR!
40402 DMA controller could not be initialised.
40403 Not all data was transferred correctly
Example DS:> 404
040400:
Test OK @
FLASH (FLASH)
Nucleus Name DS_FLASH_DevTypeGet
Nucleus Number 500
Description Get the device (revision) type information of the FLASH ICs. (type,
manufacturer, device ID and size)
Technical - Set the timing for the flash writing
- Write a command sequence to determine device type information
- Return the information to the user
User Input None
50000 Getting the information from the FLASH succeeded
50001 Getting the information from the FLASH failed
Example DS:> 500
050000: Found FLASH memory:
NOR AMD 29DL640G 8MB,NOR AMD 29DL640G 8MB
Test OK @
Nucleus Name DS_FLASH_Read

Nucleus Number 502
Description Read from a specific memory address in FLASH
Technical - Decode the user input and check the ranges and whether the address is
aligned on 4 bytes
- Read the data and return this to the user
User Input The location from which data must be read
(FLASH starts at address 0xB8000000)
50200 Reading the FLASH succeeded
50201 Reading the FLASH failed; Wrong user input
Example DS:> 502 0xb8000000
050200: Value read = 0x3C08A000
Test OK @
Nucleus Name DS_FLASH_ChecksumProgram

Nucleus Number 503
Description Check the checksum of the application partitions by recalculating and
comparing partition checksums
Technical - Determine the number of segments
- Find the application in each segment and determine its checksum
- Check whether the checksums stored match the newly calculated
User Input None
50300 The checksum is valid, the test succeeded
50301 The checksum is invalid
Example DS:> 503
050300:
BootCode checksum is: 0xBABE5B6F, which is correct
Diagnostics checksum is: 0xBABEBAFF, which is correct
Download checksum is: 0xBABEEDBF, which is correct
Application checksum is: 0xBABE8EEC, which is correct
Test OK @
Nucleus Name DS_FLASH_CalculateChecksum

Nucleus Number 504
Description Calculate the checksum over all memory addresses. Used to check entire
FLASH contents
Technical - Run the checksum calculation algorithm on all flash memory addresses
User Input None
50400 Calculating the checksum over all addresses succeeded
Example DS:> 504
050400: The Checksum = 0xBABE30A4
Test OK @
Nucleus Name DS_FLASH_CalculateChecksumFast

Nucleus Number 505
Description Calculate a checksum over a selected number of address locations
Technical - Run the checksum calculation algorithm on a selected number of flash
memory addresses
User Input None
50500 Calculating the checksum over selected addresses succeeded
Example DS:> 505
050500: The Checksum = 0xBABEB064
Test OK @
Nucleus Name DS_FLASH_EraseFlfs

Nucleus Number 506
Description Erase the complete Flash File system segment in flash memory. This will erase
all non volatile data including diversity string and DV unique ID number
Technical - Initialise Flash access
- Search in flash for the segment with the “FLFS” and “FLF2” signature
- Ask the user whether he is sure to erase all data
- If available erase the sector containing the FLFS signature
- If available erase the sector containing the FLF2 signature
Important note: This nucleus will erase all data, make sure to reboot after this and
program a diversity string
Execution Time About 1 second per block erased.
User Input None
50600 FLFS successfully erased
50601 User aborted the test
50602 FLFS segment is not available
Examples DS:> 506
Do you readlly want to erase the entire FLFS ? [Y /N(Default)] :y
Erasing FLFS...
050600: All data has been erased

Test OK @
DS:> 506
Do you readlly want to erase the entire FLFS ? [Y /N(Default)] :n
FLFS not erased.
050601: User abort

Test OK @
DS:> 506
Do you readlly want to erase the entire FLFS ? [Y /N(Default)] :y
Erasing FLFS...
050602: No FLFS segment found

Error @
VIDEO INPUT PROCESSOR (VIP)

Nucleus Name DS_VIP_DevTypeGet
Nucleus Number 600
Description Get the device (revision) type information of the VIP IC
Technical - Initialise IIC
- Read out the device (revision) type information of the VIP IC
User Input None
60000 Getting the information from the VIP succeeded
60001 The IIC bus initialisation failed
60002 The was an error getting the information from the VIP
60003 Type not according to type stored in HW diversity string
Example DS:> 600
060000: Found SAA7136
Test OK @
Nucleus Name DS_VIP_Communication

Nucleus Number 601
Description Check the communication between the IIC controller of the Codec and the VIP
IC
Technical - Initialise IIC
- Read data from a location in the VIP
User Input None
60100 Communicating with the VIP succeeded
60101 The IIC bus was not accessible
60102 There was a timeout reading the device
60103 The IIC acknowledge was not received
60104 The communication with the device failed
Example DS:> 601
060100:
Test OK @
Nucleus Name DS_VIP_SelectInput

Nucleus Number 604
Description Select an input video path to be switched to the analogue output pin (AOUT) of the
VIP
User Input Select an input video path (id) to be switched to the analogue output pin (AOUT1)
of the VIP.
Available channels for input of the SAA7136 and their description:

Id VIP Input source EURO Input source NAFTA
input
1 AI11 tuner_scart2-cvbs_in reserved
2 AI12 leco-cvbs_in1 rear-y_cvbs_in
3 AI13 front-y_in front-y_in
4 AI21 scart2_c_r_in rear-pr_in
5 AI22 scart1-cvbs_in rear-c_in
6 AI23 front-c_in front-c_in
7 AI31 scart2-g_in rear-y_in (YPbPr)
8 AI32 scart2-cvbs_in front-cvbs_in
9 AI33 scart2-tuner-dttm-cvbs_in tuner-cvbs_in
10 AI41 scart2-b_in rear-pb_in
11 AI42 leco-cvbs_in2 reserved
12 AI43 front-cvbs_in leco-cvbs_in

- Initialise IIC
- Read out the VIP id
- Write the set of registers required for the input specified
60400 Selecting the input of the VIP succeeded
60401 The user provided wrong input
60402 The VIP was not accessible
60403 An unsupported VIP was found
Example DS:> 604 1
060400:
Test OK @
Nucleus Name DS_VIP_Routing

Nucleus Number 605
Description Perform the routing of the audio and video signals in the set. It sets the audio
and video path according to the user input.
The user inputs the path id of choice, as specified in the table below for EURO
and NAFTA.
User Input <REGION> <PATH_ID>
For details see next tables
- Initialise IIC
- Read out the VIP id
- Write the set of registers required for the input specified
60500 Selecting the input of the VIP succeeded
60502 The VIP was not accessible
60503 An unsupported VIP was found
Example DS:> 605 euro 00
060500:
Test OK @
Available VIDEO path-lds for NAFTA / APAC routing

NAFTA Path id Description
nafta 00 cvbs, yc, yuv and audio rear out.
nafta 01 cvbs and iis loop through (via itu656_c).
nafta 02 cvbs and iis loop through (via itu656_d).
nafta 03 cvbs and audio front in,
cvbs and audio rear out.
nafta 04 yc and audio rear in,
yc and audio rear out.
nafta 05 yc and audio front in,
yc and audio rear out.
nafta 06 yuv and audio rear out,
yuv and audio rear in.
nafta 07 cvbs, yc, yuv and audio rear out,
tuner in.
nafta 08 spdif rear out,
spdif1 rear in.
nafta 09 spdif rear out,
spdif2 rear in.
nafta 10 cvbs, spdif rear out,
dttm itu656 spdif in..
nafta 11 cvbs and audio front in,
cvbs and audio rear out (via external audio ADC).
nafta 12 cvbs and iis loop through (via itu656_c and external audio
ADC).
nafta 13 yuv and audio rear out(via external audio ADC),
yuv and audio rear in.
Nucleus Name DS_VIP_Reset

Nucleus Number 606
Description Reset the Video input processor
Technical - Toggle the VIP_RESET PIO line of the codec
User Input None
60600 Resetting VIP succeeded
60601 Resetting VIP failed
Example DS:> 606
060600: Ok
Test OK @
Nucleus Name DS_VIP_FastBlankingCheck

Nucleus Number 607
Description Checks the fast blanking signal on SCART2 in
Technical - Read out the SCART1_P16 GPIO pin of the ASP
User Input None
60700 Value of Fast Blanking Pin is detected
60701 Error Cannot read Fast Blanking Pin
Example DS:> 607
060700: Fast Blanking is ON
Test OK @
Nucleus Name DS_VIP_WssCheck

Nucleus Number 608
Description Check if the wide screen signal can be set low and high.
Technical - Get the WSS Rear Y/C Out value
User Input None
60800
60801
Example DS:> 608

060800: WSS is ON
Test OK @
Nucleus Name DS_VIP_DetectVideo

Nucleus Number 609
Description Checks if an active video signal is available on the CVBS input of SCART 1 or
SCART 2.
Technical - Reset the VIP.
- Implement the following video route in the VIP : SCART1 (A32) to
ITU656_C
- Tell user to remove all active video input from SCART1.
- Enable sdtv(hlvln) mask in 0x500(First level interrupt enable) and 0x50d
(SDTV interrupt enable).
- Set GPIO 55 on ASP to input.
- Tell user to connect active video into SCART1.
- Read GPIO 55.
- The line should be LOW if there is active video on SCART1, else LOW.
- Clear the VIP *INTA interrupt.
Execution Time Depending on user input
User Input None
609000 Detecting the Active video succeeded.
609001 Detecting the Active video failed.
609002 This test is not applicable for current HW layout.
609003 Could not retrieve hardware version from ASP.
Example DS:> 609
Please remove video input from the SCART1 connector.
Press any key when ready ...
Please input video input into the SCART1 connector.
Press any key when ready ...
609000: Active video is ON
Test OK @
DIGITAL VIDEO INPUT OUTPUT CIRCUIT (DVIO)

Nucleus Name DS_DVIO_LinkDevTypeGet
Nucleus Number 700
Description Get the device (revision) type information of the 1394 Link layer IC
Technical - Initialise the PIO pins on the Codec
- Read out the ID register
User Input None
70000 Getting the information from the link layer IC succeeded
70001 Getting the information from the link layer IC failed
70002 Type not according to type stored in HW diversity string
Example DS:> 700
070000: Device type of the link layer IC: ffc00301
Test OK @
Nucleus Name DS_DVIO_PhyDevTypeGet

Nucleus Number 701
Description Get the device (revision) type information of the 1394 Physical layer IC
Technical - Initialise the PIO pins of the Codec
- Write the PHY-access register in the Link chip to indicate phy read access
- Wait until the link chip has obtained the value from the phy-chip
- Read this out and filter the data to be returned to the user
User Input None
70100 Getting the information from the physical layer IC succeeded
70101 The physical layer IC was not accessible
70102 Getting the information from the physical layer IC failed
70103 Type not according to type stored in HW diversity
Example DS:> 701
070100: Physical layer IC: VendorID: 0x006037, ProductID: 0x412801
Test OK @
Nucleus Name DS_DVIO_PhyCommunication

Nucleus Number 703
Description Check the accessibility of the 1394 Physical layer IC by writing to and reading
from a specific address
Technical - Initialise the PIO pins of the Codec
- Initialise IIC
- Write the data to be written to the PHY-chip to the link chip first
- Wait until the link chip indicates that the data has been written to the PHY
- Write the PHY-access register in the Link chip to indicate PHY read access
- Wait until the link chip has obtained the value from the PHY-chip
- Test whether the value read back equals the one previously written
User Input None
70300 Communicating with the physical layer IC succeeded
70301 The physical layer IC was not accessible
70302 Communicating with the physical layer IC failed
70303 Result of nucleus not according to HW diversity string
Example DS:> 703
070300:
Test OK @
Nucleus Name DS_DVIO_Routing

Nucleus Number 704
Description Route a DV stream containing an audio and video signal through the physical
and link layer ICs to the Codec. This test works for both NTSC and PAL.
Technical - Initialise the DMA to transfer 5 frames PAL/NTSC
- Initialise the DV de-multiplexer
- Initialise the 1394 interface and start reception of the DV stream
- Check whether the stream was copied to memory properly by the byte
input interface (port to memory type DMA)
Execution Time 6-10 seconds (6 when OK, 10 when no stream or error)
User Input None
70400 Routing the signals succeeded
70401 The 1394 link chip could not be initialised properly
70402 There was a syntax error in the DV stream
70403 DMA could not copy DV stream to memory. Stream connected?
70404 DMA not working properly
Example DS:> 704
070400:
Test OK @
Nucleus Name DS_DVIO_DetectNode

Nucleus Number 705
Description Check whether a DV node can be detected by the hardware. This test works for
both NTSC and PAL.
Technical - Initialise the 1394 interface
- Detect whether a node is in range
Execution Time 3 or 5 seconds (3 when OK, 5 when no stream or error)
User Input None
70500 The node was detected OK
70502 Unable to write to 1394 PHY chip
70503 Unable to read from 1394 PHY chip
70504 No node was detected
Example DS:> 705
070500:
Test OK @
Nucleus Name DS_DVIO_DetectStream

Nucleus Number 706
Description Check whether a DV stream can be detected by the hardware. This test works
for both NTSC and PAL.
Technical - Initialise the 1394 interface
- Start receiving the stream
- Detect whether the stream is OK
Execution Time 3 or 5 seconds (3 when OK, 5 when no stream or error)
User Input None
70600 The stream was detected
70602 No stream detected
Example DS:> 706
070600:
Test OK @
BASIC ENGINE (BE)

Nucleus Name DS_BE_CommunicationEcho
Nucleus Number 900
Description Check the communication between the digital board and the BE by issuing a
TEST_UNIT_READY ATAPI command
Technical - Send an ATAPI TEST_UNIT_READY command
User Input None
90000 Communicating with the BE over the IDE interface succeeded
90001 There was a time-out while communicating
90002 The Basic Engine returned an unexpected result
90003 The Basic Engine returned an error code
90004 No acknowledge received from BE
90005 Communicating with the Basic Engine failed
90006 Echo check failed, no ready status received
90007 Echo check failed, received wrong pattern
Example DS:> 900
090000:
Test OK @
Nucleus Name DS_BE_Reset

Nucleus Number 901
Description Reset the basic engine
Technical - Toggle the reset pin of the IDE interface and wait for the BE to become
ready
Execution Time 9 seconds (when disc inside)
User Input None
90100 Resetting the Basic Engine succeeded
90101 Resetting the Basic Engine failed
Example DS:> 901
090100:
Test OK @
Nucleus Name DS_BE_GetSelftestResult

Nucleus Number 902
Description Return the self-test results through the service port
Technical - Send the ATAPI REPORT_DRIVE_DIAGNOSTICS command
- On error display the specific error codes received from the BE
User Input None
90200 Self test succeeded, no errors
90203 The BE returned an error code
90206 Basic Engine returned no info
90207 Self test failed, errors are echoed
Example DS:> 902
090200:
Self-test result byte : 00000000
Test OK @
Nucleus Name DS_BE_VersionGet

Nucleus Number 903
Description Get the version of the basic engine and that of the optical unit
Technical - send the ATAPI INQUIRY command
- Send the GET_OPU_VERSION command
- Display the returned version information
User Input None
90300 BE version OK
90306 The BE returned no info
Example DS:> 903
090300:
BE version = 31.30.24. PHILIPS ,VAD8031
,31302400,REL_8031_313024 2073,
Optical unit version = 00.06.82.19.00
Test OK @
Nucleus Name DS_BE_TrayOut

Nucleus Number 904
Description Open the tray of the basic engine
Technical - Send an ATAPI START_STOP_UNIT command
Execution Time Approximately 2 seconds
User Input None
90400 The command executed successfully
90405 Unable to enter normal mode
Example DS:> 904
090400:
Test OK @
Nucleus Name DS_BE_TrayIn

Nucleus Number 905
Description Close the tray of the basic engine
Technical - Send an ATAPI START_STOP_UNIT command
Execution Time Approximately 1 - 2 seconds
User Input None
90505 Unable to enter normal mode
Example DS:> 905
090500:
Test OK @
Nucleus Name DS_BE_WriteReadDvdRw

Nucleus Number 906
Description Write data to and read data from a DVD+RW or DVD-RW disc through the
basic engine for verification of the writing
Technical - Send an ATAPI START_STOP_UNIT command to insert the tray
- Send the READ_TOC command
- Generate a random disc location
- Generate test data to write to the DVD+RW
- Transfer the test data to the disc location using PIO mode ATAPI
WRITE_10
- Transfer the test data from the disc location using PIO mode ATAPI
READ_10
- Compare the two data areas and check whether the areas are equal
User Input None
90601 This nucleus cannot be executed because the Self-Test failed
90602 The BE cannot enter normal operating mode
90603 Unable to send the tray in
90604 Unable to read TOC from disc
Invalid disc is loaded, please insert a DVD+RW or DVD-RW
90605 disc
90606 Writing the test pattern to DVD+RW or DVD-RW failed
90607 Reading back the test pattern from DVD+RW of DVD-RW failed
90608 Compare check failed
90609 Calibrating DVD+RW or DVD-RW failed
Example DS:> 906
090600: DVD+RW test on sector 0x5dbe0: OK
Test OK @
DS:> 906
090600: DVD-RW test on sector 0x304e0: OK
Test OK @
Nucleus Name DS_BE_WriteReadDvdR

Nucleus Number 907
Description Write data to and read data from a DVD+R or DVD-R disc through the basic
engine for verification of the writing
Technical - Send an ATAPI START_STOP_UNIT command to insert the tray
- Use the OPC area to test if the DVD+R or DVD-R is (still) writable
- Generate test data to write to the DVD+R or DVD-R
- Transfer the test data to the disc location using PIO mode ATAPI
WRITE_10
- Transfer the test data from the disc location using PIO mode ATAPI
READ_10
User Input None
90705 Invalid disc is loaded, please insert a DVD+RW disc
90706 Unable to write, the DVD+R or DVD-R disc is full
90707 No writable DVD+R or DVD-R sector found
90708 Writing the test pattern to DVD failed
90709 Reading back the test pattern from DVD failed
90710 Compare check failed
Example DS:> 907
090700: DVD+R test on sector 0x36210: OK
Test OK @
DS:> 907
090700: DVD-R test on sector 0x30000: OK
Test OK @
Nucleus Name DS_BE_JitterOptimise

Nucleus Number 912
Description Perform jitter optimisation:
A formatted DVD must be loaded into the engine before executing this nucleus
Technical - Send the START_STOP_UNIT command to insert the tray
- Send the MEASURE_JITTER_BLER_PPN command and display the
average jitter and bler values
User Input None
91200 Optimising jitter succeeded
91203 The Basic Engine returned an error code
91205 Unable to send tray in
91206 Unable to read the disc
91207 No disc is loaded
91208 Unknown disc is loaded
91209 Unable to enter service mode
Example DS:> 912
091200: Average Jitter, Bler C1, Bler C2: (92,4,254)
Test OK @
Nucleus Name DS_BE_FocusOn

Nucleus Number 913
Description Put the laser of the bit-engine into focus by issuing a TRANSPARENT SEND
and TRANSPARENT_RECEIVE command. This nucleus is not guaranteed to
work on all connected BEs
Technical - Send the transparent BIT engine FOCUS command
Important note: This nucleus uses the transparent bit engine interface of the drive. It is
not guaranteed to work on all drives. Only use this nucleus if you are sure
that the drive supports this interface
User Input None
91300 Focus on succeeded
Example DS:> 913
091300:
Test OK @
Nucleus Name DS_BE_FocusOff

Nucleus Number 914
Description Turn off putting the laser of the bit-engine into focus by issuing a
TRANSPARENT SEND and TRANSPARENT_RECEIVE command. This
nucleus is not guaranteed to work on all connected BEs
Technical - Send the transparent BIT engine FOCUS command
User Input None
91400 Focus off succeeded
Example DS:> 914
091400:
Test OK @
Nucleus Name DS_BE_MotorOn

Nucleus Number 915
Description Turn on the turntable motor by issuing a TRANSPARENT SEND and
TRANSPARENT_RECEIVE command. This nucleus is not guaranteed to work
on all connected Bes
Technical - Send the transparent BIT engine TTM command
User Input None
91500 Turn table motor is on
Example DS:> 915
091500:
Test OK @
Nucleus Name DS_BE_MotorOff

Nucleus Number 916
Description Turn off the turntable motor by issuing a TRANSPARENT SEND and
TRANSPARENT_RECEIVE command. This nucleus is not guaranteed to work
on all connected Bes
Technical - Send the transparent BIT engine TTM command
User Input None
91600 Turn table motor is off
Example DS:> 916
091600:
Test OK @
Nucleus Name DS_BE_CheckDisc

Nucleus Number 921
Description Check whether there is a disc inside the BE
- Display the Disc type info
- If Disc type is a DVD+R(W), then read ADIP info.
- Display manufacturer and media type.
User Input None
92100 There was a disc inside the set
92101 Unable to load the tray
92102 Error received from BE
Example DS:> 921
092100:
Disc type: DVD+RW disc
Disc manufacturer id: PHILIPS
Media type id: 010
Test OK @
DS:> 921
090500:
Disc type: None
Test OK @
DS:> 921
092100:
Disc type: DVD+R disc
Disc manufacturer id: RICOHJPN
Media type id: R00
Test OK @
Nucleus Name DS_BE_ReadTocInfo

Nucleus Number 924
Description Read the TOC from the disc. This gives a good indication if the BE works
properly.
- Display the TOC info.
User Input None
92400 A disc is loaded, TOC info if echoed
92401 Unable to load the tray
92402 The BE has not returned TOC info
92403 Error received from BE
Example DS:> 924
092400: TOC info [hex] = 91 3A 0C
Test OK @
DS:> 924
092403: The BE returned: 0x10 #{no_disc_error} No disc is detected
Error @
DS:> 924
092403: The BE returned: 0x1e #{illegal_medium_error} Engine
unable to handle current disc. Probably illegal medium.
Error @
Nucleus Name DS_BE_RegionCodeSet

Nucleus Number 928
Description Set the region code in the AV3.
Technical - Send the ATAPI SEND_KEY command
Execution Time
User Input Region code
92806 No disc is present, please insert disc
92807 Region code out of range
92808 User input wrong
92809 Region counter expired
92810 This nucleus is not supported by the engine
Example DS:> 928 1
092800:
Test OK @
Nucleus Name DS_BE_RegionCodeGet

Nucleus Number 929
Description Read the region code from the AV3.
Technical - Send the ATAPI REPORT_KEY command
Execution Time
User Input None
Example DS:> 929
092900: DVD region 1
Test OK @
Nucleus Name DS_BE_RegionCounterReset

Nucleus Number 930
Description Reset the region counter in the AV3.
Technical - Send a special ATAPI RESET_REGION_COUNTER command
Execution Time
User Input None
Example DS:> 930
093000:
Test OK @
Nucleus Name DS_BE_AdjustLaserControl

Nucleus Number 931
Description Adjust the DVD-M (with the OPU) with PCBA. (So adjusts the two PCBS to
each other)
Technical - Sending a transparent BIT engine command to align the PCBs to each
other.
User Input None
Example DS:> 931
093100:
Test OK @
Nucleus Name DS_BE_WriteReadDvdRDualLayer

Nucleus Number 932
Description Write data to and read data from both layers of a DVD+R DL disc through the
basic engine for verification of the writing
Technical - Send the TRAY_IN command
- Use READ_TRACK_INFORMATION to determine the next free writable
address on Layer 0.
- In case of address 0, reserve a track of 0x1FD800 sectors for Layer 0
- Use command SEND_OPC_INFORMATION to calibrate Layer 0
- Generate test data to write to the disc
- Transfer the test data to Layer 0 using PIO mode ATAPI WRITE_12
- Use READ_TRACK_INFORMATION to determine the next free writable
address on Layer 1
- Use command SEND_OPC_INFORMATION to calibrate Layer 1
- Transfer the test data to Layer 1 using PIO mode ATAPI WRITE_12
- Read back the data of Layer 0 using PIO mode ATAPI READ_12
- Compare the original data with the read data and check whether the areas
are equal
- Read back the data of Layer 1 using PIO mode ATAPI READ_12
- Compare the original data with the read data and check whether the areas
are equal
User Input None
93205 Invalid disc is loaded, please insert a DVD+R DL disc
93206 Unable to write, the DVD+R DL disc is full
93207 No writable sector found
93208 Writing the test pattern to Layer 0 failed
93209 Writing the test pattern to Layer 1 failed
93210 Reading back the test pattern from Layer 0 failed
93211 Reading back the test pattern from Layer 1 failed
93212 Compare check for Layer 0 failed
93213 Compare check for Layer 1 failed
Example DS:> 932
093200: Dual Layer DVD+R test on LBA 0x750 and 0x1fdf60 OK
Test OK @
Nucleus Name DS_SYS_HardwareVersionGet

Nucleus Number 1200
Description Get the hardware version and type of the digital board
Technical - Read the segment header in FLASH and determine hardware version
User Input None
120000 Getting the hardware version and type of the digital board
succeeded
120001 Getting the hardware version and type of the digital board failed
120002 Wrong hardware version read from FLASH
Example DS:> 1200
120000: Hardware ID = 0x29
Test OK @
Nucleus Name DS_SYS_SoftwareVersionBootGet

Nucleus Number 1201
Description Get the version of the boot software on the digital board
Technical - Read the segment header in FLASH and determine Boot software version
User Input None
120100 Getting the Boot software version succeeded
120101 Getting the Boot software version failed
Example DS:> 1201
120100: Software Boot Version = 0331
Test OK @
Nucleus Name DS_SYS_SoftwareVersionDownloadGet

Nucleus Number 1202
Description Get the version of the download software on the digital board
Technical - Read the segment header in FLASH and determine Download software
version
User Input None
120200 Getting the Download software version succeeded
120201 Getting the Download software version failed
Example DS:> 1202
120200: Software Download Version = 0001
Test OK @
Nucleus Name DS_SYS_SoftwareVersionApplGet

Nucleus Number 1203
Description Get the version of the application software on the digital board
Technical - Read the segment header in FLASH and determine Application software
version
User Input None
120300 Getting the Application software version succeeded
120301 Getting the Application software version failed
Example DS:> 1203
120300: Software Application Version = 0001
Test OK @
Nucleus Name DS_SYS_SoftwareVersionDiagnosticsGet

Nucleus Number 1204
Description Get the version of the diagnostics software on the digital board
Technical - Read the segment header in FLASH and determine Diagnostics software
version
User Input None
120400 Getting the Diagnostics software version succeeded
120401 Getting the Diagnostics software version failed
Example DS:> 1204
120400: Software Diagnostics Version = 0001
Test OK @
Nucleus Name DS_SYS_DvIdNumberSet

Nucleus Number 1207
Description Set the IEEE 1394 unique ID
Technical - Decode the user input
- Store the id (<b4><b3><b2><b1><b0>) into NVRAM (offset +
<b4><b3><b2><b1><b0>)
- Validate the segment of storage by updating the checksum
User Input The unique ID to be set.
120700 Setting the unique DV ID succeeded
120701 User input is not valid.
120702 Setting the unique DV ID failed.
120703 Write succeeded, but checksum is corrupt.
Example DS:> 1207 1234567890
120700:
Test OK @
Nucleus Name DS_SYS_DvIdNumberGet

Nucleus Number 1208
Description Get the IEEE1394 unique ID
Technical - Read out the ID from the configuration segment and return this info to the
user
User Input None
120800 Getting the unique DV ID succeeded
120801 Getting the unique DV ID failed
120802 Reading an unexpected section version in NVRAM
Example DS:> 1208
120800: The DvIdNumber is: 1234567890
Test OK @
Nucleus Name DS_SYS_IicWrite

Nucleus Number 1209
Description Perform an IIC write action on the digital board
Technical - Determine bus ID, slave address, number of bytes to be written and the
byte array of data from the user input
- Initialise IIC
- Write the data to the slave specified through IIC
User Input The user input the number of bytes to write followed by the bytes to write:
<BusID><Slave address to write to><number of bytes to
write><d1><d2><..><dx>
Where the bus id is either 0 (normally used) or 1
120900 Writing the data over IIC succeeded
120902 There was a timeout writing to the device
120905 Got unknown IIC bus error:
120906 Unable to initialise IIC bus
120907 Decoding bus ID unsigned value failed
120908 Decoding slaveAddr unsigned value failed
120909 Decoding nrBytes unsigned value failed
120910 Bus ID out of range
120911 nrBytes out of range
120912 Unable to decode parameters
Example DS:> 1209 0 0xa0 1 0x6
120900: 1 Bytes written
Test OK @
Nucleus Name DS_SYS_IicRead

Nucleus Number 1210
Description Perform an IIC read action on the digital board
Technical - Determine the bus ID, slave address and number of bytes to read from the
user input
- Initialise IIC
- Read the data form the slave specified
User Input The user inputs the bus number, the address to read them from and the
number of bytes to read:
<BusID><Slave address to read from><Number of bytes to read>
Where the bus id is either 0 (normally used) or 1
121000 Reading the data over IIC succeeded
121002 There was a timeout writing to the device
121005 There was an unknown IIC bus error
121006 IIC bus initialisation failed
121008 Decoding slave address unsigned value failed
121009 Decoding number of bytes unsigned value failed
121011 nrBytes out of range
Example DS:> 1210 0 0xa0 0x20
Read :
0x0000: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x0008: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x0010: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x0018: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
121000: 0 0xa0 0x20

Test OK @
Nucleus Name DS_SYS_UartWrite

Nucleus Number 1211
Description Perform an UART write action on the digital board on a specified UART
Technical - Decode the user input for the proper port to use
- Write out the bytes through the indicated port
User Input The user inputs the UART to write to, the number of bytes and the bytes to be
written to the UART.
1=UART port 1 : not used
2=UART port 2 : Bit Engine
3=UART port 3 : Analogue board
<UartNr><Number of bytes to write><d1><d2><..><dx>

121100 Writing the bytes to the UART succeeded
121102 Writing to the UART failed
Example DS:> 1211 2 2 0xd1 0x01
121100:
Test OK @
Nucleus Name DS_SYS_UartRead

Nucleus Number 1212
Description Perform an UART read action on the digital board on a specified UART
Technical - Decode the user input for the port to read from
- Read from the port and return data read to the user
User Input The user inputs the UART to read from.
1=UART port 1 : not used
2=UART port 2 : Bit Engine
<UartNr >
121200 Reading the data from the UART succeeded
121202 Reading the data from the UART failed
Example DS:> 1212 2
121200: The HEX value that was read is: 0x50 0xD1 0x00
Test OK @
Nucleus Name DS_SYS_VideoLoopThroughStart

Nucleus Number 1213
Description The video signal, which is conform the user input, is routed from the input to the
output. The input is set using the proper nucleus to route the signal on the
board(s). All outputs are enabled.
Note: Before executing this nucleus the user must route the video signal on the
VIP using DS_VIP_Routing
Technical - Decode the videosignal: PAL / NTSC and Y/C, RGB, CVBS,YUV
- Initialise the Video Input Processor and check for valid signal
- Initialise the Video Front End and start capturing frames to memory
- Initialise the SYNC module
- Initialise the Video Post Processing and retrieve frames from memory
- Initialise the mixer
- Initialise the DENC module
- Route the signal to all outputs
Execution Time Less than 1 second, but stays running.
Note: First set the correct video route using
User Input <VideoSignal> <VideoStandard>
1. Video Signal (CVBS,YC,RGB,YUV).
2. VideoStandard (PAL, NTSC).
121300 Video LoopthroughStart succeeded
121301 User input is not valid.
121302 Initialisation of the VIP failed.
121303 Unable to stop the loop through before restarting.
121304 Video Signal on the input is not a valid signal.
121305 Initialisation of the VFE failed.
Example DS:> 1213 rgb pal
121300:
Test OK @
Nucleus Name DS_SYS_VideoLoopThroughStop

Nucleus Number 1214
Description Stop routing the video input to all the outputs.
Technical - Stop the DENC and the Video Front End
User Input None
121400 VideoLoopthroughStop succeeded
121401 DENC module on Codec failed.
Example DS:> 1214
121400:
Test OK @
Nucleus Name DS_SYS_VideoLoop

Nucleus Number 1215
Description The Codec generates a video signal with a specific signature and sends it to
the output of the digital board. The user selects which video input path must be
routed on the digital board and a video standard. The Codec encodes the video
signal, checks the signature, and returns a conclusion.
Note: Before executing this nucleus the user must route the video signal on the
VIP using DS_VIP_Routing.
Technical - Evaluate user input.
- Reset the global variables, video memory.
- Fill the video memory with a vertical colourbar.
- Initialise the Codec SYNC-module.
- Initialise the Codec MIXER-module.
- Initialise the Codec VPP-module.
- Initialise the Codec DENC-module.
- Display the original image.
- Initialise the VIP.
- Initialise the Codec VFE-module.
- Try to detect a sync in the VIP input.
- Catch the received image in memory.
- Display the received image.
- Compare the received image with original image.
- Create a conclusion.
User Input <VideoSignal> <VideoStandard>
1. Video Signal (CVBS,YC,RGB,YUV,DTT).
2. VideoStandard (PAL, NTSC).
121500 Videoloop test succeeded.
121501 Wrong user input.
121502 The Codec SYNC-module cannot be initialised.
121503 The Codec MIXER-module cannot be initialised.
121504 The Codec VideoPostProcessor-module cannot be initialised.
121505 The Codec DENC-module cannot be initialised.
121506 The VideoInputProcessor cannot be initialised.
121507 The VideoInputProcessor cannot detect a sync-signal.
121508 The Codec VideoFrontEnd-module cannot be initialised.
121509 The Codec VideoFrontEnd-module cannot capture a video
field.
121510 When selected the RGB video input:
Error in colour red signal and/or
Error in colour green signal and/or
Error in colour blue signal.
When selected one of the other video inputs:
Error in luminance signal (Y) and/or
Error in chrominance signal (U) and/or
Error in chrominance signal (V).
Example DS:> 1215 cvbs ntsc
121500:
Test OK @
DS:> 1215 cvbs pal

121508: The VideoInputProcessor cannot detect a sync-signal.
Error @
DS:> 1215 yuv ntsc

121511:
Error in luminance signal(Y)
Error in chrominance signal(U)
Error in chrominance signal(V)
Error @
Nucleus Name DS_SYS_AudioLoop

Nucleus Number 1216
Description In this nucleus the Codec generates an audio sine signal with a specific
signature and sends it to the output of the digital board. The Codec encodes
the audio signal to MPEG I layer II and after this the signature of the signal will
be checked.
Note: Before executing this nucleus the user must route the audio signal on
the VIP using DS_VIP_Routing.
Technical - The user needs to route the signal to the audio inputs so the test can
encode the audio to MPEG I layer II
- An audio signal is generated, resulting in a sine of 6kHz on the left and
12kHz on the right channel.
- Then the signal is decoded in memory.
- When both signals are detected correctly in the MPEG, the test succeeded.
User Input InputType:
- I2S (default, when no user input is given)
- SPDIF: This input needs a second parameter:
- OPT (optical, default, when no user input is given)
- COAX
121600 Testing the components on the audio signal path succeeded
121601 The audio encoder did not initialise.
121602 No audio could be generated.
121603 The audio encoder did not encode audio.
121604 The audio could not be decoded.
121605 Frequency on left channel out of range.
121606 Frequency on right channel out of range.
121607 The frequencies on both channels are out of range.
121608 Frequency on left channel out of range. Right channel silent.
121609 Right channel is silent.
121610 Frequency on right channel out of range. Left channel silent.
121611 Left channel is silent.
121612 Both channels are silent.
Example DS:> 1216
121600:
Test OK @
DS:> 1216 spdif coax

121600:
Test OK @
DS:> 1216 spdif opt

121600:
Test OK @
Nucleus Name DS_SYS_SlashVersionSet

Nucleus Number 1217
Description Set the slash version of the system
Technical - Decode the user input for the slash version to set
- Issue the command to set the slash version to the analogue board
User Input The slash version
121700 Setting the slash version succeeded
121701 Invalid slash version, no slash version is set.
121702 Setting the slash version on the Analogue Board fails.
121703 Invalid input.
121704 The returned error code from the analogue board is unknown:
121705 No DS error code known for analogue board error:
121706 There was no response from the analogue board.
121707 Retrieving the current version failed
121708 Unknown recorder layout type
121709 Validating the section where the version is stored failed
121710 Getting the configuration section from NVRAM failed
121711 Initialisation of IIC or reaching NVRAM failed
Example DS:> 1217 82
121700:
Test OK @
Nucleus Name DS_SYS_SlashVersionGet

Nucleus Number 1218
Description Get the slash version of the system
Technical - Issue the command to get the slash version to the analogue board
- Return the received information to the user
User Input None
121800 Getting the slash version succeeded
121801 Getting the slash version failed
121802 The IIC write failed
121803 The IIC read failed
121806 Reading the slash version failed
121808 Reading an unexpected section version in NVRAM
Example DS:> 1218
121800: The slash version is: 82
Test OK @
Nucleus Name DS_SYS_VirginModeOn

Nucleus Number 1220
Description Turn on the virgin mode functionality (e.g. the auto channel search upon start-
up)
Technical - Issue the command to set the bit for the virgin mode to the analogue board
User Input None
122000 Turning on the virgin mode succeeded
122001 Turning on VirginMode on the Analogue Board failed.
122005 Section validation or write failed in NVRAM
122006 Reading the CONFIG section from NVRAM failed
Example DS:> 1220
122000:
Test OK @
Nucleus Name DS_SYS_VirginModeOff

Nucleus Number 1221
Description Turn off the virgin mode functionality (e.g. the auto channel search upon start-
up)
Technical - Issue the command to reset the bit for the virgin mode to the analogue
board
User Input None
122100 Turning off the virgin mode succeeded
122101 Turning off VirginMode on the Analogue Board failed.
122106 Reading the CONFIG section from NVRAM failed
Example DS:> 1221
122100:
Test OK @
Nucleus Name DS_SYS_VirginModeGet

Nucleus Number 1222
Description Get the virgin mode functionality status (e.g. the auto channel search upon
start-up)
Technical - Issue the command to reset the bit for the virgin mode to the analogue
board
User Input None
122200 Getting the virgin mode succeeded
122201 Reading the Virgin Mode flag from NVRAM failed
122202 Initialisation of IIC or reaching the NVRAM failed
122203 Reading an unexpected version of the section in NVRAM
Example DS:> 1222
122200: The Virgin Mode functionality is: ON
Test OK @
Nucleus Name DS_SYS_DisplayFatalOn

Nucleus Number 1223
Description Turn on the display-fatal functionality which displays debug-information on the
display when encountering a fatal error condition from which could not be
recovered automatically
Technical - Issue the command to use the display-fatal functionality to the analogue
board
User Input None
122300 Turning on the display-fatal functionality succeeded
122301 Turning on the display-fatal functionality failed
122306 Reading the section from NVRAM failed
Example DS:> 1223
122300:
Test OK @
Nucleus Name DS_SYS_DisplayFatalOff

Nucleus Number 1224
Description Turn off the display-fatal functionality which displays debug-information on the
display when encountering a fatal error condition from which could not be
recovered automatically
Technical - Issue the command to stop using the display-fatal functionality to the
analogue board
User Input None
122400 Turning off the display-fatal functionality succeeded
122401 Turning off the display-fatal functionality failed
122402 The returned errorcode from the analogue board is unknown:
122403 No DS errCode known for analogue board error:
122406 Reading the section from NVRAM failed
Example DS:> 1224
122400:
Test OK @
Nucleus Name DS_SYS_DisplayFatalGet

Nucleus Number 1225
Description Get the display-fatal flag of the recorder
Technical - Issue the command to get the status of the display-fatal functionality to the
analogue board
User Input None
122500 Getting the display-fatal flag succeeded
122501 Getting the display-fatal flag failed
122502 The returned errorcode from the analogue board is unknown:
122503 No DS errCode known for analogue board error:
122505 Reading the display fatal flag failed
122507 Unexpected version read from NVRAM section
122508 Reading the fatal flag from NVRAM failed
Example DS:> 1225
122500: The Display Fatal functionality is ON
Test OK @
Nucleus Name DS_SYS_SettingsSet

Nucleus Number 1226
Description Programs the digital board settings into the boot EEPROM on the digital board.
Technical - Evaluate user input.
- Set-up IIC-bus.
- Write data to boot EEPROM.
- Update checksum.
Execution Time 1 second
User Input A large hexadecimal value that represents the digital board hardware
information string
122600 The settings were successfully programmed.
122601 User input is invalid.
122602 IIC access failed.
Example DS:>1226 44424849716040014C45434F2B0000006020070000010200000101008
008000044564452323030312E30303102020000000103000000020100000000000
00000
122600:
Test OK @
Nucleus Name DS_SYS_SettingsDisplay

Nucleus Number 1228
Description Show the settings that are programmed in the BROM on the digital board.
Technical - Set-up IIC-bus.
- Read Digital Board Settings from boot EEPROM.
- Display the settings.
User Input None.
122800 The settings were successfully displayed.
122802 Invalid settings
Example DS:> 1228
Investigating the system, please wait...
DBHI-string :
44424849716040014C45434F2B0000006020070000010200000101008008000044
56445232303031
2E3030310202000000010300000002010000000000000000
Boardname : LECO+
Hardware ID : 60
Download Table Filename : DVDR2001.001
RAM type : DDRAM
RAM size [MB] : 128
ROM bank 1 type : NOR
ROM bank 1 size [MB] : 8
ROM bank 2 type : none
ROM bank 2 size [MB] : 0
EEPROM I2C-bus0 size [KB] : 0
EEPROM I2C-bus1 size [KB] : 0
Codec id : PNX7350
VIP id : SAA7136
Progressive scan id : codec internal
Dvio physical layer id : PDI1394P25
Dvio link layer id : PDI1394L41
USB id : Internal
Connector S2B : not available
Connector IDE1 : available
Connector IDE2 : available
Connector PCI : not available
Connector AVI : not available
Connector HDMI : not available
Connector DVB-T : not available
Interface analog board : IIC-bus
Audio output : stereo
Audio clock scheme : none
YUV matrix : not available
Bit Engine drive : D 4.3
122800:
Test OK @
Nucleus Name DS_SYS_SettingsGet

Nucleus Number 1229
Description Get the digital board diversity settings string that is programmed in the BROM
on the digital board.
Technical - Set-up IIC-bus.
- Read Digital Board Settings from boot EEPROM.
- Read System Settings from boot EEPROM.
- Display the settings.
User Input None.
122900 The settings were successfully displayed.
122902 The settings are invalid
Example DS:> 1229
122900:
44424849716040014C45434F2B0000006020070000010200000101008008000044
564452
323030312E3030310202000000010300000002010000000000000000
Test OK @
Nucleus Name DS_SYS_AudioLoopThroughStart

Nucleus Number 1230
Description Description: The audio input is routed from the input to all outputs. The input is
set routing the signal with the proper nucleus. All outputs are enabled.
Technical - Encode the audio to AC3 in memory
- Decode the AC3 in memory to audio on the outputs
Execution Time 1second buffer time and 30 seconds playing.
User Input InputType:
- I2S (default)
- SPDIF (Only for recorders with 5.1 input and DTT module)
InputPort: (Only for recorders with 5.1 input. For DTT modules no parameter
should be filled in, so default is chosen )
- OPT : Optical input path is selected (default)
- COAX : Coax input path is selected
123000 AudioLoopthroughStart succeeded
123001 Resetting the audio decoder failed
123002 Resetting the audio encoder failed
123003 Encoding the audio failed
123004 Decoding the audio failed
Example DS:> 1230
123000:
Test OK @
Example DTT DS:> 1230 spdif
123000:
Test OK @
Example 5.1 input DS:> 1230 spdif coax
123000:
Test OK @
Nucleus Name DS_SYS_AudioLoopThroughStop

Nucleus Number 1231
Description Stop routing the audio input to all the outputs
Technical - Send the ‘Mute’ command to the audio decoder and reset the audio
decoder
User Input None.
123100 AudioLoopthroughStop succeeded
123101 Resetting the audio decoder failed
123102 Resetting the audio encoder failed
Example DS:> 1231
123100:
Test OK @
Nucleus Name DS_SYS_SettingsHwIdSet

Nucleus Number 1232
Description This nucleus sets the HW-Id in the HW-diversity string
Technical - Read out the HW-diversity string
- Modify the HW-ID in that string as requested
- Write the modified HW-diversity string to the EEPROM
User Input - <HW-ID> - The hardware ID to set
- No input - The user will be asked for the ID
123200 Setting the hardware ID succeeded
123201 Setting the hardware ID failed
123202 The user aborted setting the hardware ID, no changes made
Example DS:> 1232
Enter the new HW ID of the digital board (Currently equals 21)
Enter a value between 0 and 99:
> 22
The HW ID will be set to: 22. Is that correct? ([Y/N]):y
123200:
Test OK @
DS:> 1232
Enter the new HW ID of the digital board (Currently equals 22)
Enter a value between 0 and 99:
>
The HW ID will be set to: 0. Is that correct? ([Y/N]):N
123202: Setting the HW ID was aborted by the user.
Error @
DS:> 1232 99
123200:
Test OK @
Nucleus Name DS_SYS_SettingsDoubleCheck

Nucleus Number 1233
Description Double check whether stored HW-string equals actual HW as far
as we can automatically detect this. An automatic and a manual mode is
supported.
Technical - Read out the HW diversity string
- Check whether these settings correspond the actual hardware
- In case of modification: Write back the new HW-diversity settings.
Execution Time 4 seconds in auto mode when everything matches
User Input - ‘manual’ or ‘MANUAL’ to enter manual mode
- default is automatic mode where the nucleus stops upon and reports the
first encountered error
123300 Double checking the HW-diversity settings succeeded
123301 Double check failed, a difference in settings was encountered
123302 Reading the HW-diversity settings failed
123303 Writing the modified HW-diversity settings failed
Example DS:> 1233
123300:
Test OK @
DS:> 1233 manual

123300:
Test OK @
DS:> 1233
123301:
Hardware ID mismatch: in HW-Diversity string:99, actual in FLASH:0
Error @
DS:> 1233 manual

Hardware ID mismatch! in HW-Diversity string:99, actual in FLASH:0
Enter the correct HW ID of the digital board.

> 0
The HW-diversity string has been modified by you. Settings:
Board name: DIAG

Hardware ID: 0
Codec IC: PNX7100_MF3
Video Input Processor IC: SAA7118
Progressive Scan Deinterlacer IC: None
Progressive Scan Denc IC: ADV7196
I-Link physical layer circuit IC: PDI1394P25
I-Link link layer circuit IC: PDI1394P40
Audio clock: Clock scheme 1
Bit engine connector: available
IDE connector 1: available
IDE connector 2: not available
PCI connector: not available
RAM size 32MByte
ROM size (NOR FLASH bank 1) 8MByte
ROM size (NOR FLASH bank 2) Not available
ROM size (NAND FLASH) Not available
Is it OK to program this in
the new HW-diversity string? ([y]es/[n]o):y
Diversity HW-string programmed successfully.
123300:
Test OK @
DS:>
Nucleus Name DS_SYS_SettingsDlTableFilenameSet

Nucleus Number 1234
Description This nucleus sets the Download table filename in the HW-diversity string
Technical - Retrieve the new filename from the user
- Ask the user whether the filename is correct before setting it
- Update the diversity settings to use the newly entered filename
Execution Time Dependent on the user confirmation
User Input - The filename to be set
- No input - No new filename will be set
123400 Setting the new filename succeeded
123401 Unsupported setting of the current HW-diversity settings
123402 Setting the filename was aborted by the user.
Example DS:> 1234
Enter the new Download Table Filename (Currently equals
DVDR2001.001)
Enter a filename:
>
The Download Table Filename will be set to: DVDR2001.001. Is that
correct? ([Y/N]):
123402: Setting the filename was aborted by the user.
Error @
DS:> 1234
Enter the new Download Table Filename (Currently equals
DVDR2001.001)
Enter a filename:
>DVDR2002.001
The Download Table Filename will be set to: DVDR2002.001. Is that
correct? ([Y/N]):Y
123400:
Test OK @
Nucleus Name DS_SYS_IicWriteRead

Nucleus Number 1235
Description Perform an IIC write-read action on the digital board
Technical - Determine bus ID, slave address, number of bytes to be written and the
byte array of data from the user input
- Initialise IIC
- Write the data to the IIC slave
- Read the data from the IIC slave
User Input The user inputs the Bus ID, Slave Address, number of bytes to read,
number of bytes to write and the bytes to be written
<NucNr><BusId><SlaveAddr><ReadLen><WriteLen><WrByte0...WrByteN>
Max number of bytes to write: 255
Max number of bytes to read: 255
123500 Writing data to and reading data from the IIC slave succeeded
123502 There was a bus timeout reading the device
123506 Unknown IIC bus error received
123511 Number of bytes out of range
Example DS:> 1235 0 0xa0 0xf 1 0
0x0000: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
0x0008: 0x00 0x00 0x00 0x00 0x00 0x00 0x00
123500:
Test OK @
Nucleus Name DS_SYS_BuildInfoGet

Nucleus Number 1236
Description Retrieve the software build information of the Diagnostics & Service application
Technical - Show the information that is stored in the DVDR_BuildInfoType structure
User Input None
123600 Retrieving build info succeeded
123601 Retrieving build info failed
Example DS:> 1236
123600:
Version :1091
Build :20050823_0630
Release :SG1_1
Buildtype :dev
Baseline :SGP29atl#SG1_1_20050609_base
Variant :genlecoplus
Test OK @
Nucleus Name DS_SYS_UartSetup

Nucleus Number 1237
Description Set up a configuration for the selected UART
Technical - Parse user input
- Use MIS_UART_Setup to setup the selected UART with the requested
parameters
User Input The user inputs 6 parameters:
<UartNr><baudrate><flowcontrol><databits><parity><stopbits>
UartNr:
1=UART port 1 : not used (Chrysalis only)
2=UART port 2 : Bit Engine or DTTM (Chrysalis only)
baudrate:
115200,62500,57600,38400,19200,9600,4800,2400,1200
flowcontrol:
0=disabled 1=enabled
databits:
7 or 8
parity:
“NO”, “ODD” or “EVEN”
stopbits:
1 or 2
123700 Setting up the selected UART succeeded
123701 User provided Invalid setup parameters
123702 Setting up the selected UART Failed
123703 Selected UART is not available
Example (Chrysalis) DS:> 1237 2 38400 0 8 NO 1
123700:
Test OK @
Example (Leco) DS:> 1237 2 38400 0 8 NO 1
123703: The selected UART is not available
Error @
Nucleus Name DS_SYS_LowPowerStandby

Nucleus Number 1239
Description Send wakeup reason to ASP and set the set to low power standby.
Technical - Set up ASP
- Send wakeup reason to ASP
- Send low power standby command to ASP
Execution Time Vary (Maximum time will depend on the relative timer used)
User Input - wakeup reason - the wakeup reason for the DB to power up
- timer - relative timing for the DB to power up if wakeup reason 1 or 3 is
chosen
123901 Invalid data was given by the user
123902 Failed to communication to ASP
Example DS:> 1239
Wakeup reason from Low Power Standby

1) timer only
2) local key or RC pressed only
3) any reason
or press 'a' to abort
1
Enter time to wake up from low power standby.
Range 1 - 5 mins:
1
Entering low power standby
Nucleus Name DS_SYS_DivxModelIdSet

Nucleus Number 1240
Description Sets the Divx Model Id in NVRAM.
Technical - Initialize the NVM interface.
- Read the NVRAM CONFIG section into RAM
- Store the Divx model id into the CONFIG section in RAM
- Validate the CONFIG section in RAM
- Write the CONFIG section in RAM back into the non-volatile storage.
Execution Time Less than 2 seconds
User Input - 16-bit word containing the 12-bit Divx model Id.
- For example :
o 0x3031 (means Low Byte : 0x30 and High Byte 0x31)
124001 Validate CONFIG section failed
124002 Cannot read CONFIG section
124003 Invalid user parameters
124004 Error initializing NVRAM interfaces
Example DS:> 1240 0x3031
124000:
Test OK @
Nucleus Name DS_SYS_DivxModelIdGet

Nucleus Number 1241
Description Retrieves the Divx Model Id from NVRAM.
Technical - Read the CONFIG section from NVRAM
- Check the header information of the CONFIG section to ensure that it is
Version 4
- If Version 4 is detected, proceed to read and display the High Byte and
Low byte of the Divx Model Id.
Execution Time Less than 2 seconds
User Input None.
124101 Section version not Version 4
124102 Cannot read CONFIG section
124103 Error initializing NVRAM interfaces
Example DS:> 1241
124100: Divx model id high byte = 0x31, low byte = 0x30
Test OK @
HIGH-DEFINITION MULTIMEDIA INTERFACE (HDMI)

Nucleus Name DS_HDMI_DevTypeGet
Nucleus Number 1500
Description Get the device (revision) type information of the HDMI-IC.
Technical - Read out the information through IIC
User Input None
150000 Getting the device type of the nucleus succeeded
150001 Failed to retrieve the hardware diversity string
150002 Failed to initialise the IIC communication
150003 The hardware was not detected although indicated by Diversity
150004 Failed to access HDMI transmitter chip SI9030
Example DS:> 1500
150000:
Vendor ID : 0x 0 0x 1
Device ID : 0x91 0x42
Device Revision : 0x 0
Test OK @
Nucleus Name DS_HDMI_Communication

Nucleus Number 1501
Description Check the communication between the I2C controller on the Codec and the
HDMI-IC by reading and writing data to one device register. This test detects
faults of the I2C lines or a defected HDMI transmitter IC.
Technical - Read out an accessible register in the HDMI transmitter IC
- Modify this register by writing a known value to it
- Read back and check this value for correctness
User Input None
150100 Communicating with the HDMI tx chip succeeded
150104 An IIC-bus error occurred
150108 There was an IIC error upon the stop-condition
150109 The IIC bus was chosen wrong
150110 The IIC functionality is not running
150111 An unknown error was returned by the IIC read
150112 The data written did not equal the date read
Example DS:> 1501
150100:
Test OK @
Nucleus Name DS_HDMI_EdidParse

Nucleus Number 1502
Description Return the E-EDID (Enhanced Extended Display Identification Data) contained
in the HDMI / DVI able TV attached to the DVD+RW.
Parse the information retrieved to print the capabilities of the TV in user
understandable format
Technical - Read out the E-EDID through the DDC channel (IIC)
- Parse the information contained in the E-EDID
- Print out the information to the user in understandable format
User Input None
150200 Getting the configuration of the HDMI-IC succeeded
150204 Retrieving the E-EDID failed
Example DS:> 1502
Checksum OK of EDID block 0.
Checking EDID Structure with 1 extensions:

Checking each Extension for consistency.
E-EDID structure contains no errors.
EDID structure OK.
Vendor Specific Data Block: 03 0c 00 10 00
Attached Display is an HDMI device.
EDID Version 1.3
Total Native DTD Formats = 0
Monitor Features (CEA Byte 3): BasicAudio YCbCr444
YCbCr422
HDMI compatible EDID
Supported video format 1
index:0 Linear PCM 1 channels, 48KHz, 44KHz, 32KHz,
SPK:RLC FLC RC RL FC LFE FL

RRC FRC .. RR .. ... FR
Attached display is HDMI compatible.

Display is YCbCr444 compatible.
Display is YCbCr422 compatible.
150200:
Test OK @
Nucleus Name DS_HDMI_DefaultVideoSet

Nucleus Number 1503
Description Set a default video configuration in the HDMI TX chip (720x480p)
Technical - Write a known configuration for 720x480P in the registers of the HDMI
transmitter chip
User Input <Id> configures the HDMI transmitter to receive an embedded or a separated
sync signal at its input.
Chose embedded sync if signal comes directly from Leco+ (ITU656) or

separated sync if signal comes from Fli2310.
Id:
<id > HDMI Tx input configuration

0 Separated sync input (default)
1 Embedded sync input
150300 Setting the video configuration succeeded
150304 Setting the video configuration failed
Example DS:> 101 11 ntsc all
010100:
Test OK @
DS:> 1516
151600:
Test OK @
DS:> 1503
150300:
Test OK @
or
DS:> 101 0 ntsc pscan

010100:
Test OK @
DS:> 1503 1
150300:
Test OK @
Nucleus Name DS_HDMI_Reset

Nucleus Number 1504
Description Reset the HDMI transmitter chip by means of a hardware reset and re-initialize
in order to have the HDMI transmitter chip accessible again.
Technical - Pull the reset line connected to the HDMI transmitter low
- Wait a little while
- Enable the HDMI chip again by setting the reset line high
User Input None
150400 Resetting the HDMI tx chip succeeded
150404 Resetting the HDMI tx chip trhrough PIO failed.
150405 Software Reset of the HDMI tx chip failed.
Example DS:> 1504
150400:
Test OK @
Nucleus Name DS_HDMI_DdcIicWrite

Nucleus Number 1506
Description Perform an IIC write action to a device on the DDC bus
Technical -
User Input <TimeOut> <Slave address> <offset> <nr of bytes> <d1> <.> <dx>
150600 Writing to the device was OK, number of bytes is echoed
150604 Writing the bytes to the device failed
150605 Decoding time-out unsigned value failed
150607 Decoding offset unsigned value failed
150609 Number of bytes out of range. Should be less than 17.
150610 Incorrect number of data bytes entered
150611 Unable to initialise IIC
Example DS:> 1506 1 0xa0 1 0
150600:
Test OK @
DS:> 1506 1 0xa8 1 0

150604: Writing the bytes to the device failed.
Error @
Nucleus Name DS_HDMI_DdcIicRead

Nucleus Number 1507
Description Perform an IIC read action to a device on the DDC bus
Technical -
User Input <TimeOut> <Slave address> <Offset> <Number of bytes>
150700
150704 Reading from the device on the DDC bus failed
150705 Decoding time-out unsigned value failed
150707 Decoding offset unsigned value failed
Example DS:> 1507 1 0xa0 0 15
[ 0]:0x0
[ 1]:0xff
[ 2]:0xff
[ 3]:0xff
[ 4]:0xff
[ 5]:0xff
[ 6]:0xff
[ 7]:0x0
[ 8]:0x34
[ 9]:0xa9
[ 10]:0x53
[ 11]:0xc0
[ 12]:0x1a
[ 13]:0x0
[ 14]:0x0
150700:
Test OK @
Nucleus Name DS_HDMI_ExtendedWrite

Nucleus Number 1508
Description Perform an IIC write action on port 0/1 of the HDMI transmitter
Technical -
User Input <Port> <Register> <Data> Where 0 == Port 0 and 1 == Port 1
150800 Byte was written OK
150804 A wrong port number was given by the user
150805 An invalid register was given by the user
150806 Invalid data was given by the user
150807 There was an error writing to the register indicated
Example DS:> 1508 0 0x10 0x22
150800:
Test OK @
Nucleus Name DS_HDMI_ExtendedRead

Nucleus Number 1509
Description Perform an IIC read action on port 0 or 1 of the HDMI transmitter
Technical -
User Input <Port> <Register> Where 0 == Port0 and 1 == Port 1
150900 Byte was read and echoed OK
150904 A wrong port number was given by the user
150905 An invalid register was given by the user
150906 There was an error reading the register indicated
Example DS:> 1509 0 0x10
150900: Data read: 0x22
Test OK @
Nucleus Name DS_HDMI_CheckHPDTx

Nucleus Number 1510
Description Check whether Hot-Plugging of the HDMI cable is detected by the SII9030
HDMI transmitter.
Technical -
User Input None
151000 The Hot Plug was detected OK by the HDMI transmitter
151004 Error writing to interrupt register
151005 Error reading interrupt register
151006 Test aborted by user
151007 Unknown action
Example DS:> 1510
Insert or remove the HDMI cable.(or type 'a' to abort):
151006: Test aborted by user.
Test OK @
DS:> 1510
151000:
Test OK @
Nucleus Name DS_HDMI_CheckHPDChrysalis

Nucleus Number 1511
Description Check whether Hot-Plugging of the HDMI cable is detected by the software.
This tests the interrupt line to the Chrysalis.
Technical -
User Input None
151100 The Hot Plug was detected OK by software. Interrupt line OK.
151104 Error writing to HDMI tx register
151105 User aborted HPD test
151106 Error reading from HDMI tx register
Example DS:> 1511
151100:
Test OK @
DS:> 1511
151105: User aborted HPD test.
Test OK @
Nucleus Name DS_HDMI_FLI2310_DevTypeGet

Nucleus Number 1512
Description Get the device and revision information of the FLI2310
Technical -
User Input None
151200 Retrieving the device type information succeeded
Example DS:> 1512
151200:
Chip name : 2300
Chip version : 4
Test OK @
Nucleus Name DS_HDMI_FLI2310_Communication

Nucleus Number 1513
Description Test whether the communication to the FLI2310 can be established
Technical -
User Input None
151300 Something is properly read so the communication is OK
151309 The read data is not the same as the written data
Example DS:> 1513
151300:
Test OK @
Nucleus Name DS_HDMI_FLI2310_TestImageOn

Nucleus Number 1514
Description Generate a test image using the FLI2310
Technical -
User Input None
151400 Test image is generated successfully
151404 Unable to generate image
151405 Unable to initialise De-inter-lacer
Example DS:> 1514
151400:
Test OK @
Nucleus Name DS_HDMI_FLI2310_TestImageOff

Nucleus Number 1515
Description Switch of test-image generation by the FLI2310
Technical -
User Input None
151500 Test image is turned off successfully
151504 Unable to initialise De-Inter-lacer
151505 IIC Error during writing DENC
Example DS:> 1515
151500:
Test OK @
Nucleus Name DS_HDMI_FLI2310_Routing

Nucleus Number 1516
Description Have the FLI2310 pass the video from its input to its output
Technical -
User Input None
151600 Routing path is created successfully
151604 Unable to initialise the Chrysalis.
151605 Unable to access de-inter-lacer
Example DS:> 1516
151600:
Test OK @
Nucleus Name DS_HDMI_FLI2310_ExtendedWrite

Nucleus Number 1517
Description Write to any register of the FLI2310
Technical -
User Input <Register> <RegLen:1=8bits;2=16bits> <Data>
151700 The IIC write action succeeded
151704 Decoding register unsigned value failed
151705 Decoding register length unsigned value failed
151706 Decoding register data unsigned value failed
151707 Error writing to register
Example DS:> 1517 0x303 1 0x9a
151700:
Test OK @
Nucleus Name DS_HDMI_FLI2310_ExtendedRead

Nucleus Number 1518
Description Read from any register of the FLI2310
Technical -
User Input <Register> <RegLen:1=8bits;2=16bits>
151800 The IIC read action succeeded
151804 Decoding register unsigned value failed
151805 Decoding register length unsigned value failed
151806 Error reading from the register
Example DS:> 1518 0x303 1
151800: Data read: 0x009A
Test OK @
Nucleus Name DS_HDMI_FLI2310_1080I

Nucleus Number 1519
Description Set the Faroudja FLI2310 to generate a 1080I image from the video on its
inputs.
Technical -
User Input None
151900 Generating the up-scaled image succeeded
151904 Generating the up-scaled image failed
151905 Unable to configure HDMI Tx.
Example DS:> 1519
151900:
Test OK @
Nucleus Name DS_HDMI_Audio

Nucleus Number 1528
Description Set the proper audio settings to the HDMI transmitter.
Note: When 1528 spdif is used to set the HDMI transmitter audio settings
correctly and just 103 is entered i.s.o. 103 spdif then ‘clicking’ audio is heard
because the Chrysalis audio decoder does not use its SPDIF-path explicitly.
Note: Currently there is an issue in the order of the tests:

- Reboot the set.
- First create the video, as audio is passed alongside the video on HDMI
- Create the spdif audio using nucleus 103 spdif
- Create the spdif audio settings in the HDMI transmitter using nucleus
1528 spdif
- The spdif audio will be audible
- Switch off spdif audio using nucleus 104
- Create i2s audio using nucleus 103
- Create the i2s audio settings in the HDMI transmitter using nucleus
1528 or 1528 I2S
- The audio will be audible
- Switch off the audio using nucleus 104
Technical -
User Input ‘SPDIF’ - Set the HDMI transmitter's audio path to SPDIF
‘I2S’ or nothing - Set the HDMI transmitter's audio path to I2S
152800 Creating the proper audio settings succeeded
Example DS:> 1528 i2s
152800: i2s
Test OK @
DS:> 1528 spdif

152800: spdif
Test OK @
ANALOGUE SLAVE PROCESSOR (ASP)

Nucleus Name DS_ASP_Communication
Nucleus Number 1600
Description This nucleus checks the communication between the IIC controller of the Codec
and the ASP.
Technical - Initialise IIC-bus.
- Read something from ASP.
- Handle the errorcode.
User Input None
160000 Communicating with the ASP succeeded
160005 Got unknown IIC bus error
Example DS:> 1600
160000:
Test OK @
Nucleus Name DS_ASP_Version

Nucleus Number 1601
Description This nucleus returns the version number of the software running on the ASP or
MCU and if available that of the display driver.
Technical - Read versions from ASP and display it.
User Input None
160100 Retrieving the software versions succeeded
160101 The IIC bus initialisation failed.
160102 The IIC bus failed.
160103 The CRC checksum of the message is wrong.
Example DS:> 1601
160100:
Software version : 0.9
Display driver version: 0.1
Hardware version : 0x02
Hardware layout : 0x03
Hardware revision : 0x00
Test OK @
Nucleus Name DS_ASP_RealTimeClockSetValues

Nucleus Number 1602
Description This nucleus is used to set the real time clock to the correct values.
Technical - Decode the user input.
- Write RTC value to ASP.
User Input User must give time and date like this:
hh:mm:ss dd/mm/yy
160200 Setting the real time clock succeeded
160201 The ASP initialisation failed.
160203 Wrong user input.
Example DS:> 1602 03:20:01 22/06/03
160200:
Test OK @
Nucleus Name DS_ASP_RealTimeClockGetValues

Nucleus Number 1603
Description This nucleus is used to retrieve the actual real time from the ASP
Technical - Read RTC value from ASP.
- Decode the RTC value.
User Input None
160300 Retrieving the real time succeeded
160301 The ASP initialisation failed.
160303 The CRC checksum of the message is wrong.
160304 The Real Time Clock has been found invalid or was not found.
Example DS:> 1603
Time: 03:20:17
Date: 22/06/03 (dd/mm/yy)
160300:
Test OK @
Nucleus Name DS_ASP_NTCGet

Nucleus Number 1606
Description This nucleus reads the value of the NTC-resistor connected to the ASP, which
tells the ambient temperature to the processor.
Technical - Read the ADC input pin of the ASP that is connected to the NTC-resistor.
- Display this value.
User Input None
160600 Getting the NTC-value succeeded
160601 The IIC bus failed
Example DS:> 1606
160600: Temperature(NTC) ADC input value = 0x94
Test OK @
Nucleus Name DS_ASP_FanSpeedSet

Nucleus Number 1607
Description This nucleus sets the speed of the fan that controls the temperature within the
set.
Technical - Decode user input.
- Set pio-pins FAN_C1 and FAN_C2.
User Input Speed to be set: off, low, medium, high
160700 Setting the new fan speed succeeded
160701 The IIC bus failed
Example DS:> 1607 low
160700:
Test OK @
Nucleus Name DS_ASP_LightDisplay

Nucleus Number 1608
Description This nucleus lights the entire display.
Technical - Set all segments on in the display buffer.
- Set the grids correct in the display buffer.
- Send the display buffer to the ASP.
User Input None
160800 Lighting the entire display succeeded
160801 IIC-bus communication failed
Example DS:> 1608
160800:
Test OK @
Nucleus Name DS_ASP_BlinkDisplay

Nucleus Number 1609
Description This nucleus lights the entire display, and lets it blink. Only for ASP
Technical - Set all segments on in the blink buffer.
- Set the grids correct in the blink buffer.
- Send the blink buffer to the ASP.
User Input None or ‘on’ to start the blinking of the display.
‘off’ To stop the blinking of the display.
160900 The test succeeded
Example ASP DS:> 1609
160900:
Test OK @
DS:> 1609 off

160900:
Test OK @
Nucleus Name DS_ASP_DimmingDisplay

Nucleus Number 1610
Description This nucleus lights the entire display, and dims it.
Technical - Change in a loop the display brightness from maximum to minimum.
User Input ‘ON’ or ‘OFF’
Example DS:> 1610 ON
161000:
Test OK @
Nucleus Name DS_ASP_ClearDisplay

Nucleus Number 1611
Description This nucleus clears the display and deactivates dimming/blinking functionality
Technical - Make the display buffer empty.
- Make the blink buffer empty.
- Send the display buffer to the ASP.
- Send the blink buffer to the ASP.
User Input None
Example DS:> 1611
161100:
Test OK @
Nucleus Name DS_ASP_KeyBoard

Nucleus Number 1612
Description This nucleus checks all keys of the keyboard by having the user confirm the
key-code displayed of all keys. If the user presses ‘a’ or ‘A’ the test is aborted.
If the user presses ‘o’ or ‘O’ the test is indicated as OK.
If the user holds down ‘PLAY’ for more than a second the test is indicated as
OK, if the user holds down ‘RECORD’ the test is indicated as failed.
Indicate the number of keys pressed to the user, both in the terminal logging
and on the display.
Technical - Initialise the display.
- Display the key pressed by the user on the display.
- Monitor the service port for an abort and get the next key pressed.
- Update the display and repeat previous steps until user stops / confirms.
- Display the number of keys that were pressed.
Execution Time Depends on the user.
User Input None
161200 Checking all keys succeeded
161202 The user signals a failure of the keyboard
161203 The user aborted the test
Example DS:> 1612
161200: 3 keys were pressed.
Test OK @
Nucleus Name DS_ASP_RemoteControl

Nucleus Number 1613
Description This nucleus checks the interface to the remote control by having the user
confirm the key-code displayed.
At least one key must be tested.
If the user presses ‘a’ or ‘A’ the test is aborted. If the user presses ‘o’ or ‘O’ the
test is indicated as OK.
If the user holds down ‘PLAY’ for more than a second the test is indicated as
OK, if the user holds down ‘RECORD’ the test is indicated as failed.
Indicate the number of keys pressed to the user, both in the terminal logging
and on the display.
Technical - Initialise the display.
- Display the key pressed by the user on the display.
- Monitor the service port for an abort and get the next key pressed.
- Update the display and repeat previous steps until user stops / confirms.
- Display the number of keys that were pressed.
Execution Time Depends on the user.
User Input None
161302 The user signals a failure of the remote control
161303 The user aborted the test
Example DS:> 1613
161300: 4 keys were pressed.
Test OK @
Nucleus Name DS_ASP_LEDsOn

Nucleus Number 1614
Description Switches on the display leds.
Technical ASP specific
- Check if the analogue board is a MOBO board, if so:
- Read the ASP pio port.
- Set the RECORD-LED bit on in this port.
- Write the ASP pio port.
- Set the TRAY-LED bit on in this port.
- Set the EPG-LED bit on in this port.
- Else
- Set the RECORD-LED bit on.
- Write the external ASP pio port.
- Set the TRAY-LED bit on.
- Set the EPG-LED bit on.
MCU Specific
- Get the user input and capitalize it and check validity
- Check which lights should be turned on
- Write the command to the MCU
User Input None, Green or Red: Choose which colour of the bi-led should be lit with the
rest (only for OLAL22PREMIER variant)
161400 Switching on the LEDs succeeded
Example DS:> 1614
161400:
Test OK @
Nucleus Name DS_ASP_LEDsOff

Nucleus Number 1615
Description This nucleus switches off the display leds.
Technical ASP specific
- Check if the analogue board is a MOBO board, if so:
- Set the RECORD-LED bit off in this port.
- Set the TRAY-LED bit off in this port.
- Set the EPG-LED bit off in this port.
- Else
- Set the RECORD-LED bit off.
- Set the TRAY-LED bit off.
- Set the EPG-LED bit off.
MCU Specific
- Write the command to the MCU to turn all display leds off
User Input None
161500 Switching off the LEDs succeeded
Example DS:> 1615
161500:
Test OK @
Nucleus Name DS_ASP_Reset

Nucleus Number 1616
Description This nucleus resets the ASP.
Technical - Reset the ASP by toggling the reset wire by a GPIO pin of the codec.
- Wait 500ms according to the HSI.
- Read Status from ASP.
- Put ASP in normal mode.
- Configure general ASP PIO.
- Make a ASP pio pin low to read the version.
- Get GPP40 - GPP47 and GPP48 - GPP55.
- Decode hardware version, revision, and layout.
- Configure the ASP clock.
- Configure display, part 1.
- Configure display, part 2.
- Configure blinking.
- Configure external ASP PIO.
- Configure ADC input.
- Configure remote control input.
- Enable power on the AV3.
User Input None
161600 Reset command succeeded
Example DS:> 1616
161600:
Test OK @
Nucleus Name DS_ASP_Watchdog

Nucleus Number 1618
Description This nucleus configures the watchdog timer of the ASP, and waits till the
watchdog expires. The watchdog time-out is 10 seconds. On expiry of the
watchdog timer, the ASP switching off, and on its power supply, and resets the
main controller.
So, this nucleus will not return an error code when the test succeeded, but the
system will restart again.
Technical - Configure watchdog timer.
- Wait till the watchdog expired.
User Input None
161801 IIC-bus communication failed.
161802 The ASP did not reset the host processor.
Example DS:> 1618
Waiting till the watchdog expires.
Factory Diagnostics and Service Software

DVD Video Recorder (Sep 10 2004, 08:11:24)
Version :662 Build :20040910_0515

Release :C1_1 Buildtype :no
Baseline :F_C1_195 Variant :verum:dvdrw2_lib
DS:>
Nucleus Name DS_ASP_Reboot

Nucleus Number 1619
Description This command forces a reboot of the main controller. The ASP shutdown the
digital board power supply and then switch it on to force reset.
So, this nucleus will not return an error code when the test succeeded, but the
system will restart again.
Technical - Send command reboot to ASP.
User Input None
161901 IIC-bus communication failed.
161902 The ASP did not reset the host processor.
Example DS:> 1619
Factory Diagnostics and Service Software
DVD Video Recorder (Sep 10 2004, 08:11:24)
Version :662 Build :20040910_0515

Release :C1_1 Buildtype :no
Baseline :F_C1_195 Variant :verum:dvdrw2_lib
DS:>
Nucleus Name DS_ASP_PioExtended

Nucleus Number 1623
Description This nucleus enables the user to switch all the General Purpose Pins of the
ASP.
Technical - Decode user input.
- Execute the parameter command.
User Input One of the next parameters can be used
� “GPIO CONFIG <GPP> <DIR> <MODE>"
� "GPIO SET <GPP> <VALUE>"
� "GPIO GET <GPP>"
� "ADC GET <GPP>"
� "ADC CONFIG <BYTE0> <BYTE1> <BYTE2>"
(See CONFIG_ADC command parameters)
where <GPP> = 0 .. number of GPP pins
where <DIR> = 0 (input) or 1 (output)
where <MODE> = 0 or 1
0 = input without notification/push-pull output
1 = input with notification/open drain output
where <VALUE> = 0 (low) or 1 (high)
162301 Invalid user input.
Example DS:> 1623 GPIO SET 45 0
162300:
Test OK @
Nucleus Name DS_ASP_8SC2Check

Nucleus Number 1624
Description Check if the 8SC2 signal (slow blanking) can be set low, medium and high. The
user must connect SCART2 (pin8) to SCART1 (pin8) on the outside of the set.
Works on EURO sets only.
Technical - Set the SCART1_PIN8_OUT pin low
- Measure the value on the ASP 8SC2 input ADC
- Set the SCART1_PIN8_OUT pin to medium level
- Measure the value on the 8SC2 input ADC
- Set the SCART1_PIN8_OUT pin Matrix high
- Measure the value on the ASP 8SC2 input ADC
User Input None
162400 Detecting 8SC2 signal succeeded
162401 Detecting 8SC2 signal failed
162402 This test is not applicable for current HW layout
162403 Could not retrieve hardware version from ASP
Example DS:> 1624
162400:
Test OK @
FRONTEND (TUNER) (FRE)

Nucleus Name DS_FRE_Communication
Nucleus Number 2000
Description This nucleus checks the communication between the IIC controller of the Codec
and the Front End (Tuner) on the analogue board
Technical - Determine whether anything can be read from the FRE through IIC
User Input None
200000 Communicating with the front end succeeded
200005 Got unknown IIC bus error
Example DS:> 2000
200000:
Test OK @
Nucleus Name DS_FRE_ChannelSelect

Nucleus Number 2001
Description This nucleus sets the tuner to receive a valid audio and video signal
Technical - Parse the user input to determine all parameters to set
- Pass these parameters to the respective parts using IIC
User Input <Frequency*16> <video standard id> <Tuner>
Tuner frequency: to tune the tuner to e.g. 216 MHz, this parameter must be
3456. (Since 216*16 = 3456. This is to avoid the decimal points to the
parameter list.)
Name Colour system Transmission Sound modulation

standard
PAL_BG_S PAL BG FM-Stereo
PAL_BG_M PAL BG FM-Mono / NICAM
PAL_I_M PAL I FM-Mono / NICAM
PAL_DK_S PAL DK FM-Stereo
PAL_DK_M PAL DK FM-Mono / NICAM
NTSC_M_S NTSC M FM-Stereo
Video Standard ID: The table below shows which video standards are possible
ID Europe Nafta / Apac
0 PAL_BG_S NTSC
1 PAL_BG_M Invalid
2 PAL_I_M Invalid
3 PAL_DK_S Invalid
4 PAL_DK_M Invalid
* Video Standard ID: For TCSM0601PD25F tuner only

ID Europe
0 PAL_BG
1 PA_I
2 PAL_DK
3 SECMA L
4 SECAM L’
Tuner: Select the tuner type that you want to tune. This input is not mandatory.
(If no input is detected, tuner will be defined run-time (if recognised).)
Tuner Tuner ID Runtime Detected

1 FE1316 (Europe Philips) V
2 FE1319 (Europe Philips) V
3 TMQZ2-403A (Europe ALPS)
4 JS6B2-L121 (Europe Xuguang)
5 TCPK0601 (APAC Samsung)
6 TCMN0682 (NAFTA Samsung) V
7 TCPK0600 (APAC Samsung)
8 TCPD0601 (APAC Samsung)
9 VPC12R_ENG56PPG1F (Panasonic)
10 * TCSM0601PD25F (Europe Samsung)
11 TCSN9082PA26AF (Nafta Samsung)
* Refer to Video Standard ID table for TCSM0601PD25F tuner

200100 Setting the tuner channel succeeded
200101 Invalid user input
200102 Getting the version of the set failed
200103 Configuration of the tuner failed
200104 Configuration of the IF module failed
Example DS:> 2001 3456 0 1
200100:
Test OK @
HARD DISK DRIVE (HDD)

Nucleus Name DS_HDD_Communication
Nucleus Number 2100
Description Check the communication between the digital board and the hard disk drive by
querying the device type of the hard disk drive
Technical - Initialise/start IDE
- Check for an ATA device on the IDE interface
User Input None
210000 Communication with the hard disk drive succeeded
210001 The initialisation of IDE failed
210002 Communication with the hard disk drive failed
Example DS:> 2100
210000: Found a hard disk drive: MASTER device on IDE interface 1
Test OK @
Nucleus Name DS_HDD_Reset

Nucleus Number 2101
Description Reset the hard disk drive
- Toggle the IDE reset pin of the selected interface
User Input None
Error 210100 Resetting the hard disk drive succeeded
210103 Failed to reset the hard disk drive
Example DS:> 2101
210100: Resetting IDE interface 1 succeeded
Test OK @
Nucleus Name DS_HDD_VersionGet

Nucleus Number 2102
Description Get the vendor- and product identification and the product revision level of the
hard disk drive
- Send ATA command IDENTIFY DRIVE
- Display the serial, firmware revision and model information
User Input None
Error 210200 Version info successfully
210203 Failed to get version info from the hard disk drive
Example DS:> 2102
210200: Serial number = F19LP8WE,Firmware rev. = VAM51JJ0 ,Model
nu
mber = Maxtor 2F040L0
Test OK @
Nucleus Name DS_HDD_WriteRead

Nucleus Number 2103
Description Write data to the hard disk, read it back and verify the data read back.
- Generate a random sector number
- Generate test data to write to the disk
- Read the data from the sector using READ_SECTOR(S) and store this in a
temporarily buffer
- Transfer the test data to the disk location using ATA command
WRITE_SECTOR(S)
- Read back the data from the disk location using ATA command
READ_SECTOR(S)
- Write back the data from the temporarily buffer
User Input None
Error 210300 Version info successfully
210303 Unable to retrieve device capabilities from HDD
210304 Writing data to HDD failed
210305 Reading back data from HDD failed
210306 Data read back did not equal written data
Example DS:> 2103
210300: OK, writing to sector 3f95776
Test OK @
Nucleus Name DS_HDD_CapabilitiesGet

Nucleus Number 2104
Description Get the cylinders, heads and track information of the hard disk drive
- Send ATA command Identify drive information
- Display all required capabilities
User Input None
Error 210400 Capabilities are displayed correctly
210403 Failed to get information from the hard disk drive
Example DS:> 2104
Number of cylinders 16383
Number of heads 16
Number of sectors per track 63
Capacity in sectors 80293248
Number of current cylinders 16383
Number of current heads 16
Number of current sectors per track 63
Current capacity in sectors 16514064
Number of unformatted bytes per track 0
Number of unformatted bytes per sector 0
210400:
Test OK @
Nucleus Name DS_HDD_Diagnostics

Nucleus Number 2105
Description Shall perform the internal diagnostic tests implemented by the hard disk drive.
- Send the diagnostic (ATA) command to the HDD device
User Input None
210500 The Diagnostic test on the hard disk drive device succeeded
210501 The hard disk drive failed
210501 The diagnostics ATA command failed
Example DS:> 2105
210500:
Test OK @
Nucleus Name DS_HDD_UploadImage

Nucleus Number 2106
Description Upload raw data from the HDD to a DVD+RW
- Check for an ATAPI DVD+RW drive
- Calibrate the DVD+RW laser
- Repeat until transfer is completed
- Read x MB from HDD source sector into SDRAM
- Write x MB from SDRAM to the destination sector on DVD+RW
- Read sector 0x34000 on DVD containing the transfer table to use
- Update the contents of the table and write it back
Execution Time Depending on the number of sectors to transfer it may take approximately 2 MB
per second.
User Input The user can enter 3 parameters in the next format:
<COMMAND> <HDD sector> <nr of HDD sectors>
<COMMAND> is one of the next strings:
� NEW: Create a new transfer image table, <HDD sector> and <nr of
HDD sectors> must be entered.
� ADD: Add a section to the current transfer table, <HDD sector> and
<nr of HDD sectors> must be entered
� READ: Read the current transfer image table from the DVD. The tray
of the DVD drive is sent out an the user is asked to insert a DVD+RW
� VIEW: View the contents of the current transfer table
� GO: Copy data from the HDD to the DVD+RW according to the
currently entered transfer table
<HDD sector> = the sector on HDD to start reading from
<HDD sectors> = the number of HDD sectors to transfer
210600 Uploading image succeeded
210603 Communication with the AV3 failed
210604 No DVD+RW is available
210605 Calibrating DVD+RW failed
210607 Error while reading image data from HDD
210608 Error while writing image to DVD+RW
210609 Unable to update the transfer table on the DVD+RW
Example DS:> 2106

210605: Invalid user input
Error @
DS:> 2106 READ

Please insert a writable DVD+RW
210609: Unable to update transfer table
Error @
DS:> 2106 NEW 0x1 2048

Creating new transfer table
Adding entry 1 to transfer table
Length 1 entries
210605: NEW 0X1 2048
Test OK @
DS:> 2106 VIEW

Length 1 entries
Entry 1:
hddPosition : 0x1
nrHddSectors : 0x800
dvdPosition : 0x34040
nrDvdSectors : 0x200
210605: VIEW
Test OK @
DS:> 2106 ADD 0x2001 20480

Adding entry 2 to transfer table
Length 2 entries
210605: ADD 0X2001 20480
Test OK @
DS:> 2106 GO
Please insert a writable DVD+RW
Executing transfer table 1 of 1, size 1048576 bytes (=1 MB)
Calibrating laser of DVD drive
Start creating image on DVD at 0x34040. Checking ... <OK>
210600: Transfer OK
Test OK @
Nucleus Name DS_HDD_DownloadImage

Nucleus Number 2107
Description Download a raw image from a DVD+RW disc to the hard disc drive. This image
will be written on the hard disc drive.
- Check for an ATAPI DVD+RW drive
- Mount the DVD containing the image to transfer
- Read sector x containing the transfer table to use
- Read the source sector, destination sector and transfer length from the
transfer table
- Repeat until transfer is completed
- Read x MB from DVD source sector into SDRAM
- Write x MB from SDRAM to the destination sector on HDD
Execution Time Assumption based on 4.3GB data � 11 movies of 3 minutes.
33 minutes
User Input Actions:
The tray of the DVD drive is sent out and the user is asked to insert a DVD+RW
210700 Downloading image succeeded
210703 Communication with the AV3 failed
210704 No disc is available
210705 Invalid medium is mounted
210706 Unable to read the transfer table from DVD
210707 Error while reading image from DVD
210708 Error while writing image to HDD
Example DS:> 2107
Please insert the Master DVD <OK>
Executing transfer table 1 of 4
524288 bytes
Dvd Sector 0x50000
Dvd Sector Count 256
Hdd Sector 0x40000
Hdd Sector Count 1024
please wait ..<OK>
10485760 bytes (=10 MB)
Dvd Sector 0x70000
Hdd Sector 0x60000
please wait ..<OK>
524288 bytes
Dvd Sector 0x50000
Hdd Sector 0x40000
please wait ..<OK>
524288 bytes
Dvd Sector 0x50000
Hdd Sector 0x40000
please wait ..<OK>
210700: Transfer OK
Test OK @
Nucleus Name DS_HDD_RandomReadScan

Nucleus Number 2108
Description Perform a short random read scan of x times 1000 commands (x is
selectable between 1 to 20) to test the servo. If anything would
be wrong with the servo or tracking, the result would be too
slow. Recheck the LBA addresses that caused the disc to fail in
order to avoid incorrect failure caused by shock or vibrations
during the measurement.
Technical - Initialise the HDD connection
- Get the user input
- Generate a random sequence of test sectors
- For every sector in the random sequence do
- Read 1000 sectors and measure the time to perform this action
- Update a list of statistics about the measurement
- Display statistical information about the test sequence
- If more than 10% above 160 ms and/or more than 1 request in between
200 & 250ms and/or requests above 250 ms make the result of the test fail.
Execution Time Depending on the user input x times 4 minutes
User Input parameters in the next format:
<nr_cmds><GRAPH>
- Number of commands to send (in multiples of 1000), if no input
is given 1000 commands will be sent
- "GRAPH" optional to print out the measured read scan graph
210801 The initialisation of the HDD failed
210803 Performance failure: more than 10% above 160 ms and/or
more than 1 request in between 200 & 250ms and/or
requests above 250 msec
210804 Read error, unable to read a specified sector from disc
Example DS:> 2108 1
210800:
Minimum access time = 142 msec
Maximum access time = 159 msec
Average access time = 146 msec
Number of commands below 160 msec = 1000
Number of commands between 160 and 200 msec = 0
Number of commands above 250 = 0
Test OK @
Nucleus Name DS_HDD_LinearSurfaceScan

Nucleus Number 2109
Description Perform a linear surface scan so that most of the disc is covered.
Technical - Initialise the HDD connection
- Get the user input
- Generate a sequence of test sectors according to the user input
- For every sector in the sequence do
- Read the sector and measure the time to perform this action
- Update a list of statistics about the measurement
- Display statistical information about the test sequence
- If more than 1% above 100 ms and/or more than 0.1% above 200 msec
and/or requests above 300 msec make the result of the test fail.
Execution Time Depending on the user input and HDD size
User Input parameters in the next format:
<SECTORS> <STEP> <LOW> <HIGH>
where
- SECTORS: Specifies the number of sectors to read in each access
- STEP: Specifies the step (in sectors) between each access.
- LOW: The start sector address of an explicit range of LBA
addresses to be used for testing. If no value is entered LBA
0 will be used
- HIGH: The end sector address of an explicit range of LBA
addresses to be used for testing. If no value is entered the
maximum LBA will be used.
The user must enter either no parameter or all parameters
If no parameters are entered the next defaults will be used:
1000 sector each access, steps of 1000 sectors and an address
range from 0 to the maximum LBA
210901 The initialisation of the HDD failed
210903 Performance failure: more than 10% above 160 ms and/or
more than 1 request in between 200 & 250ms and/or
requests above 250 msec
210904 Read error, unable to read a specified sector from disc
Example DS:> 2109 1000 1000 0 100000
210900:
Executed 100 linear seeks of 1000 sectors each
Minimum access time = 141 msec
Maximum access time = 148 msec
Average access time = 141 msec
Number of commands below 160 msec = 100
Number of commands above 250 = 0
Test OK @
Nucleus Name DS_HDD_SpinOff

Nucleus Number 2110
Description Put the HDD in parking position by sending the sleep command so it can be
moved without endangering the mechanical parts
- Send the Sleep (ATA) command to the HDD device
User Input None
211000 The spin off of the hard disk drive device succeeded
211003 The sleep ATA command failed
Note All other HDD nuclei will not work until DS_HDD_Reset is executed
Example DS:> 2110
211000:
Test OK @
Nucleus Name DS_HDD_SectorRead

Nucleus Number 2111
Description Read 512 bytes from a specified sector on HDD
Technical - Get the user input
- Read the data from the sector using READ_SECTOR(S) and display the
contents
User Input 3 parameters in the next format: <sector> <offset> <length>
where
- sector is the sector to read from
- offset is the byte-offset in the sector buffer (0 .. 256)
- length the length (in bytes) of the data to display (1 .. 256)
211100 Reading from HDD succeeded
211104 The read command failed
Example DS:> 2111 0x80001 0 128
211100:
0x00 : 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF
Test OK @
Nucleus Name DS_HDD_SetPower

Nucleus Number 2112
Description Set the power of the HDD On or Off
Technical - Get user input
- Set the IDE1_POWER PIO line to the desired value
User Input 1 parameter:
"ON" , enables the power of the HDD
"OFF" , turn off the power of the HDD
211200 Setting the HDD power mode succeeded
211201 Setting the HDD power mode failed
Note All other HDD nuclei will not work until DS_HDD_Reset is executed
Example DS:> 2112 off
211200:
Test OK @
Nucleus Name DS_HDD_ValidateBootSegmentHeader

Nucleus Number 2113
Description Validates the Boot Segment Header in the HDD.
Technical - Initializes the HDD interface.
- Reads 8 bytes from LBA 0x8001
- Compares these 8 bytes with 0x42,0x4F,0x4F,0x54,0x2D,0x48,0x44,0x4D
- If identical, returns pass. Else Hard Disk Boot Segment Header is corrupt.
User Input None.
211300 Validation of Hard Disk Boot Segment Header passed.
211301 Hard Disk Boot Segment Header corrupt or does not match
expected values.
211302 HDD init failed.
211303 Starting HDD failed.
211304 Reading from HDD failed.
Example DS:> 2113
211300:
Test OK @
UNIVERSAL SERIAL BUS (USB)

Nucleus Name DS_USB_DevTypeGet
Nucleus Number 2300
Description This nucleus retrieves the device and type information of the USB controller
Technical - Read out the chip-ID and revision register and return the info to the user
Execution Time < 1 sec.
User Input None
230000 Retrieving the device type information succeeded
Example DS:> 2300
230000: USB Controller chip ID: 0x6123 Revision:0x10.
Test OK @
Nucleus Name DS_USB_Reset

Nucleus Number 2301
Description This nucleus performs a software reset of the controller and tests whether the
functional state of the controller has become USBReset
Technical - Write the command to software reset the controller and read back the
functional status of the controller
User Input None
230100 Resetting the host controller succeeded
230101 Resetting the host controller failed
Example DS:> 2301
230100:
Test OK @
Nucleus Name DS_USB_CheckDeviceConnect

Nucleus Number 2302
Description This nucleus checks whether a device connect / disconnect can be aught by the
software
Technical - Initialise the host controller and its interrupts
- wait for the port connect status change interrupt
- display the status cause (connect/disconnect) of the interrupt
Execution Time Depending on user actions
User Input None
230200 The device connect was noticed by the hardware correctly
230201 Retrieving the information from the diversity string failed
230202 User aborted HPD test
Example DS:> 2302
Insert or remove the USB cable (or type 'a' to abort):
230200:
Test OK @
Nucleus Name DS_USB_ CheckDeviceSpeed

Nucleus Number 2303
Description This nucleus checks whether the connected device functions at low / full or high
speed.
Technical - Initialise the host controller and its interrupts
- Find out the total number of ports
- Read out the port status and display it
User Input None
230300 The device connect was noticed by the hardware correctly
230301 Retrieving the information from the diversity string failed
230302 User aborted the test
Example DS:> 2302
230200: Full Speed device on port number: 1
Test OK @
SCRIPT (SCRIPT)
Nucleus Name DS_IH_ScriptHandler
Nucleus Number Script
Description The test requires no user interaction. A number of nuclei will be run before a
message is returned indicating if there is a failure in the DVD Recorder. When a
nucleus failed, the script stops and displays the message "FAIL". Otherwise it
displays "PASS" at the end when all nuclei are executed. During the execution
of a script, a progress indicator is displayed on the display of the DVD
Recorder.
Technical Execute the included nuclei one by one
If a nucleus fails quit and display the failed nucleus on the local display and
service port
Included tests: 1. DS_CHR_DEVTYPEGET_NUC
2. DS_SDRAM_WRITEREADFAST_NUC
3. DS_FLASH_DEVTYPEGET_NUC
4. DS_FLASH_CHECKSUMPROGRAM_NUC
5. DS_VIP_COMMUNICATION_NUC
6. DS_VIP_DEVTYPEGET_NUC
7. DS_DVIO_LINKDEVTYPEGET_NUC
8. DS_DVIO_PHYCOMMUNICATION_NUC
9. DS_DVIO_PHYDEVTYPEGET_NUC
10. DS_BE_COMMUNICATIONECHO_NUC
11. DS_BE_VERSIONGET_NUC
12. DS_SYS_HARDWAREVERSIONGET_NUC
13. DS_SYS_SOFTWAREVERSIONBOOTGET_NUC
14. DS_SYS_SOFTWAREVERSIONDOWNLOADGET_NUC
15. DS_SYS_SOFTWAREVERSIONAPPLGET_NUC
16. DS_SYS_DVIDNUMBERGET_NUC
17. DS_SYS_SLASHVERSIONGET_NUC
18. DS_SYS_SETTINGSDISPLAY_NUC
19. DS_SYS_BUILDINFOGET_NUC
20. DS_ASP_COMM_NUC
21. DS_ASP_VERSION_NUC
22. DS_FRE_COMM_NUC
23. DS_HDD_COMMUNICATION_NUC
24. DS_HDD_VERSION_NUC
DS_USB_DEVTYPEGET_NUC
Note! Invocation by holding down the PLAY button when powering up the
system
Note! The following example is for Lecoplus variant only
Example Factory Diagnostics and Service Software
DVD Video Recorder (Dec 15 2006, 14:14:54)
Version :1463 Build :20061215_1352

Release :SG1_1 Buildtype :dev
Baseline :SGP29atl#SG1_1_20050609_base Variant :lecoplusleadV1
Executing User/Dealer script.
Busy executing NUC100

Device ID 7300
Codec ID PNX7350
F-BCU (0x0102) 4.0 INTC (0x011d) 3.0 SIF (0xa04b) 2.0
BOOT (0x010a) 3.1 CONFIG (0x013f) 5.0 RESET (0x0123) 5.0
CLOCK (0x013e) 7.0 DEBUG (0x0116) 0.1 UART0 (0x0107) 1.2
UART1 (0x0107) 1.2 I2C0 (0x0105) 0.1 I2C1 (0x0105) 0.1
GPIO (0x013c) 3.1 SYNC (0x013a) 4.0 OSD (0x0136) 1.0
SPU (0xa00e) 1.1 MIXER (0x0137) 3.0 DENC (0x0138) 5.0
CCIR (0x0139) 2.1 VDEC (0x0133) 1.0 PARSER (0xa00d) 0.0
DV (0xa00c) 0.0 IDE0 (0xa009) 1.2 IDE1 (0xa009) 1.2
SGDX (0xa008) 4.0 BYTE (0xa00b) 1.0 OUTPUT (0xa003) 8.0
ACOMP (0xa000) 8.0 VFE (0xa001) 8.0 VCOMP (0xa002) 8.0
SCR (0xa004) 8.0 SIFF (0xa011) 3.0 PSCAN (0xa05d) 0.1
ADEC (0x0134) 1.1 IR (0x0131) 2.0 AOI (0xa08c) 0.0
PIP (0xa04d) 1.0 AVLINK (0xdead) 10.11 USBLINK(0xa08e) 0.0
MSVD (0xa087) 0.0 FEBCU (0xa05e) 1.0 BM (0xa085) 0.0
BMI (0xa084) 0.0 DISP (0xa04d) 1.0

Found FLASH memory:
NOR ST M29DW160ET 2MB
BootCode , in FLASH, checksum is: 0xBABE7E83, which is correct

Diagnostics, in FLASH, checksum is: 0xBABED436, which is correct
Download , in FLASH, checksum is: 0xBABE7C57, which is correct
Application, on HDD , checksum is: 0xBABE5D76, which is correct

Found SAA7136

Be version = 52.07.02.10.PHILIPS ,D5.2, 52070210,5VC0635130300,
Basic Engine returned no OPU info

Hardware ID = 0x66

Software Boot Version = 1463

Software Download Version = 1463

Software Application Version = 1463

The DvIdNumber is: 0000000000

The slash version is = 11602
PASS
DS:>
Alignments & Test Procedures
Replacing the Digital Board
When the defective Digital Board is to be replaced with a new board, the following settings should be restored.
• Slash information (or slash version)

• IEEE Unique number (or DV ID)
• Hard Ware Diversity String (or Hardware ID)
The slash version, IEEE Unique number, and the Hardware ID are set at the end of the production line of the set.
The “Diversity String” tells the software during startup which hardware version is present.
In a new Digital Board, the non-volatile memory, the NVM, is an empty device. After replacement the set can only startup in
Diagnostic software mode because the Slash version and Hardware ID is not initialized properly.
By way of commands via the Diagnostic Software (DS) and hyperterminal connection to the PC, these factory settings must
be restored into the NVM.
5.8 Slash Version
The The slash version is stored with DS command 1217 followed by the slash version as parameter.
The slash versions used in DVDR3570H and DVDR3590H are as follows:
DVDR3570H/97 & DVDR3590H/97: 13601

DVDR3570H/75 & DVDR3590H/75 13602
Example:
DS:> 1217 12601
With DS command 1218 the slash version can be displayed
5.9 IEEE Unique Number
1. Note the serial number of the set example:

VN19 0650 100070
- VN = production center (VN….Szekesfehervar).
According to UAW-500: V=22 and N=14 (A = 1, B = 2, C =3, etc)
- 19 = change code (this is not used for this calculation)
- 06 = YEAR
- 50 = Production WEEK
- 100070 = Lot and SERIAL number
2. Calculate the unique number: this number always exists out of 10 hexadecimal numbers
3. First 5 numbers: First we calculate a decimal number according to formula below:
- 35828*YEAR + 676*WEEK + 26*V +N + 8788
- The figures are fixed, YEAR, WEEK and production center codes V, N are variables
- Example: 35828*06 + 676*50 + 26*22 + 14 + 8788 = 258142 (decimal)
- Then we translate this decimal number to a hexadecimal number.
- Example: 258142 = 3F05E (hex)
4. Last 5 numbers: The last 5 numbers exist out of the Lot and SERIAL number.
We have to translate the decimal number to the next 5 hexadecimal numbers:
Example: 100070 (decimal) = 186E6 (hex)
5. This IEEE Unique number (10-digit hexadecimal number) is stored with DS command 1207.
Example:
DS:>1207 3F05E186E6
120700: Test OK@
The set has now its original IEEE unique number.

With DS command 1208 the number can be displayed
5.10 Setting Hardware ID.
With DS command 1228 (command mode interface) the system settings including the Hardware “Diversity String” can be displayed
Note: An error in the Diversity string will render the set not able to boot-up and the Digital board will be defective.
Via th .
That stored “Diversity String” can be checked with the DS command 1229.
The Diversity strings used in DVDR3570H and DVDR3590H are as follows:
DVDR3570H/75/96/97 and DVDR3590H/75/97:

44424849E38840014C2B30365F3600006620070000020300000101004002000044564452323030312E303031020200000001
0300010002010000410000000000
Example:
DS:> 1226 44424849E3C840014C2B30365F3600006620070000020300000101004002000044564452323030312E303031020200000
0010300010002010000810000000000
122600:
Test OK @
6.
+5V 7
N/U 6
GND 5
N/U 4
RXD 3
SERVICE 2
TXD 1
HARD-DISK D5.2 Closed

(160GB)
(250GB)
Overall Block Diagram
O O
1 40
1 40 1 40 1 3V3D
2 3V3D
3 3V3D
4 3V3D
5 GND
6 12VD
7 GND
8 GND
9 5VD
10 GND
11 GND
12 5ND
Block Diagrams, Waveforms, Wiring Diagram.
1 GND
2 SCL_S
3 SDA_S Optical Digital Bd.
4 GND
18 GND 5 WSRO
Analog Bd. SDA_5V
17 SCL_S3V3 6 STBY SCL_5V
16 SDA_S3V3 7 DD_ON
15 GND 8 FAN_SPEED
1 14 WSRO 9 FAN_SPEED_FINE
1 GND 2 13 STBY 10 REGION_SEL_A_P90_DECON
Block Diagrams, Waveforms, Wiring Diagram
2 +5VSTBY 3 12 DD_ON 11 REGION_SEL_B_P91_DECON

3 +12VSTBY 4 11 FAN_A 12 GND
4 VNSTBY 5 10 FAN_B 13 8SC1
5 GND 9 REGIO N_SEL_A_P90_DECON HD_ON
6 14
REGIO N SEL_B_P91_DECO N
8 15 8SC2
7 GND IMUTE
8SC1/AFC 16
6 17 LOOP_THRU_ON
1 TXD 5 HD_ON YUV_ACTIVEN
8SC2/WSR1 18
2 SERVICE 4
3 RXD 3 IMUTE
4 N/U 2 LOOP_THRU_ON
5 GND 1 YUV_ACTIVEN
6 N/U
7 +5V
1 GND
3139 785 32801
I2C 0 n/u 2 D_BCLK

3 GND
4 D_WCLK
5 D_DATA0
6 GND
7 D_PCMCLK
8 GND
1 GND
2 D_BCLK AL1
DDR_CK
3 GND
I2S_OUT 4 D_WCLK
5 D_DATA0 AR1
6 GND
6.
MIU_A[1:22] 1 AUDIO1 L
7 D_MCLK
2 GND
8 GND
3 AUDIO1 R
PIO3_
4 GND
5 AUDIO2 L AL2
6 GND
7 AUDIO2 R
MIU_D[0:15] AR2
8 GND
9 N/U
24 AUDIO1 L 10 GND
23 GND 11 N/U
22 AUDIO1 R 12 GND
EN 95
21 GND 13 LR1_L
SPDIF_OUT 20 AUDIO2 L 14 GND
19 GND 15 LR1_R
18 AUDIO2 R 16 GND
17 GND 17 D_KILL
16 N/U 18 DAOUT
15 GND 19 GND
14 N/U 20 DAINCOAX(n/u)
13 GND 21 DAINOPT(n/u)
12 LR1_L 22 GND
11 GND 23 SIF
SPDIF1_IN 10 LR1_R 24 GND
9 GND
I2S_IN 8 D_KILL
7 DAOUT
6 GND
5 DAINCOAX9(n/u)
4 DAINOPT(n/u)
6 GND
3 GND
VIP_I2S_OUT 5 N/U
2 SIF
4 DTT_SEL
1 GND
3 GND
2 DTT_ON
9 AFCRI_FC 1 FBOUT
8 GND
7 AFCLI_FC
AR 6 GND 1 GND
5 2 N/U
CVBSFIN_FC SD0 3 DTT_SEL
4 GND 4 GND 1 D_UB
AL 3 CFIN_FC 5 DTT_ON 2 GND
2 GND 6 FBOUT 3 D_YG AL
1 YFIN_FC 4 GND
5 D_VR
CVBS 6 GND AR
7 D_C
8 GND
PHI 9 D_Y
10 GND
1 TPBn 11 D_CVBS
2 TPB 12 GND
3 GND 1 D_UB 13 SC1_CVBS
4 TPAn 2 GND 14 GND
5 TPA 3 D_YG 15 Vmux_6_out
6 GND 1 AINFR 4 GND 16 GND
2 GIND 5 D_VR 17 A_YG
3 AFINL 6 GND 18 GND
4 GND 7 D_C 19 A_UB
5 CVBSFIN 8 GND 20 GND
1 5VBUS 9 21 A_VR
6 GND AI12 D_Y
2 USBM AI13 10 22 GND
7 CFIN GND
3 USBP AI42 11 23 Vmux_5_out
8 GND AI23 D_CVBS
4 GND 12 24 GND
9 YFIN AI43 GND
13 SC1_CVBS
AI22 14 GND
AI11 15 Vmux_6_out
16 GND
17 A_YG
AI31 18 GND
AI41 19 A_UB
20 GND
AI21
21 A_VR
22 GND
AI33 23 Vmux_5_out
24 GND
Set Block Diagram 3139-249-40531-130-a3.pdf
2006-10-10
1115
+12VE 1
GND 2 24 GND
GND 3 23 TUN_CVBS
+5VE 4 1301 22 GND
Wiring Diagram
1 1 +12VE 21 A_VR
2 GND 20 GND
3 GND 19 A_UB
4 +5VE GND
18
17 A_YG
16 GND
15 Y/CVBS_TUN/DTT
14 GND
13 SC1_CVBS
12 GND
11 D_CVBS
10 GND
9 D_Y
39
1202 8 GND
7 D_C
8 GND 6 GND
7 D_MCLK D_VR
5
6 GND 4 GND
5 D_DATA0 3 D_YG
4 D_WCLK 2 GND
3 GND 1 D_UB
2 D_BCLK
1 GND
Block Diagrams, Waveforms, Wiring Diagram.
1603 1502
1507
AUDIO1_L 24
1101 GND 8
14 GND GND 23
D_BCLK 7
13 SEL KEY2 3 AUDIO1_R 22 1208
GND 14 GND 6
12 KEY 2 3 GND 21
NU 13 D_WCLK 5
11 KEY1 AUDIO2_L 20 1 AUDIO1_L
KEY2 12 D_DATA0 4 1210
10 TEMP_SENSE GND 19
40-pin IDE connector
KEY1 11 2 GND
GND 3
9 GND AUDIO2_R 18
3139 785 32800
TEMP_SENSE 1 GND 3 AUDIO1_R

10 D_MCLK 2
8 RC GND 17 2 4 GND
GND 9 GND 1 SCL_S3V3
7 STDBY_LEDN AUDIO3_L 16 3 5 AUDIO2_L
RC 8 SDA_S3V3
6 DISP_STBN GND 15 4 6 GND
NU 7 GND
5 DISP_CLK AUDIO3_R 14 5 WSRO 7 AUDIO2_R
CSN_F 6
4 DISP_DATA GND 13 6 8
SCK_F 5 STBY GND
3 GND LR1_L 12 7 DD_ON 9 AUDIO3_L
SDA_F 4 1600
2 GND
6.
VFD_CLK 11 8 FAN A 10 GND

GND 3 18
1 GND 1501 LR1_R 10 GND 9 11
40KHZ 2 FAN B AUDIO3_R
GND 9 SCL_S3V3 17 12
GND 1 1 AINFR 10 REGION SELECT A GND
2 D_KILL 8 SDA_S3V3 16 13
GND 11 REGION SELECT B LR1_L
3 AINFL 7 GND 15 14
4 GND DAOUT 12 GND GND
5 CVBSFIN_FC GND 6 WSRO 14 15
GND 13 8SC1�AFC LR1_R
6 5 STBY 13 16
7 CFIN_FC DAINCOAX 14 HD_ON GND
EN 96
8 GND 4 DD_ON 12 17
DAINOPT 15 8SC2�WSR1 D_KILL
9 YFIN_FC 3 FAN A 11
GND 16 IMUTE 18 DAOUT
FAN B 10
SIF 2 17 LOOP THRU ON 19 GND
1203 1 REGION SELECT A 9 20 DAINCOA�
GND 18 YUV ACTIVEN
REGION SELECT B 8 21 DAINOPT
YFIN_FC 9 GND
8 7 22 GND
GND
CFIN_FC 7 8SC1�A
FC 6 23
GND 6 SIF
5 HD_ON 5
CVBSFIN_FC 1209 24 GND
GND 4 8SC2�WR1 4
AINFL 3 1606 IMUTE 1 FBOUT
GND 2 3
AINFR 1 LOOP THRU ON 2 2 DTT/WU
1301 FBOUT 6 3 GND
YUV ACTIVE 1
DTT/WU 5 4 AUDIO_MUX2_SEL/DTT_SEL
1302 1 TPB0- GND 4 5 VIDEO_MUX3_SEL
2 TPB0+ AUDIO_MUX2_SEL/DTT_SEL 3
1 +5V 1703 6 GND
3 GND VIDEO_MUX3_SEL 2
2 -D
4 TPA0- GND 1 5VSTBY 1
3 +D 5 TPA0+ GND 2
4 ID 3V3STBY 3
6 GND
5 GND
1318 1211
1700 2 FAN_N
1 5VSTBY 1 FAN_P
5ND 12
2 GND
GND 11 3 3V3STBY
GND 10
5VD 9
GND 8 1304
GND 7
6 1 3V3D
12VD
5 2 3V3D
GND
4 3 3V3D
3V3D
3 4 3V3D
3V3D
2 5 GND
3V3D
1 6 12VD
3V3D
7 GND
8 GND
9 5VD
10 GND
11 GND
12 5ND
1313
1911 1 +12VH
GND 1 2 GND
SDA0 2 3 GND
GND 3
SCL0 4 +5VH
4
GND 5 1
ITU_OUT_CLK 6
GND 7
ITU_OUT_0 8
GND 9
ITU_OUT_1 10
GND 11
ITU_OUT_2 12
GND 13
ITU_OUT_3 14
+5V_HDMI 15
ITU_OUT_4 16
+3V3_HDMI 17
ITU_OUT_5 18
GND 19
ITU_OUT_06 20
GND 21
ITU_OUT_7 22
GND 23
FSCLK12_OUT 24
39
GND 25
SCK12_OUT 26
GND 27
SD_OUT 28
Set Wiring 3139-249-42051-132-a3.pdf
GND 29
SPDIF_OUT +12VH 1
30
GND 31 GND 2
WS12_OUT 32 GND 3
GND 33 +5VH 4
INT_HDMI 34
GND 35
HDMI_RSTn 36
GND 37
PSCAN_RSTn 38
2006-10-10
GND 39
GND 40
Block Diagrams, Waveforms, Wiring Diagram. 3139 785 32800 6. EN 97
Waveforms of Analog Board

F115 Tuner CVBS F117 Tuner SIF F124 CVBS F126 SY
F127 SC F132 Digital Out Black F133 Yout Green F135 Pr out Red
F136 Pb out blue F138 Audio R Out F139 Audio L Out F201 AIO D_BCLK
F202 AIO D_WCLK F203 AIO D_DATA0 F204 AIO D_MCLK

Waveforms of Digital Board

F101 (1100) F102 (1100) F303 (1303) F304 (1303) F500_D_B F500_D_U
F501_D__G F501_D_Y F502_D_R F502_D_V F503_D_C F504_D_Y
F505_D_CVBS F531_DAOUT F537_D_BCLK F538_D_WCLK F539_D_DATA0 F540_D_MCLK
F550 (1504 Top View) F551 (1504 Top View) F651 (1605) F652 (1605) F654 (1604) F655 (1604)
Waveforms of HDMI Board

F111 HDMI P_HSYNC F112 HDMI P_VSYNC
Test Points Overview for HDMI Board
HDMI Columbus Test Point Overview 3139-243-32736-132-a1.pdf 2007-05-08

Test Points Overview for Analog Board
716.3 Analog Test Point Overview_8_3139-243-36735-sh132-a1.pdf 2007-05-08

Test Points Overview for Digital Board
Digital Board Test Points overview_3139-243-36835_132_a4.eps 2007-07-17

Circuit Diagrams and PWB Layouts 3139 785 32800 7. EN 103
7. Circuit Diagrams and PWB Layouts
Analog: VIO/SPDIF OUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1101 E4
1102-A A2
F112 E4
F113 E4
1102-B C2 F114 E4
1102-C B2 F115 G2
1103 G1 F116 G2
from PS
1104 G1 F117 G2
For DTTM 5VSTBY 5V 3V3STBY 33V 1105-1 B14
1105-2 B13
F118 H2
F119 H2
1105-3 H14 F120 H2
7113_NJM2244 1105-4 F14 F121 H2
SW2 SW1 VOUT 1110 D2 F122 H2
A 1102-A
MSP-801V1-02-01-B NI FE LF H X CVBSSIN_DTT Vin3 A 1115 I7 F123 H2
2101 B13 F124 A13
1 L L RE_SY_IN Vin1 2102 B2 F125 B13
*
5VSTBY 5V 3V3STBY 33V 4101
F101 RE_SY_IN L H RE_CVBS_IN Vin2 2103 B2 F126 C13
Y
3 to I2C cct to Tuner to I2C cct to Tuner
2104 B5 F127 C13
Rear YC in 4
F102
RE_SC_IN 3102 SW2 SW1 3101 V0_CVBS F124
MSP-806V-10 NI 2105 B3 F128 C13
C 150R 75R 1%
7 2106 B7 F132 F13
CVBS out
BZX384-C12
BZX384-C12
2
2107 B7 F133 F13
100p
6 1105-2
6101
6103
3103 2108 C5 F134 F13
7 5 R 1%
YELLOW
3104
8SC2
1 00p
100p
2109 C9 F135 F13
5
75R 1%
47K
2104
2110 C4 F136 G13
3105
10n
F103
BZX384-C12
BZX384-C12
2101
B B 2118 C5 F137 H13
1u0
2102
2103
6102
6104
F125 2119 C11 F138 I13
5V 5101 2120 C2 F139 I13
GND 2121 D13 F140 H7
2105
1102-C 600R
MSP-801V1-02-01-B NI FE LF 2122 D13 F141 H7
2123 D9 F142 H7
47u 6.3V
GND 7101
NJM2244M 6 GND
2106
100n
2107
GND GND 1105-1 2124 D11 F143 H7
Φ V+
8
MSP-806V-10 NI
2126 E5 F144 H7
*
4102 SDIN
3-INPUT 1 2127 E5 F145 H8
GND 2108
VIDEO SW VO_SY 2128 E5 F146 H8
3106 F126
MSP-801V1-02-01-B NI FE LF
6
F104 RE_CVBS_IN 2110 1u0
1u0 1
3
VIN1
VIN2 VOUT
7
75R 1% F127
3
Y
C
2129 F11
2130 F12
F147 H8
F148 H8
5 4
C Rear CVBS in F105
2118 1u0
VIN3
3107 C 2131 F12 F149 H8
75R 1%
Y/C out 2132 G12 F150 H8

2120
100p
1102-B 7 2 2
from COM_0 YUV_ACTIVEN SW1 WSRO
310 8
from COM_1 DTT_SEL

4
SW2 150R 2136 G3 F151 H8
2109
100n
GND 2137 G3 F152 H9
BZX384-C12
BZX384-C12
8 5V
5
2138 H13
*
F128
311 7
311 8
311 9
6105
6107
1M0
1M0
1M0
5V 5V 2139 H13
100p
100p
4103
2119 2140 H4
GND GND GND 2141 H4
3109
BZX384-C12
BZX384-C12
100n GND 2142 H5
To/From DTTM
*
GND
*
2121
2122
4108
6106
6108
GND 75R 1% VO_SC 2143 I2
2149 I3
3120
7102
3121
27K
1K0
HLW6S-2C7 BC857BW 2150 I4
D GND 6
F106
3123 D 3101 A12
A_C 5 3102 A4
GND 4
F107
2123 100R GND 3103 B4
DTT_CVBS 3
LPR6520-P910F
F111 A_YG 3104 B3
GND 2 100n 3105 B4
6
GND 1 3129 2124
BC847BW 3106 C11
1110 Rear YUV in 5
F113 A_UB
7103
100R 100n 3107 C9
100R
3132
3133
27K
VIO_DTT 4
3108 C3
F114 3109 D12
3 3117 C5
F112 A_VR 3118 C5
2
E GND GND 5V E 3119 C6
3120 D9
100p
100p
1101 1
100p
3121 D10
3123 D10
GND
3129 D10
470R
3155
2126
212 7
2128
3132 E9
7104 2129 3133 E10
74LVC1G125GW 3155 E11
5 10n 3156 F10
3156
GND DAOUT
2
2130
3157 F11
4 3157 3158
from IOA 1K0 3158 F12
1 GREEN-BLUE-L_BLACK-RED-R
(AIO_0) EN 75R 8n2 120R 3159 F12
F F
13 1105-4
3 3160 G11
150R
3159
2131
390p
F132
11 3161 G3
Digital out - Black 3162 G5
F133
5VSTBY 3V3STBY 12
33V 4105 Y out - Green 3163 G6
F134 3164 G11
16
VO_Pr 3165 G4
3160
*
F135
75R 1%
14 3166 G11
Pr out - Red
31980183
3167 G5
3161
5108
3162
3163
10K
47K
10u
75R 1% F136
100p
2132
LATAM : USE TCSN9082PA26F(H) SIF
15
Pb out - Blue 3168 G6
to IOA (AIO_0) MSP-806V-10 NI 4101 A12
TCSM0601PD25F(H) 5109 4102 C11
4106
TCSN9082PA26F(H) 1103 SDA_S3V3
*
3165 4103 C12

G 1104 15 14
2K2
600R 7105
BSN20
from COM_0
3164 VO_Y
GND
G 4105 F11
*
5VSTBY 3V3STBY 4106 G11
4u7 50V
MT
2136
2137
50V
4107 G11
10n
13 F115 4107 75R 1%

VIDEO_OUT
12 4108 D10
NC AFT 5101 B6
11 F116 to IOA (AIO_0) VO_Pb
*
VT
10 F117 3166 5108 G3
3167
3168
10K
47K
*
SIF_OUT 2140
9 5109 G5
AUDIO_OUT
8 75R 1%
ER
R
AFT_OUT 22n 5110 H5

NE
7 F118
SDA 5110 5111 H3
UN
100p
2138
100p
2139
6 F119
SCL SCL_S3V3
TU
5 5112 H4
T
AS 600R from COM_0

NC
4 7106 6101 B3
3 F120 BSN20
H NC
B+
2
1
F121
F122
H 6102 B3
6103 B3
GND
22u 25V
BB+ 6104 B3
* 2141
* 2142
10n
5112 6105 C12

MT
5111 LHL08
6106 D13
F145
F148
F149
F143
F141
F142
F144
F146
F147
F150
F151
F152
5V
16 17 5V
F140
600R Bead 22u F137 WHITE-T_RED-B 6107 C13

F123 8 1105-3
6108 D13
100u 10V
2143
100n
2149
2150
Audio R out
10n
F138 7101 B6
9
HLW24S-2C7
ARout 7102 D10

7103 E9
VIO
Audio L out
1115
F139
ALout 10 7104 F10
MSP-806V-10 NI
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
7105 G5
I I 7106 H5
A_YG
GN D
G ND
G ND
G ND
G ND
G ND
G ND
GND
G ND
G ND
G ND
G ND
D_YG
A_VR
A_UB
SC1_CVBS
D_VR
D_UB
D_CVBS
TUN_CVBS
D_C
Y/CVBS_TUN/DTT
D_Y
Tuner in F101 A2
F102 A2
F103 B2
F104 C2
F105 C2
* Not used (Provision only) F106 D2
To/From LeCO+ Step 3139-243-36735-130-01-a2.pdf 2007-03-14 VIO/SPDIF OUT F107 D2
F111 D4
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Analog: AIO/DAC/SPDIF IN/OUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1202 B1
1203 I1
3293 E7
3294 E7
1205 D1 4201 C2
1208 E1 4202 C2
1209 F13 4205 A3
1210 G13 4206 C5
1211 H5 4207 C5
1213 C1 4210 F7
2201 B9 5201 C12
from PS 2202 B7 5202 C5
12VD 5NSTBY 5VD 5V 12VSTBY 2207 B7 5206 E12
A A 2211 C9
2212 C7
6201 C12
6202 D12
7230
4205 * MC78L05ACD-R2 2219 C9
2221 C7
6203 E12
6204 E12
BAS316
8 1 2222 C8 6206 E6
12VD IN OUT
2 6
6210 GND GND 2224 C9 6210 A3
3 7
*
100u 10V
GND GND 2225 C9 6215 E7
2281
4 5 5NSTBY 5VD 5V 12VSTBY
2280
2282
12VD
10n
1u0
NC NC
2233 C10 7202 B6
2234 C13 7203-1 C9
2235 C9 7203-2 E9
2236 C5 7204 C11
2240 C5 7205 C12
B B 2241 C3 7207 E11
1202
2201 2242 C3 7209 E12
GND 1 2243 C3 7211 F7
F201 3222
D_BCLK 2 SCLK to DAC 820p 2244 C3 7212-1 F6
22R
DAC 5VD
10u 25V
GND 3 2245 D9 7212-2 F5
F202 3230
100n
2207
2202
D_WCLK 4 LRCK to DAC 7202 16V 47u
F203 22R 3234 CS4344 2248 E7 7217 G1
D_DATA0 5 SDIN to DAC
GND 6
F204 3236
22R
1 Φ 5
2211 2249 E8
2250 E9
7219 H6
7222-1 I8
D_MCLK 7 MCLK to DAC from AIO_1 SDIN SDIN VQ
22R
GND 8
2 6
25V 10u 2252 E10 7222-2 I7
SCLK DEM FILT+ 100n 2219
HLW8S-2C7
from AIO_1 2253 E13 7228 H4
2241
2242
2243
2244
22p
22p
22p
22p
SCLK 2212 2221 3204 3212 3213 2255 E2 7230 A4
8
3 7 3
AIO_1 from AIO_1 LRCK LRCK AOUTL 3214 3216 5201
C 4 10
50V 4u7 680R 6K8 6K8
2
7203-1
1 ALout Audio-L out C 2256 E2 F201 B2
2224
3218
2222
820p
LM833D 2257 E2 F202 B2
27K
2n7
from AIO_1 MCLK MCLK AOUTR 100R 39R 600R
BZX384-C12
*
5V
* 5202 Bead 2258 E3 F203 B2
330p
4206 9
100K
3221
7205
6201
7204
2233
*
5V VA BC817-25W 2259 F6 F204 C2
1213 100n 2225 BC817-25W
*
600R
F251 4201 GND 2260 H6 F205 D2
*
100u 10V
1 DAOUT 2235
4207 2261 H2 F206 D2
3223
3224
2234
470p
2236
2240
100n
1K0
1K0
*
2 5VD
BZX384-C12
F252 4202
3 DAINOPT 47u 16V
* 2262 H3 F207 E2
6202
4
F253 5ND 2263 H3 F208 E2
5 3237 3238 3239 2264 I2 F209 E2
05FMN-BTRK-A 390R 15K 12K
2270 D9 F210 F2
2270 2271 E9 F211 F2
1205 3 2280 B3 F212 F2
BKILL
D 1 F248
100R 1% 2283
2245
56p D 2281 B3
2282 B4
F213 F2
F214 F2
100R 3246 2n2 2284
2 F249 2283 D4 F215 F2
820p
3248 1% 2n2 2284 D4 F216 F2
6 F205 5VD 2285 F3 F217 F2
Rear Audio In 4 F206
100R 1% 12VSTBY 2286 F3 F218 G2
2248 3240 3241 3242 3204 C8 F219 G2
8
3251 5 5206
100R
Audio-R out
5 F207 7203-27 3243 3244 3212 C8 F220 G2
50V 4u7 680R 6K8 6K8 ARout
6 3213 C8 F221 G2
3245
2249
2250
820p
LM833D
27K
2n7
LPR6520-E610F 3252 1% 100R 39R 600R
BZX384-C12
100p
100p
100p
100p
1K0
1K0
1K0
1K0
1K0
Bead
* 3214 C10 F222 G2
4
7209
100K
3247
330p
6203
7207
2252
BC817-25W 3216 C11 F223 H2
BC817-25W
3290
3291
3292
3293
3294
3218 C7 F224 H2
E GND
5ND
E
2255
2256
2257
2258
3221 C10 F225 H6
1K0
3249
3250
2253
470p
1K0
BZX384-C12
3222 B2 F226 H6
*
BZX384-C5V1
IMUTEn 5VSTBY 3253 3254 3255
6204
GND GND GND GND 3223 C10 F227 F13
1208
6215
F208 3257 6206 390R 15K 12K 3224 C11 F228 F13
AUDIO1_L 1 2271 3230 B2 F229 F13
GND 2 F209 12K 3258 IPFAIL 5VSTBY 3234 B2 F230 G13
3256
22K
AUDIO1_R 3 56p
GND 4 3259 12K BAT54A 3236 C2 F231 G13
F210
3237 D8 F232 G13
AUDIO2_L 5 5VSTBY * BKILL
To/From Leco+ Step

F211 4210
GND 6 F212 12K 3260 3238 D9 F233 H13
AUDIO2_R 7 3239 D9 F234 H13
8 12K PDTA124EU
GND F213 7211 3240 E8 F235 H13
AUDIO3_L 9
F F 3241 E8 F236 H13
2285
2286
3261
4K7
2n2
2n2
GND 10 F214 BKILL

6 3242 E8 F237 H13
from/to Digital Board
AUDIO3_R 11
*
1209
GND 12 F215 2 F227
3243 E10 F238 H13
100K
2259
3262
22n
LR1_L 13 LR1_L (nc) (NC) FBOUTSC1 1 FBOUT 3244 E11 F239 H13
F228
GND 14 F216 to PS DTT_ON 2 DTT/WU
3 1 3245 E7 F240 H13
LR1_R 15 LR1_R (nc) 3 GND
GND 16 7212-1 to IOV DTT_SEL F229
4 AUDIO_MUX2_SEL / DTT_SEL 3246 D3 F241 H13
F217 5 7212-2 PUMH1 3247 E10 F242 H13
D_KILL 17 PUMH1 5 VIDEO_MUX3_SEL
*
F218
DAOUT 18 DAOUT from Tuner
4
6 GND 3248 D3 F243 H13
3263
4K7
GND 19 3249 E10 F244 H13

F219 HLW6S-2C7
DAINCOAX 20
F220 DAINOPT COM_1 3250 E11 F245 H13
DAINOPT 21
GND
SIF
22
23
F221
SIF from Tuner
AUD_MUTING 3251 E3
3252 E3
F248 D2
F249 D2
G GND 24 5V G 3253 E8
3254 E9
F251 C1
F252 C1
HLW24S-2C7 to ana_tun SCL_S3V3
AIO_0 1210 3255 E9 F253 D1
to ana_tun SDA_S3V3 F230
To/From Leco+ Step

WSRO 1 GND 3256 F6 F254 I2
F231
3268
47R
4K7 2 SCL_S3V3 3257 E2 F255 H3

7217 * F222
F232
3 SDA_S3V3 3258 E2 F256 I3
OPT IN
1 3264
VS 4 GND 3259 F2 F257 I4
F233
F223 3269 3265 5 WSRO
3 12VSTBY 12VSTBY to PS (1500) STBY F234 3260 F2
OUT DAINOPT 6 STBY
180R to PS (1500) DD_ON 100R F235
7 DD_ON 3261 F5
2 FAN_A F236 3262 F7
GND 8 FAN_A
5V 12VSTBY F237
100n
2261
3273
1K8
10u 25V
JFJ2000-010111
F224
FAN_B
F238
9 FAN_B 3263 G5
2260
F255 (NC) REGION_SEL_A_P90_DECON 10 REGION_SEL_A

3276 3264 G12
H H
to FAN 1
1211 F239 REGION_SEL_B

(NC) REGION_SEL_B_P91_DECON 11
470R 1 F225 GND
3265 H12
FAN_P 12
2 F226 F240 3268 G2
3270
3K9
1u0 10V
FAN_N from ana_tun AFT 13 8SC1/AFC
3271
100K
F241
2263
3279
2262
3272
3269 H2
10K
10K
10n
to PS HD_ON 14 HD_ON
B2B-EH-A 7219 F242
3275 (NC) 8SC2
F243
15 8SC2/WSRI 3270 H7
BC327-25
IMUTEn 16 IMUTE 3271 H11
7228 560R (NC) LOOP_THRU_ON
F244
17 LOOP_THRU_ON
74HC1GU04GW F245 3272 H11
YUV_ACTIVEN 18 YUV_ACTIVEN
3273 H3
3277
3278
F254 F256 F257

3K3
2K2
*
5
2264 3280 3281

1203 2 2 1 4 HLW18S-2C7 3275 H7
SPDIF in 1
100n 100R NC
100R
3 6
COM_0 3276 H4
1
MTJ-032-13 3277 I7
3282
75R
5 2 3278 I8
100K
3283
7222-2 7222-1
FAN_A PUMH1 FAN_B
3284
I 10K
PUMH1
4
from COM_0
1 I 3279 H3
3280 I3
3281 I4
3282 I2
3283 I3
3284 I4
3139-243-36735-130-02-a2.pdf 2007-03-14 AIO/DAC/SPDIF IN/OUT 3290 E6
3291 E6
3292 E7
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Analog: Power Supply (PS)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1301 A14
1304 E1
7347 F8
7348 C11
1313 C14 7349-1 G8
1314 B3 7349-2 G7
1315 B3 7350 E11
1316 C3 7353 C7
1317 C1 7354 F12
1318 C5 7355 H8
(NC) 1319 E14 7356 E11
12VSTBY 5VSTBY 5V 5NSTBY 3V3STBY 3V3SW 33V 5V_DTTM 1320 E14 7357 G11
1321 D1 7359 G3
A 7342
SI2307BDS 2339 A 1322 G13
1323 C2
7360 E7
7361 H2
F338 PS_BE 1325 H13 7362 F7
12VSTBY 12VD 7341 100u 16V 1326 H14 7363 I2
SI2307BDS to
OPTICAL DRIVE 2337 B13 F301 B3
10K
3375
12VSTBYPS 12VE
12VSTBY 5VSTBY 5V 5NSTBY 3V3STBY 3V3SW 33V 5V_DTTM
12VD SW 3302 1301
2338 B11 F302 B3
3396
3377
4K7
2339 A13 F303 C4
4K7
F317
*
3308
10K
10K 1 12VE 2340 B7 F304 C2
2370
100n
3303
3378
F318
47K
3K3
100n 2 GND 2341 D13 F305 C2
F339 F319 3 GND
2342 D2 F306 C2
4309
4310
#
#
For non DTT models
For non DTT models
2371
* 4 5VE
2343 G8 F307 C2
B4B-EH-A
2340
PMEG1020EA 2345 C13 F308 D2
1n0
1314 F301
B B
3304
47K
12VSTBYPS 5VSTBYPS 5VE 2346 F13 F309 D2
2338
100n
4A T STBY 6311
SI2306DS 2347 I8 F310 D2
100u 10V
from COM_0 7340
7344-2 4322 2349 E13 F311 D2
3301
2337
10K
4311 # For non DTT models PUMH1 4323 2350 H5 F312 D2
4312 # 7344-1
For non DTT models
PUMH1
2351 H5 F313 E2
1315 F302 DD_ON 2352 E7 F314 F2
5VSTBYPS from COM_0 2353 H3 F315 F2
4A T
7343 2354 E8 F316 F2
PDTC124EU 2355 F7 F317 B13
2360 D11 F318 B13
4320
* 4322
* 2361 F10 F319 B13
4321
* 4323
* 7353
SI2306DS 2370 B10 F320 D13
C C
6310 to IOV,IOA,DAC_ADC,CU 5VSTBY
1316 F303 5310 5VD
1317 5VSTBY 2345
2371 B12 F321 D13
F304 2372 D10 F322 D13
12VSTBY 1 1A T 22u
PMEG1020EA
5VD SW
from PSU
t o D IG I b d
1318
GND 2 7348 100u 16V to 2373 D12 F323 F13
F305
3389
10K
5VSTBY 3 1323 1 5V_STBY SI2307BDS 2374 F10 F324 F13
3V3STBY 4 F306 2 GND 12VSTBYPS 12VH HARD DRIVE
F307 2375 F12 F325 F13
GND 5 T 4A 3 3V3STBY 3317 1313 3301 B13 F326 G13
3391
10K
220u 10V
F320
*
B5P-VH B3B-PH-K 3302 A12 F327 G13
2342
3315
10K
3V3STBY 10K 1 12VH
PS_STBY
2372
100n
3314
PS_DIG_STBY F321
47K
12VD 100n 2 GND 3303 B11 F328 H13
F322 3 GND 3304 B11 F329 H13
2373
* 4 5VH 3308 B12 F330 H13
4320
* PMEG1020EA B4B-EH-A 3313 D11 F331 H13
D
4321
* D
3313
3314 D11 F332 I13
47K
1321 5VSTBYPS 5VH PS_HDD
2360
100n
5311 6312 SI2306DS 3315 D12 F333 H2
6 F308 12VSTBY
100u 10V
12VSTBY to IOV,COM 7346 3316 D13 F334 D7
f ro m P S U
F309 4324
3316
2341
10u
10K
GND 5
4 F310 4325 3317 C12 F335 F8
IPFAIL IPFAIL to IOA
GND 3 5312 3323 F10 F338 A8
F311 F334
2 5NSTBY to IOA,PROG,DAC 3V3STBY 3V3D HD_ON 3324 F11 F339 B7
5V_DTTM
5NSTBY
F312 10u
VGNSTBY 1 VGNSTBY to PS_FP 7360 from COM_0 3325 F12
B6B-PH-K
STS9NF30L 3V3D SW 7350
3326 F13
PDTC124EU 3327 E12
2352
560u
3331
PS_ANA
3K9
3331 E8
3332 E8
3333 F8
E 1304
2349 to E 3334 F7
3341 H2
100R
3332
F313
DTTM
2354
3342 H2
1 0n
3V3D 1 3V3D 7356 100u 16V
TL431ACDBV
3V3D 2
SI2307BDS 3343 I1
NC
3V3D 3 12VSTBYPS PS_DTTM 3344 H3
4
REF
3V3D 4 3327
* 3345 H3
to DIGI bd
1320 1319
PSDIG_0
7362
GND 5 3346 I3
*
F323
NC
F314
3325
A
10K
12VD 6 12VD 10K 1 1 12VF
100p
3347 I3
2355
3334
3333
2374
100n
3323
F324
10K
10K
47K
GND 7 100n 2 2 GND
GND 8 3 3 3348 H4
2
*
F315 F325 GND
5VD 9 5VD 12VD 2375 4 4 5VF 3349 G3
GND 10 B4B-EH-A
5 5VSTBY 3350 H6
GND 11 3375 A8
F F
F316 B5B-EH-A
3324
47K
5ND 12 5ND 5V_DTTM
3377 A7
2361
100n
B12P-PH-K SI2306DS
7354 5VSTBY 3378 B8
PS_DIG
3326
2346
10 K
3382 G8
1u0
SI2306DS 3385 G7
5313 7347 F335
5VSTBY
3387 G8
5V DTT_ON
3389 C8
100n 50V
1m0 to FV,PROG,DAC,COM from COM_0
2343
3391 C8
7359 7357 3392 I8
MC34063AD PDTC124EU
10K 3393 I7
3349 8 DCOL SWC 1
12VD 5V SW 1322
3395 I8
3382 7 GND
100R 6
3396 A7
NC
to DTTM
G G
S Q 6 4309 B3
5 GND
F326 4310 B3
BAS316
3385 4 NC
2
6305
7349-1
R PUMH1
3 NC 4311 B3
3387
47K
4K7 2
5V
4314 * 7 IS 1 5VSTBY 1
NC
5VSTBY
4312 B3
3 F327 4313 H7
SWE 2 HLW7S-2C7 4314 G2
IPK 5 7349-2
* OSC TIMC 3
DTT_ON PUMH1 PS_DTT_5VSTBY 4320 C3
3344
3345
1R5
1R5
33V 4320 D3
from COM_0 4
BC857BW 4321 C3
REFERENCE *
100u 50V
7361 F333 5314

6 4321 D3
2350
390p
2351
3350
10K
12VD VCC REGULATOR 4322 B13

33u
4322 C4
H H
3341
22K
100u 16V
4323 B13
5 CIN_NEG GND 4 1325
*
2353
4323 C4
7 1326
DIROUT F328
6
4324 D12
3348 5 5 4325 D12
F329
3342
3K3
7355
VGNSTBY 4 4 5310 C4
47K F330
4313 SI2306DS 12VSTBY
F331
3 3 5311 D3
5NSTBY 5ND 5VSTBY 2 2
F332 5312 D3
3346
3347
3K9
3K9
1 1
5313 F4
10K
3392
10K
12VD to 33V 5ND SW B7B-PH-K-K B5B-PH-K 5314 H2
3393
100n
2347
47K
DTT_ON
3343 PS_FP 6304 I7
7363
BC847BW 6305 G5
6310 C3
I I 6311 B13
6312 D12
3395
1K0
7340 B12
BZX384-C6V8 7341 A11
* Not used (provision only)

12VD 7342 A8
6304
7343 C11
# For "specific models" 7344-1 B6
3139-243-36735-130-03-a2.pdf 2007-03-14 7344-2 B7
7346 D12
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Layout: Analog Top View
716.3 Analog Top View_7_3139-243-36735-sh132-a1.pdf 2007-05-09

Layout: Analog Bottom View
716.3 Analog Bottom View_8_3139-243-36735-sh132-a1.pdf 2007-05-09

Front: Display Part (DISP)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1100 D2
1101 G2
F130 J13
F131 J13
1102 J3 F132 K13
1165 K9 F133 K13
1166 K5 F134 C13
1167 K7 F135 C10
1168 K5 F140 F9
A A 1169 K8
1170 K6
F141 F9
F142 F9
1177 J12 F143 F9
1178 J14 F144 E9
2100 J9 I100 F6
2103 J7 I101 E6
2105 G5 I121 K9
2107 D3 I122 K8
12V 2116 F2 I127 K7
2144 C7 I128 K6
B B 2145 C7
2146 C8
I129 K6
I133 K5
VFD Sketch code is use for MG, for partlist 12NC is 272217100321 2147 C5 I134 F2
3113 2148 C8 I139 F2
VGNSTBY 7100 2149 C5
330R 3170 2150 D5
330R
3114
2144
3115
10K
47n
HUV-08SS65T
BC817-25 10R 2151 D6
6100 3116
7130
3171 2152 D10
12V 2153 D10
P17
P16
P15
P14
P13
P12
P11
P10
F2
F11
F12
F22
F21
NC
8G
7G
6G
5G
4G
3G
2G
1G
P9
P8
P7
P6
P5
P4
P3
P2
P1
BZX384-C6V8 3117 470R 50V 22u 3118 6103 10R 2154 D8
C C
7131 3172 2156 E8
33R BC847BW 2145 470R BZX384-C6V8 F134
32
2157 E8
31
3122
1
2
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
1K0
3173 10R 10R
470R
3119
2146
2159 G10
47n
2147
2148 3174 F135 2160 D10
10R
220n 3101 G5
2149
100n
BC807-25
7132 22u 50V 3175 3102 H6
10R
100u
5100 5101
+5VSTBY 3103 J7
1100 2150 220n 3104 J8
from ANA BOARD
3123 2151 10u

3106 J9
F2
GND 1
F100 +5VSTBY
10u 25V
+5VSTBY 2 6K8 1n0 3107 J7
100n
2152
2153
100n
2160
F101
3 +12VSTBY
D D
+12VSTBY F102 3108 J6
3125
1K0
VGNSTBY 4 VGNSTBY 3110 J5
5 7134 SCL_F
GND BC847BW
3128
3112 F2
10K
7103
13
43
4u7 50V
B5B-PH-K
2154
100p
3113 B7
Φ
2107
PS_FP VDD
14 3114 C6
VFD 1
15 3115 C8
3127 F144 5 2
SDA_F OSC
PT6315
3
16 3116 C7
82K 17 VFD{P(1:17),G(1:8)} 3117 C6
4
8 18
2156
100p
CLK 5 3118 C8
19
6101 7
6
20 3119 C8
I101 DIN 7
E E
3137 3121 F2
21
RECORD +5VSTBY
390R 6 SG
8
22 3122 C5
LTL816KETNN DOUT 9
7105 23 3123 D5
PDTC124EU SCN_F 10
+5VSTBY 9 24
RED LED STB 11 3125 D6
25
2157
100p
3129 12 3127 D9
10 26
1 13 3128 D7
10K 11 K 27
6108 BAS316
6107 BAS316
2 14
3129 E9
220R
3121
28
6102 15
F140 1 29 3130 J6
I100
6109 BAS316
3142 1 16
6110 BAS316
7107 F141 2
HDD 3134 I2
6111 BAS316
+5VSTBY
6112 BAS316
TSOP4836ZC1 2
F142 3 LED KS <1:16>
I139
6113 BAS316
470R 3 3137 E6
3 LTL-816TDK3 7113 F143 4 31
82K
82K
82K
82K
82K
82K
FP_CONTROL
6114 BAS316
VS 4 17
F BLUE LED PDTC124EU 32
F 3142 F6
6115 BAS316
I134 3112 18
OUT
1 42
1 19
33 3147 F13
41 34 3148 F13
1K0 2 20
40 GR SG 35
3149 F13
3147
3152
3148
3149
3150
3151
GND 3 21
39 36
2116
2
22u
6116 BAS316
4 22
37 3150 F14
6117 BAS316
23 3151 F14
38
6118 BAS316
24
3152 F14
GR <12:5> 3169 J3
VEE
VSS VGNSTBY
3170 B13
12
44
VGNSTBY
3171 C13
30
G G 3172 C13
F118
1101 +12VSTBY 12V 100n
2 3 3173 C9
HLW14S-2C7
3101
3174 C9
47K
2159
2105
100n
GND 14 7101 3175 C9

from/to Digital Board
40KHZ 13 SI2307BDS 5100 D5

1
GND 12 F114
SDA_F 11 F115 5101 D10
SDA_F
F116 6100 C5
3102
47K
SCL_F 10 SCL_F
SCN_F 9 F117 6101 E5
SCN_F
STDBY_LED 8 7102 6102 F5
F119
RC 7 6103 C8
GND 6
H TEMP_SENSE 5
KEY1 4
F120
F121
FP_CONTROL H 6107 F11
6108 F11
KEY2_3 3
F122 6109 F11
SEL_KEY2_3 2 PDTC124EU 6110 F11
GND 1 6111 F11
6112 F12
6113 F12
COMM_FP 6114 F12
6115 F12
6116 G12
I I 6117 G12
23226153
10K -T
3134
6118 G13
7100 B11
7101 G6
7102 H6
7103 D10
7105 E6
to STBY-PRINT
7107 F2
7113 F6
not used
1102 7130 C7
+5VSTBY
3107
J J
F126 3169 7131 C6
POWER 1 1177 1178
GND 2 4K7 2K2 7132 C7
CSS5004-7A01E B6B-PH-K
7134 D5
220R
3110
WH02D-1 1
3130
2103
F130
3108
10K
F100 D2
47K
10n
1
2 F131 2 F101 D2
220R
3103
3104
3106
STBY_FP 3
2100
10K
47K
10n
3 F102 D2
4 F132
I133
I129
I128
OPEN/CLOSE
4
6 5 F133 5
F114 G2
F115 G2
I127
I122
I121
6
EVQ11L05R
EVQ11L05R
EVQ11L05R
PREV
NEXT
F116 H2
1168
1166
1170
IEEE1394 F117 H2
EVQ11L05R
EVQ11L05R
EVQ11L05R
STOP
PLAY
REC
K K F118 G6
1169
1167
1165
to DIGITAL BOARD F119 H2

F120 H2
* OPTIONS F121 H2
Front 717.4 Circuit 3139-243-36954-130-01-a2.pdf 2007-03-14 F122 H2
F126 J3
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Front: Front Connector Part (FC)
1 2 3 4 5 6 7 8 9 1200-1 B1
1200-2 B1
1200-3 C1
1203 E9
2200 C5
2205 C6
3200 B5
3202 B5
3205 C3
A A 3209 B5
3210 B6
3211 B6
2
3212 B6
3213 B6
6205 4201 C2
4202 C2
3
DF3A6.8
4203 C2
5201 B2
5202 B2
CINCH 6205 A2
1
LPV8529-0100F F206 3209

2 F200 D8
B CVBS 1200-1 YELLOW
1
F207 5201 3202
1R0
3210 3211
B F201 D8
F202 D8
3
1K0 220R 10K 1K8 F205 E8
AL/MONO 1200-2
WHITE 4
5
F208 5202 3200 3212 3213 F206 B2
F207 B2
LPV8529-0100F 10K 1K8
1K0 220R F208 B2
6 F209 C1
7
AR 1200-3 RED
8
2200
2205
3205
10n
10n
75R
LPV8529-0100F
C C
F209
4201
AV_GND AV_GND AV_GND
4202
AV_GND
4203
TO DIGITAL BOARD
D D
HLW9S-2C7
F200
9 AFCRI_FC
F201 8 GND
7 AFCLI_FC
F202 6 GND
5 CVBSFIN_FC
4 GND
3 CFIN_FC
2 GND
1 YFIN_FC
1203
F205
AV_FP
E E
AV_GND
Front 717.4 Circuit 3139-243-36954-130-02-a3.pdf 2007-03-14
1 2 3 4 5 6 7 8 9
Layout: Display / Front Connector (Top View)
Front Display Bd Top View 717.3_3139_243_36944_sh130_a1.pdf 2007-05-09
Layout: Display / Front Connector (Bottom View)
Front Display Bd Bottom View 717.3_3139_243_36944_sh130_a1.pdf 2007-06-01

Front: Standby (STBY) Layout: Standby (STBY) (Top View) Layout: Standby (STBY) (Bottom View)
1301 B2 1302 B4 2302 B3 4301 B3 5301 B3 F303 B2 F304 B2 F305 B4
1 2 3 4
A A
from Front Board
4301
1301
POWER 1 5301 F305
B GND 2
F303
2u2
B
2
WH02D-1 F304
EVQ11L05R
POWER
not used
1302
2302
4n7
not used
1
C C
GND
Front Standby Top_3139-243-36934-132-a1.pdf 2007-05-10

Front Standby Bot_3139-243-36934-132-a1.pdf 2007-05-10
1 2 3 4
LecoPlus INIT Layout: LecoPlus INIT (Top View) Layout: LecoPlus INIT (Bottom View)
1400 B1 F400 B2 F401 B2 F402 B2 F403 C2 F404 C2
1 2 3
A A
B B
1400
LECO PLUS INIT Top_3139-243-37094-132-a1.pdf 2007-05-10 LECO PLUS INIT Bot_3139-243-37094-132-a1.pdf 2007-05-10
1 F400
2 F401
3 F402
4
5 F403
6
7 F404
S7B-PH-K
C C
1 2 3
Digital: LeCoplus (LECO)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1100 G4
2100 A4
4118 D8
5100 E6
2101 A4 5101 F4
2102 G5 5102 F6
2103 G4 5103 F6
2104 E6 5105 G6
2105 E6 5106 I7
DDR_VREF +3V3 +1V2 +VDDR MIU_CSN(3:0)
MIU_RDY 7100-2 IDE0_DD(15:0) 2106 E6 5107 I7
PNX7350E/C1
2107 E6 5108 G7
MIU_D(15:0)
B1
Φ A4 MIU_CSN(0) MIU_A(22:0) 2108 E7 7100-1 A2
{DDR_DQM(1:0),DDR_DQS(1:0),DDR_RAS,DDR_CAS} RDY MIU 0
B4 MIU_CSN(1)
{IDE0_CS(1:0),IDE0_DIOW,IDE0_DIOR,IDE0_IORDY,IDE0_DMACK,IDE0_DA(2:0),IDE0_DMARQ} 2109 E7 7100-2 A8
1
MIU_D(0) G1
0
CSN
2
C4 MIU_CSN(2) 2110 E7 7100-3 A11
MIU_D(1) G3 D4 MIU_CSN(3) 2111 E7 7100-4 C6
DDR_D(15:0) 1 3
A MIU_D(2) F1
F3
2
D11 A 2112 E7 7100-5 E2
*
MIU_D(3) MIU_A(0)
2100
MIU_D(4) E1
3 0
A10 MIU_A(1)
{IDE1_CS(1:0),IDE1_DIOW,IDE1_DIOR,IDE1_IORDY,IDE1_DMACK,IDE1_DA(2:0),IDE1_DMARQ} 2113 F5 7100-6 E11
PNX_VDDR 4 1
DDR_VREF +3V3 +1V2 +VDDR MIU_D(5) E3 B10 MIU_A(2) 7100-3 2120 F5 7100-7 I3
100n DDR_BA(1:0) 5 2
DDR_VREF MIU_D(6) D1
6 3
C10 MIU_A(3) PNX7350E/C1
IDE1_DD(15:0)
2121 F5 7100-8 I11
7100-1
PNX7350E/C1 * 2101
MIU_D(7)
MIU_D(8)
C1
G2
7
8
DATA<0:15>
4
5
D10
A9
MIU_A(4)
MIU_A(5) IDE0 Φ IDE1
2122 F6
2123 F7
F101 G4
F102 G4
DDR_A(13:0)
Φ AB10
100n {DDR_CK,DDR_CKB,DDR_CKE,DDR_WE}
MIU_D(9)
MIU_D(10)
G4
F2
9 6
B9
C9
MIU_A(6)
MIU_A(7)
IDE0_CS(0)
IDE0_CS(1)
R3
R4
0
CS CS
0
AB4
AA4
IDE1_CS(0)
IDE1_CS(1) 2124 G6 F103 E7
Y6 DDR DDR_VREF
33R 3112 DDR_BA(0) MIU_D(11) F4
10 7
D9 MIU_A(8)
1 1 2125 G6 F104 F5
1V2A_DDR_DLL 1 11 8
W6
2
VDD_DLL_CLEAN
0
AB14 MIU_D(12) E2
12 9
A8 MIU_A(9) IDE0_DIOW N3
DIOW DIOW
Y4 IDE1_DIOW 2126 G7 F105 F7
BANK AA14 33R 3113 DDR_BA(1) MIU_D(13) E4 B8 MIU_A(10) 2127 H7 F106 G7
1 13 10
DDR_D(0) 3100-4 33R AA6 MIU_D(14) D2 C8 MIU_A(11) IDE0_DIOR N4 AA1 IDE1_DIOR
0 14 ADDR<0:22> 11 DIOR DIOR 2128 H7 F107 G8
DDR_D(1) 3100-3 33R AB6 MIU_D(15) C2 D8 MIU_A(12)
1 15 12 2129 H7 F108 H7
B B
DDR_D(2) 3100-2 33R AA7 AA15 33R 3114-4 DDR_A(0) A7 MIU_A(13) IDE0_IORDY P1 AA2 IDE1_IORDY
2 0 13 IORDY IORDY 2130 H7 F109 I8
DDR_D(3) 3100-1 33R AB7 AB16 33R 3114-3 DDR_A(1) A1 B7 MIU_A(14)
3 1 MIU_OEN OEN 14
DDR_D(4) 3101-4 33R AA8
4 2
AA16 33R 3114-2 DDR_A(2)
15
C7 MIU_A(15) IDE0_DMACK N2
DMACK DMACK
AB1 IDE1_DMACK 2131 H7 F110 I8
DDR_D(5) 3101-3 33R AB8 AB17 33R 3114-1 DDR_A(3) B2 D7 MIU_A(16) 2132 H7 F112 G5
5 3 MIU_WEN WEN 16 IDE1_DA(0)
DDR_D(6) 3101-2 33R AA9 W16 33R 3144 DDR_A(4) A6 MIU_A(17) IDE0_DA(0) P4 AA3
6 4 17 0 0 2133 H7 F115 B7
DDR_D(7) 3101-1 33R AB9 Y16 33R 3145 DDR_A(5) F115 A2 B6 MIU_A(18) IDE0_DA(1) P3 AB2 IDE1_DA(1)
DDR_D(8) 3102-4 33R W10
7
DATA<0:15>
5
W15 33R 3146 DDR_A(6)
MIU_CLK CLK 18
C6 MIU_A(19) IDE0_DA(2) R1
1 DA DA 1
AB3 IDE1_DA(2) 2134 H7 F120 E11
8 6 19 2 2 2135 I7 F121 F11
DDR_D(9) 3102-3 33R Y10 Y15 33R 3147 DDR_A(7) D3 D6 MIU_A(20)
9 7 NC UB 20
DDR_D(10) 3102-2 33R W9
10
ADDR<0:13>
8
W14 33R 3148 DDR_A(8)
21
A5 MIU_A(21) IDE0_DMARQ P2
DMARQ DMARQ
Y3 IDE1_DMARQ 2136 I7 F122 F11
DDR_D(11) 3102-1 33R Y9 Y14 33R 3149 DDR_A(9) C3 B5 MIU_A(22) 2138 I7 F123 F11
11 9 NC LB 22 IDE1_DD(0)
DDR_D(12) 3103-4 33R W8 AB15 33R 3150 DDR_A(10) IDE0_DD(0) N1 Y2
12 10 0 0 IDE1_DD(1)
2139 I7 F124 F11
DDR_D(13) 3103-3 33R Y8 W13 33R 3151 DDR_A(11) B3 IDE0_DD(1) M3 W4
DDR_D(14) 3103-2 33R W7
13 11
Y13 33R 3117 DDR_A(12)
NC LBA
IDE0_DD(2) M1
1 1
W2 IDE1_DD(2) 2140 G1 F125 F11
14 12 2 2 2141 H7 F126 F11
DDR_D(15) 3103-1 33R Y7 AA11 A3 IDE0_DD(3) L2 V4 IDE1_DD(3)
15 13 NC BAA 3 3
C C 3100-1 B1 F127 F11
DDR_CK IDE0_DD(4) L4 V2 IDE1_DD(4)
4 4 IDE1_DD(5)
DDR_DQM(0) 3104 22R Y11 AB12 IDE0_DD(5) K2 U3 3100-2 B1 F128 F11
0 CK 5 5 IDE1_DD(6)
100R
Y12 DQM K4 U1
3119
DDR_DQM(1) 3105 22R IDE0_DD(6)
1 6 6 3100-3 B1 F129 F11
AB11 IDE0_DD(7) J2 DD<0:15> T2 IDE1_DD(7)
CKB 7 7 3100-4 B1 F130 F11
DDR_DQS(0) 3106
DDR_DQS(1) 3107
22R
22R
AA10
W11
0
1
DQS
CKE
W12 33R 3120
* DDR_CKB
DDR_CKE
IDE0_DD(8)
IDE0_DD(9)
J3
J1
8
9
DD<0:15>
8
9
T1
T3
IDE1_DD(8)
IDE1_DD(9) 3101-1 B1 F131 G11
7100-4 IDE0_DD(10) K3
10 10
U2 IDE1_DD(10) 3101-2 B1 F132 G11
AA13 AA12 PNX7350E/C1 K1 V1 IDE1_DD(11) 3101-3 B1
DDR_RAS 3108 33R RAS WE 33R 3121 DDR_WE IDE0_DD(11)
11 11 F133 G11
DDR_CAS 3109 33R AB13 R19 Φ Y19 PNX_PIO16_EJTAG_DSU_CLK 4115 TUNER_ON
IDE0_DD(12)
IDE0_DD(13)
L3
L1
12 12
V3
W1
IDE1_DD(12)
IDE1_DD(13)
3101-4 B1 F134 G11
CAS PNX_PIO0_IDE1_RSTN
R21
0 PIO 16
AB20 PNX_PIO17_EJTAG_DSU_TPC1 4116 DTT_RESETN IDE0_DD(14) M2
13 13
W3 IDE1_DD(14) 3102-1 C1 F135 G11
PNX_PIO1_BOOT_1 1 17 14 14 IDE1_DD(15) 3102-2 C1 F136 G11
D5 AA20 4117 PNX_PIO8_HD_ON IDE0_DD(15) M4 Y1
4K7
4K7
PNX_PIO18_EJTAG_PCST0(0)
PNX_PIO2_ASP_RST 2 18 15 15
+3V3
3133 10K
PNX_PIO3_MIU_A23
C5
3 19
Y20 PNX_PIO19_EJTAG_PCST0(1) 4118 VIDEO_MUX3_SEL 3102-3 B1 F137 G11
T4 AB21 SCL_ABT 3102-4 B1 F138 G11
PNX_PIO4_ASP_IRQ 4 20
D R20 AB22
D
SDA_ABT
PNX_PIO5_VIP_IRQN 5 21 SDA_ABT 3103-1 C1 F139 G11
PNX_PIO6_IDE1_IRQ U4 AA21 PNX_PIO22_EJTAG_PCST1(1) F146
3103-2 C1 F140 H11
3110
3111
6 22
E20 AA22 PNX_PIO23_EJTAG_PCST1(2) F147
PNX_PIO7_SPDIF2_IN 7 PIO<0:15> 23 3103-3 C1 F141 H11
A17 Y21 PNX_PIO24_1394_PD
*
8 24
HTS_IRQN
4105
PNX_PIO9_USB_OC
C11
9
PIO<16:31>
25
Y22 PNX_PIO25_HDMI_RSTN 3103-4 C1 F142 H11
(HTS) E8 W21 PNX_PIO26_1394_RSTN 3104 C1 F143 H11
PNX_PIO10_HDMI_IRQ 10 26
W5 W22
PNX_PIO11_IDE0_RSTN 11 27
PNX_PIO27_DD_ON
3105 C1 F144 H11
HDMI_CEC_INTn 4106 Y5 F20 PNX_PIO28_IDE0_EN 4107
{PHY_D(7:0),PHY_CTL(1:0),PHY_LREQ} PNX_PIO12_IDE0_IRQ
W17
12 28
F19 PNX_PIO29_IR_OUT
PSCAN_RESETN
3106 C1 F146 D8
PNX_PIO13_DTT_RTS_1 13 29 3107 C1 F147 D8
PNX_PIO8_HD_ON 4108 W18 R22 PNX_PIO30_DKILLN
{PNX_SCL(0),PNX_SDA(0),PNX_SCL(1),PNX_SDA(1)} PNX_PIO14_DTT_CTS_1 14 30 {PNX_ITU0_IN(7:0),ITU0_IN_VS,ITU0_IN_HS,ITU0_IN_VALID,ITU0_IN_CLK}
PNX_PIO15_VIP_RSTN
G19
15 31
B15 PNX_PIO31_USB_VBUSON
from VIP 3108 C1 c100 H5
3109 D1
+3V3
3110 D1
7100-6
+1V2 3111 D2
E 5100
BLM31 F103
PNX7350E/C1
AV Φ E 3112 B4
3113 B4
3122
3123
3124
3125
1V2_CORE
7100-5 50R ITU0_IN ANA_VIDEO 3114-1 B4
100n
100n
100n
100n
100n
100n
100n
100n
PNX7350E/C1 ITU0_IN_VS G21
OUT 3114-2 B4
22u 16V
VS
G20 E19 4100
2104
ITU0_IN_HS
HS ANA_VREF 3114-3 B4
CTRL Φ C22 1K2 3135
2K7
2K7
2K7
2K7
RSET
2105
2106
2107
2108
2109
2110
2111
2112
ITU0_IN_VALID F120 F22 3114-4 B4
VAL
I2C FRONT END 0
D20 12R 3136 3117 C4
PNX_SDA(0) 4101 D19 J4 ITU0_IN_CLK F121 F21 IDUMP C20 12R 3137 3118 H11
SDA 25 NC CLK 1
PNX_SCL(0) 4102 C19 0 J5
SCL 26 NC 5101 5102 3119 C4
H1 BLM18P PNX_ITU0_IN(0) F122 J21 D22 3V3_VDAC_VDD0
PNX_SDA(1) 4103 W19
27
H2
NC +VDDR F104 +1V2 BLM18P F105
PNX_ITU0_IN(1) F123 J20
0 0
B20 3120 C4
SDA FE_DD<25:31> 28 NC 1V2A_PLL 1 AVDD 1
PNX_SCL(1) 4104 W20 1 H3 PNX_ITU0_IN(2) F124 J19 A20 3121 C4
SCL 29 NC 60R PNX_VDDR 60R 2 2 3V3_VDAC_VDD1
F F
100n
100n
100n
H4 PNX_ITU0_IN(3) F125 H22 3122 E2

10u 25V
10u 25V
30 NC 3
D14 H5 F126 H21 ITU<0:7> B21
2113
2122
USB_DM DM USB 31 NC PNX_ITU0_IN(4)

4 C|CVBS PNX_C 3123 E2
3V3_USB_VDD B14 PNX_ITU0_IN(5) F127 H20
USB_DP DP 5 3124 E2
2120
2121
2123
* 1K5
3126
3127
B13
12K 1%C15
RPU
RREF
BM_IRQ
HOST
BUFFER
G5
F5
NC
NC
PNX_ITU0_IN(6)
PNX_ITU0_IN(7)
F128
F129
H19
G22
6
7
Y|CVBS
A21
PNX_Y 3125 E2
3126 F1
E15 D21
USB_ID ID CVBS|Y PNX_CVBS
E14 E5 3127 F2
USB_VBUS VBUS
BMI
BE_BUSY
E6
NC 5103 F130 K19 ITU1_IN C21
XFER_REQ NC BLM18P 5108 F106
ITU1_IN_VALID
VAL B|U PNX_B_U 3128 G1
C14
+1V2
VSSA_TERM 3129 H7
ITU1_IN_CLK F131 J22 B22
GENERAL 60R 60R 1V2A_DDR_DLL CLK G|Y|Y PNX_G_Y 3130 H11
100n
D15 R2
10u 25V
VSSA_REF FE_CP NC F112

2102 22p 3131 H11
XPNX
D12 F132 M19 A22

2124
2126
PNX_ITU1_IN(0)
47n
PLL_OUT NC 0 R|V|C PNX_R_V

D13
VDDA_3V3 F101
PNX_ITU1_IN(1) F133 L22
1
3132 G5
2125
B12 F134 L21 3133 D4

1100
PNX_ITU1_IN(2)
4M0
3V3_USB_VDD IN 2 ITU_OUT
G C13
VDDA_3V3DRIVER XTAL F102 2103 22p
PNX_ITU1_IN(3) F135 L20
3 VAL
T21
G 3134 H11
XPNX
*
A12 PNX_ITU1_IN(4) F136 L19 ITU<0:7>
2140
A14
OUT
PNX_ITU1_IN(5) F137 K22
4
T22 3138-2 47R ITU_OUT_CLK
3135 E13
GNDA +3V3 5 CLK 3136 F13
B11 PNX_ITU1_IN(6) F138 K21
100n SYS_RESET 5105 6
A11 PNX_ITU1_IN(7) F139 K20 T19 3138-1 47R ITU_OUT_VSYNC 3137 F13
3128 C16 IEEE1394-PHY RESET 3132 +3V3 BLM31 F107 7 VS
T20 3138-3 47R
+3V3 PHY_CLK SYSCLK 4K7 3V3_PAD HS
ITU_OUT_HSYNC 3138-1 G13
A13
10K AVDD_CLK 1V2A_PLL PNX_SYS_RESETN 50R {PNX_ITU1_IN(7:0),ITU1_IN_VALID,ITU1_IN_CLK} 3138-2 G13
100n
100n
100n
100n
100n
100n
A15 V19 3139-4 47R PNX_ITU_OUT(0)

22u 16V
PHY_LKON
A16
LINKON
C12
PNX_RESETN 0
V20 3139-3 47R 3138-3 G13
2127
PNX_ITU_OUT(1)
PHY_LPS LPS AVSS_CLK 1 3139-2 47R 3139-1 H13
PHY_LREQ B16 c100 V21 PNX_ITU_OUT(2)
LREQ 2
2128
2129
2130
2132
2131
2141
TCK
AB18 PNX_TCK
3
V22 3139-1 47R PNX_ITU_OUT(3) 3139-2 H13
PHY_CTL(0) D16
0
JTAG TRST
AA19 PNX_TRST
AUDIO_IN ITU<0:7>
4
U19 3140-4 47R PNX_ITU_OUT(4) 3139-3 H13
PHY_CTL(1) B17 CTL Y18 PNX_TMS +3V3 F140 3118 47R M22 U20 3140-3 47R PNX_ITU_OUT(5)
1 UART TMS
AB19 PNX_TDI
XPNX PNX_SD0_IN
F141 3130 47R M21
SD 5
U21 3140-2 47R PNX_ITU_OUT(6)
3139-4 G13
TDI 3129 F108 PNX_WS0_IN WS 0 6 3140-1 H13
H H
PHY_D(0) C17 AA18 PNX_TDO 3V3_VDAC_VDD0 F142 47R M20 U22 3140-1 47R PNX_ITU_OUT(7)
0 TDO PNX_SCK0_IN SCK 7 3140-2 H13
PHY_D(1) D17 33R 3131
1
100n
PHY_D(2) A18 AB5 PNX_UART_TXD(0) N22 3140-3 H13

AUDIO
10u 25V
2 TXD {PNX_TCK,PNX_TRST,PNX_TMS,PNX_TDI,PNX_TDO} NC SD
B18 0 AA5 N21 P22 3140-4 H13
2133
PHY_D(3) PNX_UART_RXD(0)
3 RXD NC WS 1 SD0 PNX_SD_OUT
PHY_D(4) C18
4
D<0:7>
NC
N20
SCK
OUT WS
P21
PNX_WS_OUT 3144 B4
2134
PHY_D(5) D18 Y17 PNX_UART_TXD(1) P20 PNX_SCK_OUT

PHY_D(6) A19
5
1
TXD
AA17 PNX_UART_RXD(1) F143 3134 47R N19
SCK 3145 B4
6 RXD PNX_FSCLK_IN FSCLKE 3146 B4
PHY_D(7) B19 {PNX_UART_TXD(1:0),PNX_UART_RXD(1:0)} F144 E21 P19 PNX_FSCLK_OUT
7 5106 PNX_SPDIF1_IN SPDIF1 FSCLK
BLM18P F109 SPDIF
E22 PNX_SPDIF_OUT 3147 B4
3V3_VDAC_VDD1 3148 C4
1V2_CORE PNX_VDDR 3V3_PAD 60R 3149 C4
100n
10u 25V
3150 C4
2135
{PNX_ITU_OUT(7:0),ITU_OUT_VALID,ITU_OUT_CLK,ITU_OUT_VSYNC,ITU_OUT_HSYNC}
3151 C4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
2136
4100 E13
7100-7
V15
V8
V7
V6
V5
U18
U5
T18
T5
R18
R5
4101 F1
N18
V13
V10
P18
E13
V14
K18
E12
E10
J18
I I
PNX7350E/C1
N5
P5
K5
E9
V9
L5
5107 4102 F1
1V2 2V5 3V3 BLM31 F110 4103 F1
NC
3V3_USB_VDD
SUPPLY
NC
4104 F1
Φ
GND GND GND GND GND GND 50R
100n
7100-8 4105 D4
NC
10u 25V
PNX7350E/C1 4106 D4
2138
E11
L18
M5
M18
V11
V12
J9
J10
J11
J12
J13
J14
K9
K10
K11
K12
K13
K14
L9
L10
L11
L12
L13
L14
M9
M10
M11
M12
M13
M14
N9
N10
N11
N12
N13
N14
P14
P13
P12
P11
P10
P9
4107 D8
* Not used (Provision only)
G18
H18
E16
E17
E18
V18
V17
V16
2139
F18
E7
4108 E4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
4115 D8
3139-243-36835_130-01_a2.eps 2007-07-17 4116 D8
4117 D8
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Digital: FLASH+SDRAM (MEM)
1 2 3 4 5 6 7 8 9 10 11 12 13 2200 A2
2201 A3
2202 A6
2203 A7
2206 A3
2207 A7
2209 B2
+VDDR
2210 A6
+VDDR +3V3
5200 2212 B3
BLM31 F200 2213 B7
DDR_VDD 2215 B2
50R 2216 B6
2218 B3
A A
{DDR_A(12:0),DDR_A(13),DDR_BA(1:0),DDR_DQM(1:0),DDR_DQS(1:0),DDR_CK,DDR_CKB,DDR_CKE,DDR_WE,DDR_CAS,DDR_RAS} DDR_VDD
2219 B7
DDR_VDD 2202 2203 +VDDR +3V3 2221 B2
2222 B6
2200 2201 100u 6.3V 100n 2224 B3
2207
100u 6.3V 100n
2225 B7
2206 2210 100n 2227 D1
2213 2228 D4
2209 100n 100n 2229 D1
2212 2216 100n 2230 D4
100n 2219
2215 100n 100n
2233 F5
2218 2222 100n 2234 F11
2236 I5
B 100n
2221 100n 100n
2225
B 3202 D1
2224 100n 3203 C3
100n
100n
3206 D5
3207 C7
7200 7201
EDD5108AFTA-5B 3216 H1
18
33
18
33
15
15
55
61
55
61
EDD5108AFTA-5B
1
9
9 3217 H1
VDD VDDQ VDD VDDQ
DDR_A(0) 29 2 DDR_D(0) DDR_A(0) 29 2 DDR_D(8) 3218 H2
0 0 0 0
DDR_A(1) 30
1 1
5 DDR_D(1) DDR_A(1) 30
1 1
5 DDR_D(9) 3219 H5
DDR_A(2)
DDR_A(3)
31
32
2 Φ 2
8
11
DDR_D(2)
DDR_D(3)
DDR_A(2)
DDR_A(3)
31
32
2 Φ 2
8
11
DDR_D(10)
DDR_D(11)
3220 H2
3 DDR 3 3 DDR 3 3223 E1
DDR_A(4) 35 D 56 DDR_D(4) DDR_A(4) 35 D 56 DDR_D(12)
DDR_A(5) 36
4
SDRAM 4
59 DDR_D(5) DDR_A(5) 36
4
SDRAM 4
59 DDR_D(13) 3224 F1
C DDR_A(6)
DDR_A(7)
37
38
5
6
A
64Mx8
5
6
62
65
DDR_D(6)
DDR_D(7)
DDR_A(6)
DDR_A(7)
37
38
5
6
A
64Mx8
5
6
62
65
DDR_D(14)
DDR_D(15)
C 3225 D1
3226 D5
7 7 7 7
DDR_A(8) 39 DDR_A(8) 39 3227 H2
8 8
DDR_A(9) 40 DDR_A(9) 40
9 3203 DDR_DQS(0)
9 3228 H1
DDR_A(10) 28 51 DDR_A(10) 28 51 3207 DDR_DQS(1)
DDR_A(11) 41
10 DQS
DDR_A(11) 41
10 DQS 4200 E2
11 11 4201 E5
DDR_A(12) 42 DDR_A(12) 42
12 12
AP NC AP NC 4202 I1
4 NC 4 NC 4202 I5
DDR_VDD DDR_VDD
7 7
DDR_BA(0) DDR_BA(0)
4203 I1
26 10 NC 26 10 NC
DDR_BA(1) 27
0
BA 13 DDR_BA(1) 27
0
BA 13 4204 G12
1 NC 1 NC
14 NC 14 NC 4205 H12
16 16 4206 H12
2228
100n
2227
100n
NC NC
D DDR_DQM(0) 3202 47
DM
17
20
NC
NC
DDR_DQM(1) 3206 47
DM
17
20
NC
NC
D 4207 H12
DDR_VREF 4208 H12
DDR_VREF 49 NC 25 NC 49 NC 25 NC
3225 240R
VREF
43 3226 240R
VREF
43 4209 H12
NC NC
DDR_CKB 46 53 NC DDR_CKB 46 53 NC 4210 H12
CK CK
45 54 45 54 4211 H12
2229
100n
2230
100n
DDR_CK NC DDR_CK NC
CK CK
DDR_CKE 44 57 NC DDR_CKE 44 57 NC 4212 I13
CKE CKE
4200 24 60 NC 4201 24 60 NC
CS CS 4213 I13
DDR_RAS 23 63 NC DDR_RAS 23 63 NC
DDR_CAS 22
RAS
19 DDR_CAS 22
RAS
19 4214 I13
CAS NC CAS NC
DDR_WE 21 50 NC DDR_WE 21 50 NC 4215 I13
WE WE
VSSQ VSSQ
4216 I1
VSS VSS
4238 H1
34
48
66
12
52
58
64
34
48
66
12
52
58
64
4238 I1
E DDR_VDD
E 5200 A2
5201 G1
7200 B1
7201 B6
1K0 1%
{DDR_A(12),DDR_A(13),DDR_D(15:0),DDR_DQS(0),DDR_DQS(1)}
3223
7203 G10
7204 G4
F201
7XXX G7
DDR_VREF
F200 A3
F201 F1
1K0 1%
3224
F202 G1
F203 I1
F 3V3_MIU F F204 I1
F205 I1
3V3_MIU
F206 I1
2234 F207 I1
F208 G12
100n F209 H12
2233
100n
{MIU_D(15:0), MIU_A(22:0), MIU_CLK, MIU_OEN, MIU_WEN, CSN(0), BYTEN}

F210 H12
3V3_MIU
F211 H12
*
7204 7206 7203
F212 H12
29
37
37
43
M29DW640D70N M29W160ET70N6F M29DW128F70NF
F213 H12
VDD
Φ
VCC
VCCQ
MIU_A(1) F250 31 1 F214 H12
MIU_A(1) 25 MIU_A(2) 26
0 DRAM 27 F215 H12
G 5201
MIU_A(2)
MIU_A(3)
24
23
0
1 EPROM 0
29
31
MIU_D(0)
MIU_D(1)
MIU_A(1)
MIU_A(2)
25
24
0 [FLASH] 0
29
31
MIU_D(0)
MIU_D(1)
MIU_A(3)
MIU_A(4)
F252 25
24
1
2
128M
[FLASH] NC
28
30
G F216 H11
BLM31 F202 2 8Mx8/4Mx16 1 1 2Mx8/1Mx16 1 3 F217 H11
3V3_MIU MIU_A(4) 22 33 MIU_D(2) MIU_A(3) 23 33 MIU_D(2) MIU_A(5) 23 55
+3V3 MIU_A(5) 21
3 2
35 MIU_D(3) MIU_A(4) 22
2 2
35 MIU_D(3) MIU_A(6) 22
4
56 F218 H11
50R 4 3 3 3 5 {PHI_D(7:0),NOR_RSTN,CSN(3),CSN(1)} F219 H11
MIU_A(6) 20 38 MIU_D(4) MIU_A(5) 21 38 MIU_D(4) MIU_A(7) 21
5 4 4 4 6
MIU_A(7) 19
6 5
40 MIU_D(5) MIU_A(6) 20
5 5
40 MIU_D(5) MIU_A(8) 20
7
F220 H11
MIU_A(8) 18 42 MIU_D(6) MIU_A(7) 19 42 MIU_D(6) MIU_A(9) 10 35 MIU_D(0) MIU_D(0) F208 4204 PHI_D(0) F221 H11
7 6 6 6 8 0
MIU_A(9) 8 44 MIU_D(7) MIU_A(8) 18 44 MIU_D(7) MIU_A(10) 9 37 MIU_D(1) MIU_D(1) F209 4205 PHI_D(1)
8 7 7 7 9 F222 I11
MIU_A(10) 7 D 30 MIU_D(8) MIU_A(9) 8 D 30 MIU_D(8) MIU_A(11) 8 39 MIU_D(2) MIU_D(2) F210 4206 PHI_D(2)
3V3_MIU
MIU_A(11) 6
9 8
32 MIU_D(9) MIU_A(10) 7
8 8
32 MIU_D(9) MIU_A(12) 7
10
41 MIU_D(3) MIU_D(3) F211 4207 PHI_D(3)
F223 I11
10 9 9 0 9 11
MIU_A(12) 5 0 34 MIU_D(10) MIU_A(11) 6 A 34 MIU_D(10) MIU_A(13) 6 ADR 44 MIU_D(4) MIU_D(4) F212 4208 PHI_D(4) F250 G9
11 A 10 10 2M-1 / 1M-1 10 12 DQ
MIU_A(13) 4
12
64M-1
11
36 MIU_D(11) MIU_A(12) 5
11 11
36 MIU_D(11) MIU_A(14) 5
13
46 MIU_D(5) MIU_D(5) F213 4209 PHI_D(5) F252 G9
MIU_A(14) 3 39 MIU_D(12) MIU_A(13) 4 39 MIU_D(12) MIU_A(15) 4 48 MIU_D(6) MIU_D(6) F214 4210 PHI_D(6) F253 I4
13 12 12 12 14
2 41 3 41 3 50 F215 4211
3216 4K7
MIU_A(15) MIU_D(13) MIU_A(14) MIU_D(13) MIU_A(16) MIU_D(7) MIU_D(7) PHI_D(7)

3228 4K7
3217 4K7
3220 4K7
3218
F254 I5
H H
4K7
14 13 13 13 15 7
1 43 2 43 54
3227
MIU_A(16) MIU_D(14) MIU_A(15) MIU_D(14) MIU_A(17)

4K7
MIU_A(17) 48
15 14
45 MIU_D(15) MIU_A(16) 1
14 14
45 MIU_D(15) MIU_A(18) 19
16
36 F216 MIU_D(8) F256 I10
16 15 15 15 17 8 F272 H9
* BYTEN
MIU_A(18)
MIU_A(19)
17
16
17
18
A-1
3V3_MIU
MIU_A(17)
MIU_A(18)
48
17
16
17
A-1
MIU_A(19)
MIU_A(20)
18
11
18
19
38
40
F217
F218
MIU_D(9)
MIU_D(10)
MIU_A(20) 9 MIU_A(19) 16 MIU_A(21) 12 42 F219 MIU_D(11)
MIU_RDY * 4225 RDY MIU_A(21) 10

13
19
20
A21 MIU_A(20) 9
18
19
13
MIU_A(22)
F272
15
2
20
21
DQ 45
47
F220
F221
MIU_D(12)
3219
MIU_A(22) MIU_D(13)
4K7
21 22
14 PNX_PIO3_MIU_A23 49 F222 MIU_D(14)
F207 4202 NC
NOR_RSTN RDY 15 RDY 15 10 MIU_WEN 13 51 F223 MIU_D(15)
RB RB WE 15
PNX_SYS_RESETN NOR_RSTN 12 VPP/WP_ 14 4227 NOR_RSTN 12 NOR_RSTN 14
RP RP RP A-1
MIU_WEN 11 MIU_WEN 11 BYTEN 53
F203 CSN(0) WE WE BYTE
4203 28 28 34 17
2236
100n
MIU_OEN MIU_OEN MIU_OEN RDY

MIU_CSN(0) OE OE G RY
CSN(0) 26 CSN(0) 26 CSN(0) 32
CE CE E BY
BYTEN 47 BYTEN 47 16 MIU_A(22) 4213
I MIU_CSN(1)
F204 4238
CSN(1) BYTE
F254
BYTE VSS WP
VPP
MIU_WEN 4214
PHI_CMD
I
27
46
27
46
VSS PHI_WRN
F205 F253
4216 MIU_OEN 4215
33
52
MIU_CSN(2) PHI_CSN PHI_RDN
F206 F256
MIU_RDY 4212
MIU_CSN(3) PHI_RDY
{MIU_A(22:0),MIU_CLK,MIU_OEN,MIU_WEN,CSN(0),BYTEN,RDY,NOR_RSTN}

3139-243-36835_130-02_a2.eps 2007-07-17
1 2 3 4 5 6 7 8 9 10 11 12 13
Digital: IEEE 1394+USB (DV+USB)
1 2 3 4 5 6 7 8 9 10 11 12 13 1301 D13
1302 H12
1303 C7
2300 B9
2301 B9
2302 B9
2303 B9
2304 B7
2305 B7
2306 C6
A A 2307 C6
2308 C7
2309 E7
2310 E11
2311 E11
3V3A_PHY 3V3D_PHY 3V3PLL_PHY 2312 D3
2313 G9
2314 G10
4308
2316 2315 H9
2316 B8
100u 10V
3300 C9
+5V +3V3 MT2 XDV
2300 100n 3301 C7
B 2301 100n
B 3303 D6
PHY_XIN 3304 D6
from VIP 2304 100n 2302 100n 3305 D6
3306 D7
3332
22R
2305 100n 2303 100n 3307 D7
+5V +3V3 * 3308 D6
3309 E6
1303 7300 to LECO
5300 F316 2306 24M576 AT-49 F320 3300 3310 E7
25
35
21
44
45
40
BLM18P 4309 TSB41AB1PHP
F300 PHY_CLK
3311 D9
Φ
PLLVDD
3V3PLL_PHY 10p AVDD DVDD 22R
F303 42 1 3312 D9
3330
1M0
60R XI SYSCLK {PHY_CTL(1:0),PHY_LREQ,PHY_D(7:0)}
+3V3 XDV 2307 3313 E9
F304 43 48 F321 PHY_LREQ
C 5301
BLM18P F301 10p # 2308 100n 38
XO LREQ
2 F322 PHY_CTL(0)
C 3314 E10
3315 E10
3V3A_PHY 3V3D_PHY 0 0
39 FILTER CTL 3 F323 PHY_CTL(1) 3316 D10
60R # 2308, 4300 Not for PDI1394P25BY XDV 1 1
3317 D11
# 4300 22 1-PORT CABLE 4 F324 PHY_D(0) 3318 D11
5302 TESTM 0
BLM18P F302
TRANCEIVER 1
5 F325 PHY_D(1)
3319 D11
3V3D_PHY 3301 1K0 23
SE ARBITER 2
6 F326 PHY_D(2)
3320 E11
7 F327 PHY_D(3)
60R 3 F328
24 D 8 3321 G7
3305
3304
3303
PHY_D(4)
4K7
4K7
100u 10V
1K0
SM 4 F329
9 3322 F8
2312
PHY_D(5)
5 F330
20 10 PHY_D(6) IEEE1394 3323 G8
CPS 6 F331
11 PHY_D(7)
PHY_LPS * 4301 F317 13

LPS
7
30
F305
F306 6 GND
3324 G10
3325 G9
D 19
ISO
TPA+
TPA-
29 F307
F310
5
4
TPA
TPAn
D 3326 H11
3327 H11
F308 3 GND
3306 5K6 1% 33 28 3330 C6
3V3D_PHY 0 TPB+ F309 2 TPB
3307 750R 1% 34 R 27
1 TPB- 1 TPBn 3331 D6
3331 31 16 3311 680R B6B-PH-K 3332 B7
56R 1%
56R 1%
56R 1%
56R 1%
TPBIAS 0
17 3312 680R 1301 4300 C7
3316
3317
3318
3319
* 3308 10K PC 1
PNX_PIO24_1394_PD F318 12
PD 2
18 3313 680R 4301 D6
from FRONT BOARD 4302 E10
*
22R 3309 F332
F319 37 15 4302
PNX_PIO26_1394_RSTN 4303 H7
GND_HS
RESET C PHY_LKON
PLLGND
100R LKON 3314 4304 H7
5K1 1%
AGND DGND 3V3D_PHY
4305 F8
2310
2311
220p
3320
1u0
10K
4306 I11
*
2309
E E
26
32
36
14
46
47
41
49
100n
3310
4K7
3315
4308 B5
10K 4309 C6
XDV 5300 C3
5301 C3
5302 C3
7300 C8
7301 F9
F300 C4
F301 C4
USB_VBUS F302 C4
+5V
F303 C7
F F F304 C7
F305 D12
7301
F306 D12
3322
TPS2051AD
10K
F307 D12
F308 D12
4305 4 6
PNX_PIO31_USB_VBUSON EN 1 F309 D12
from LECO 2 7 F310 D12
+5V 1 OUT 2
F311 H12
3323
10K
IN
3 8 F312 H12
47u 16V
2 3
*
2314
F313 H12
5
OC_ F314 H12
GND
2313
100n
F315 H12
G 3V3D_PHY +5V
G F316 C6
F317 D7
1
F318 E7
F319 E7
3321
3324
10K
10K
F320 C9
* 3325
F321 C9
* 4303
1394_CNA (not used) USB_OC
5K6
USB
1302
F322 C9
F323 C9
B5B-PH-K
4304 3326
F324 C9
2315
100n
PNX_PIO9_USB_OC USB_OC USB_DM F311 1 5VBUS
F312 F325 C9
to LECO 2 USBM
to LECO F313 F326 C9
3 USBP
3327 F314 F327 D9
H USB_DP
to LECO
F315
4
5
ID
GND H F328 D9
F329 D9
from USB Cable F330 D9
F331 D9
F332 E9
USB_ID
to LECO
4306
I I
3139-243-36835_130-03_a2.eps 2007-07-17
1 2 3 4 5 6 7 8 9 10 11 12 13
Digital: VIDEO+IDE+BOOT PROM+ EJTAG
1 2 3 4 5 6 7 8 9 10 11 12 13 1400 B8
1401 F8
3463 D7
3464 H7
F455 I8
F456 I8
1402-1 D12 3465 C4 F457 I8
1402-2 D13 3466 C3 F458 I8
1404 G13 3467 D7 F459 I8
{IDE0_CS(1:0),IDE0_DIOW,IDE0_DIOR,IDE0_IORDY,IDE0_DMACK,IDE0_DA(2:0),IDE0_DMARQ} PIO1 PIO0 BOOT MODE PIO13 QUARTZ SEL 2400 D6 3468 H7 F460 D11
2401 I6 3469 D4 F461 D11
5NV +5V +3V3
L L INT BOOT-FLASH 8 BIT L 4MHZ 2408 G13 3470 E3 F462 D11
+3V3 2410 A2 3471 D7 F463 D11
IDE0_DD(15:0) L H INT BOOT-FLASH 16 BIT H 16MHZ 2411 A3 3472 I7 F464 D11
H L I2C BOOT 2412 A3 3473 E4 F465 D11
+3V3 +3V3 2413 B5 3474 D6 F466 B10
H H I2C FAST BOOT 2414 C2 3475 D7 F467 A10
A A
+5V 5NV
5NV +5V +3V3
2415 C2 3476 I6 F469 A2
2416 C3 3477 I7 F470 A3
3403
3401
3402
F469 F470
10K
4K7
4K7
5401 5402
2417 C4 3478 D7 F471 B3
3444
3405
10K
1K0
5V_BUF 5N_BUF IDE0
4u7 4u7
PIO0
F467
* 2418 D1
2419 D1
3479 I7
3480 D7
F472 C2
F473 E3
10u 16V
OPTICAL DRIVE
16V 10u
PNX_PIO0_IDE1_RSTN
2410
2411
2412
100n
1400 2420 D2 3481 I7 F474 H13
F466
3410 33R F400 2421 D4 3482 D7 F475 H13
PNX_PIO11_IDE0_RSTN 1 PIO1 PNX_PIO1_BOOT_1 PNX_PIO13_DTT_RTS_1
2
2422 E1 3483 I7 F476 H13
IDE0_DD(7) 3412-4 33R F401 2423 E2 3484 D7 F477 H13
3
IDE0_DD(8) 3412-3 33R F402
5V_BUF 4 2424 E2 3485 I7 F478 H13
3407
3409
IDE0_DD(6) 3412-2 33R F403
4K7
4K7
IDE0_DD(9) 3412-1 33R F404
5 2425 F3 3486 D7 F479 D13
B
6
2413
IDE0_DD(5)
IDE0_DD(10)
3414-4
3414-3
33R
33R
F405
F406
7
8
B 2426 F1
2427 F2
3487 I8
3488 G11
F480 F2
F481 G2
4411 IDE0_DD(4) 3414-2 33R F407 2428 G3 3494 F2 F482 I2
100n 9
F471 IDE0_DD(11) 3414-1 33R F408
PNX_B_U 2429 G1 3495 G3 F483 G11
* 100R
5403 5404 5405 3462 10
7401 IDE0_DD(3) 3416-4 33R F409
from LECO
BC847B IDE0_DD(12) 3416-3 33R F410
11 2430 G2 3496 H3 F484 H11
1u2 1u5 470n 12 2431 H3 3497 F13
IDE0_DD(2) 3416-2 33R F411
13 BOOT MODE QUARTZ SEL
*4405 2432 I1 3498 I2
2414
2415
270p
2416
180p
3420 3421 IDE0_DD(13) 3416-1 33R F412

82p
D_UB 14
75R 1% 75R 1% IDE0_DD(1) 3418-4 33R F413
15 2433 I1 3499 G11
to VIO conn IDE0_DD(14) 3418-3 33R F414
16 3401 A11 4400 D5
IDE0_DD(0) 3418-2 33R F415
17 3402 A12 4401 H6
330R
3422
3465
IDE0_DD(15) 3418-1 33R F416
1K0
18 3403 A6 4405 C4
19
C 5V_BUF
* IDE0_DMARQ 3449 82R F417
20
21 C
3404 F6
3405 A7
4406 D3
4407 E4
22 3406 F7 4411 B4
IDE0_DIOW 3452 22R F418
+3V3 23 +3V3 3407 B11 4412 C3
2417 5N_BUF 24
IDE0_DIOR 3454 22R F419 3409 B12 4413 E3
25 3442
4412
100n 26
3410 B7 5401 A1
F472 IDE0_IORDY 3457 82R F420 3411 F7 5402 A3
5406 5407 5408
* 3466 27 10K
EJTAG
5
3460
7402
10K
PNX_G_Y 28 3412-1 B7 5403 B2
3443-1
3443-2
3443-3
3443-4
BC847B IDE0_DMACK 3463 22R F421
10K
10K
10K
10K
1u2 1u5 470n 100R 29 3412-2 B7 5404 B3
from LECO
3423
* 4406 4400 * 30 ROW_1
1402-1
ROW_2
1402-2 3412-3 B7 5405 B3
2418
2420
180p
2419
270p
3424 3467 82R F422

82p
D_YG PNX_PIO12_IDE0_IRQ 31
4
75R 1% 75R 1%
32 PNX_TRST
F460
1
F479 3412-4 B7 5406 C1
to VIO conn PNX_TRST GND 2
IDE0_DA(1) 3471 33R F423
33 PNX_TDI
F461
3 PNX_TDI GND 4 3413-1 G7 5407 C2
* 3475
2400
3474
5K6 F424 3451 33R F462
10K
3413-2 G7 5408 C2
22p
+3V3 PNX_TDO
D
34 PNX_TDO 5 GND 6
D
330R
3425
3469
IDE0_DA(0) 3478 33R F425 F463

1K0
35 PNX_TMS 7 PNX_TMS GND 8 3413-3 F7 5409 E2

IDE0_DA(2) 3480 33R F426 F464
36 PNX_TCK 9 PNX_TCK GND 10 3413-4 G7 5410 E2
* 5V_BUF
IDE0_CS(0)
IDE0_CS(1)
3482
3484
33R
33R
F427
F428
37
38
JTAG_RSTN
F465
11 EJTAG_RSTn GND 12
3414-1 B7 5411 E3
FTSH-106-01-L-DV FTSH-106-01-L-DV 3414-2 B7 5412 F1
39
F429 3414-3 B7 5413 G2
40
3486
5K6
5N_BUF 2421 3414-4 B7 5414 I1
1-440094-2
4413 3415-1 G7 7101 G12
100n
F473 3415-2 G7 7401 B4
*
5409 5410 5411 3470
PNX_R_V
7403 3415-3 G7 7402 D3
BC847B
1u2 1u5 470n 100R 3415-4 G7 7403 E4
from LECO
3416-1 C7 7404 F3
* 4407
2423
270p
2424
180p
2422
82p
3426 D_VR
E E 3416-2 B7 7405 G3
3427
to VIO conn
75R 1% 75R 1%
{IDE1_CS(1:0),IDE1_DIOW,IDE1_DIOR,IDE1_IORDY,IDE1_DMACK,IDE1_DA(2:0),IDE1_DMARQ} 3416-3 B7 7406 I3
3416-4 B7 7407 H11
330R
3428
3473
1K0
3417-1 G7 F400 B8
3417-2 G7 F401 B8
5V_BUF
* IDE1_DD(15:0) 3417-3 G7 F402 B8
3417-4 G7 F403 B8
+3V3 3418-1 C7 F404 B8
2425 5N_BUF 3418-2 C7 F405 B8
3418-3 C7 F406 B8
100n +5V 3418-4 C7 F407 B8
3404
F480
10K
5412 3494
3419-1 G7 F408 B8
3406
7404
1K0
IDE1
F F
PNX_C BC847B
1u5 100R 3419-2 H7 F409 B8
from LECO
HARD DRIVE 3419-3 G7 F410 B8
75R 1%
75R 1%
2426
270p
3429
2427
270p
3430
3447
1K0
D_C 3419-4 G7 F411 B8
1401
to VIO conn
3411 33R F430 3420 B1 F412 C8
PNX_PIO0_IDE1_RSTN 1 3497
2
3421 B3 F413 C8
3431
IDE1_DD(7) 3413-3 33R F431 3422 C4 F414 C8

1K0
3 100R
IDE1_DD(8) 3413-4 33R F432 F483
4
PNX_UART_TXD(0) 3488 3423 D1 F415 C8
IDE1_DD(6) 3413-2 33R F433 7101
IDE1_DD(9) 3413-1 33R F434
5
BC847B 3424 D2 F416 C8
6 4K7
IDE1_DD(5) 3415-4 33R F435 3425 D3 F417 C8
5V_BUF 7 3448
5N_BUF IDE1_DD(10) 3415-3 33R F436
8 2408
3426 E1 F418 C8
IDE1_DD(4) 3415-1 33R F437 9 4K7 3427 E3 F419 C8
IDE1_DD(11) 3415-2 33R F438 3428 E4 F420 C8
G
2428 10 1n5
100n
IDE1_DD(3)
IDE1_DD(12)
3417-3
3417-4
33R
33R
F439
F440
11
12
+3V3 G 3429 F1 F421 D8
F481 IDE1_DD(2) 3417-1 33R F441 3430 F2 F422 D8
5413 3495 13
PNX_Y
7405 IDE1_DD(13) 3417-2 33R F442
14
3431 F3 F423 D8
1u5 100R
BC847B IDE1_DD(1) 3419-3 33R F443
15
SERVICE 3432 G1 F424 D8
from LECO
3499
IDE1_DD(14) 3419-4 33R F444
10K
3433 G2 F425 D8
75R 1%
75R 1%
16
1404
3432
2429
270p
2430
270p
3433
IDE1_DD(0) 3419-1 33R F445

D_Y 17 3434 H3 F426 D8
IDE1_DD(15) 3419-2 33R F446 F474
18 PNX_PIO24_1394_PD 1 TXD
to VIO conn F475 3435 I1 F427 D8
19 2 SERVICE
20
F476
3
3436 I2 F428 D8
+3V3 RXD
330R
3437 I3 F429 D8
3434
3496
IDE1_DMARQ 3450 82R F447

1K0
21 4 NC
F477 3438 H11 F430 F8
22 5 GND
*
IDE1_DIOW 3453 22R F448
+3V3 23
F478
6 NC 3439 H12 F431 F8
+5V
H
24 7
H
+5V 3440 I12 F432 G8
3438
IDE1_DIOR 3455 22R F449
10K
25
26
B7B-PH-K 3441 I12 F433 G8
5V_BUF
5N_BUF IDE1_IORDY 3458 82R F450
27 F484 3442 C11 F434 G8
PNX_UART_RXD(0)
3461
10K
28 3443-1 D10 F435 G8

IDE1_DMACK 3464 22R F451
2431 29 3439 3443-2 D10 F436 G8
100n PNX_PIO6_IDE1_IRQ
4401 * 3468 82R F452
30
31
7407
BC847B 10K
3443-3 D10 F437 G8
5414 F482
32
3443-4 D11 F438 G8
PNX_CVBS 3498
7406 IDE1_DA(1) 3472 33R F453
33 3444 A7 F439 G8
BC847B
*
3440
3441
2401
3476
3477 5K6 F454
10K
6K8
from LECO
10K
3447 F12 F440 G8

22p
1u5 100R +3V3 34 {PNX_UART_TXD(1:0),PNX_UART_RXD(1:0)}

IDE1_DA(0) 3479 33R F455
75R 1%
75R 1%
35 3448 G12 F441 G8

3435
2433
270p
3436
2432
270p
IDE1_DA(2) 3481 33R F456

LECO_CVBS 36 3449 C7 F442 G8
IDE1_CS(0) 3483 33R F457
37
# to VIO conn IDE1_CS(1) 3485 33R F458 3450 H7 F443 G8
I
38
39 I 3451 D11 F444 G8
LECO_CVBSin
330R
3437
3459
F459
1K0
40 3452 C7 F445 G8
1-440094-2 3453 H7 F446 H8
* 3454 C7
3455 H7
F447 H8
F448 H8
3457 C7 F449 H8
3487
5K6
3458 H7 F450 H8
5N_BUF
* Not used (Provision only) 3139-243-36835_130-04.eps 2007-07-21
3459 I3 F451 H8
3460 D6 F452 H8
3461 H6 F453 I8
3462 B4 F454 I8
1 2 3 4 5 6 7 8 9 10 11 12 13
Digital: Audio/Video Decoder (VIP)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1500 B1
1501 E1
3525-4 D13
3526 D4
F525 F2
F526 F2
1502 H1 3528 D4 F527 G2
1503 I1 3531 E12 F528 G2
+3V3_VIP +1V8 +5V 5500 5501 1504 G8 3533 B13 F529 G2
BLM18P F541 BLM18P F548
VDDDIO 5502 +1V8 VDDDI 1505 I10 3534 H10 F530 G2
+3V3_VIP
60R BLM18P F546 60R 1506 B1 3536 I10 F531 G2
1507 I2 3537 I10 F532 G2
10u 16V
10u 16V
+3V3_VIP VDDA3V3
100n
2500
2501
100n
2503
2505
100n
2506
100n
2508
100n
2509
2510
100n
2511
100n
2512
100n
2513
100n
2514
100n
2515
100n
2502
100n
2504
100n
2507
100n
60R 2500 A5 3539 F8 F533 G2
10u 16V
2501 A5 3540 F12 F534 G2
2516
2518
100n
2519
100n
2520
100n
2521
100n
2522
100n
2524
100n
2525
100n
2526
100n
2527
100n
+3V3_VIP +1V8 +5V 2502 A5 3543 F7 F535 H2
A
5503
+1V8
BLM18P F547
VDDDMEM
A 2503 A5
2504 A5
3544 G8
3545 H9
F536 H2
F537 I2
3V3 60R 5504 2505 A6 3546 H3 F538 I2
VDDA3V3 BLM18P F549 2506 A6 3547 I3 F539 I2
2528
100n
2529
100n
5505 3V3 +1V8 VDDA1V8
{REAR_Y_CVBS,REAR_CIN,Y_G,U_B,V_R_C,TUN_CVBS,SC1_CVBS,SC2_YCVBS,VCR_CVBS,FR_YIN,FR_CIN,FR_CVBS,LECO_CVBS} F542 BLM18P VDDA3V3 60R
2507 A6 3548 I3 F540 I2
5506 2508 A6 3549 I3 F541 A6
2530
100n
2531
100n
3V3SW 60R F564 BLM18P {VIP_ITU0_IN(2:9),VIP_ITU0_IN_CLK,VIP_ITU0_IN_VAL,VIP_ITU0_IN_SOP,VIP_ITU0_IN_LOCK} 2509 A12 3550 H4 F542 A6
47u 6.3V
2510 A12 3551 C8 F543 B5
2517
100n
2533
60R 1V8 3V3 1V8 2511 A12 3552 D8 F545 B7
VDDDI VDDDIO VDDDMEM
VDDAADC 2512 A12 3553 H12 F546 A10
4526
2534
100n
+3V3_VIP
2513 A13 3554 H12 F547 A11
5507 1V8 {PNX_SCL(0),PNX_SDA(0),PNX_SCL(1),PNX_SDA(1)} 2514 A13 3555 H12 F548 A13
*
BLM18P F543 VDDA1V8 2515 A13 3556 H12 F549 A13
M13
G16
R13
H16
C14
N10
D10
N11
C11
3V3
P10
K16
E14
B14
B12
E13
T11
T16
7500-2
L15
+3V3_VIP
J11
5508 2516 A8 3557 H12 F550 G7
R9
C9
D7
P7
T8
VIO conn
4K7
4K7
B
VDDA3V3
B
60R F545 BLM18P SAA7136AE/V1/G
100n
2523
Y_G 2517 A6 3558 H12 F551 G8
100u 6.3V
VDDDI VDDDE VDDDMEM
1500 #1506 HLW24S-2C7 2518 A8 3559 I7 F552 C2
2535
2536
100n
F500 1V8 3V3 60R
1
Φ 2519 A9
6 10K
7 10K
8 10K
D_UB 1 D_UB (YCVBS_IN_REAR) VDDA1V8 VDDA3V3 3560 C3 F553 C14
47R
47R
47R
47R
47R
47R
VMUX6_OUT
2 M7
2537
100n
2520 A9
3501
3561 C3
3502
GND 2 F501 NC 0 F554 C13
AUDIO/VIDEO
4 3505-4 5
LECO_CVBSin
3 N7 D_CON
D_YG 3 D_YG 3573 1
3574
3575
3576
3577
NC 2521 A9 3562 C3 F555 C13
3523
4 DECODER T4 3533 22R PNX_SCL(1)
10K
GND 4 F502 SCL
5 P8 N5 3512 22R PNX_SDA(1) 2522 A9 3563 C3 F556 C13
D_VR 5
6 F558
D_VR
R8
0 DIGITAL PART SDA
P5
GND 2523 B4 3564 C3 F557 C13
3505-33
3505-22
3505-11
6 1 SCL_SILENT SCL_S3V3
M3
G3
G6
H5
D2
C7
D1
N4
R1
R7
K4
A6
F5
4524 Eu
4525 Eu
L4
J2
J7
J4
7 F503 7500-1 VIP_ITU0_IN(2) K8 R5
D_C 2524 A10 3565 C3 F558 C2
4519 #
4523 #
7 D_C SAA7136AE/V1/G 2 SDA_SILENT SDA_S3V3

8 VIP_ITU0_IN(3) K9
VDDA1V8
VDDAC18
VDDAADC
VDDADAC
VDDADAC1
VDDADAC2
VDDA1A
VDDA2A
VDDA3A
VDDA4A
VDDA0
VDDA1
VDDA2
VDDA3
VDDA4
VDDAPLL
VDDAOSC
GND 8 3 F553 2525 A10 3566 D3 F559 C2
9 F504 VIP_ITU0_IN(4) L9 T2
D_Y 9 D_Y 4 TRST
10 3560 27R 2538 22n F1 VIP_ITU0_IN(5) N9 DI_A R3 F554 2526 A10 3567 D3 F560 D2
GND 10 F505 LECO_CVBS 1 5 TCK
D_CVBS 11
11 3561 27R 2539 22n G2
2
VIP_ITU0_IN(6) P9
6 TMS
T3 F555 2527 A10 3569 D3 F561 F2
Φ
12 3562 27R 22n G1 AI1 E2 T9 P4 F556 2528 A11 3570 D3 F562 G2
3513
FR_YIN 2540 VIP_ITU0_IN(7)
C C
1K0
GND 12 F506 3 V_IOUTP NC 7 TDO
13 SC1_CVBS 2541 22n H6 E1 VIP_ITU0_IN(8) G13 R4 F557
13 D V_IOUTN NC 8 TDI 2529 A11 3571 D3 F563 H2
SC1_CVBS / C_IN_REAR#
14 AUDIO/VIDEO VIP_ITU0_IN(9) G14
GND 14 F552 VMUX6_OUT 9 2530 A13 3573 B3 F564 A7
VMUX6_OUT 15
15 V_R_C 3563 27R 2542 22n H3
1 DECODER SI_VSYNC
L8 NC
16 F559 3564 27R H2 VIP_ITU0_IN_CLKJ10 2531 A13 3574 B4 F565 H8
GND 16
SC1_CVBS (C_IN_REAR) # 2543 22n 2 ANALOG PART 3551 CLK
A_YG 17
GND 18
17
18
F508
F509
Y_G FR_CIN 3565 27R
4508 4509
2544
2545
22n
22n
H1
J5
3
D
AI2
75R 1%
L10
VIP_ITU0_IN_LOCK
VIP_ITU0_IN_VALM10
LOCK
VAL
DI_A
IF_AGC
A8 NC
* 4514
PNX_PIO5_VIP_IRQN
2532 H9
2533 A6
3575 B4
3576 B4
F570 E13
c500 E2
19 U_B # K5 VIP_ITU0_IN_SOPT10 N6 4513
A_UB 19 AOUT1 AOUT1 SOP INT_A WU 2534 B7 3577 B4 c501 H7
{PNX_ITU0_IN(7:0),ITU0_IN_VS,ITU0_IN_HS,ITU0_IN_VALID,ITU0_IN_CLK}
20 Y_G Eu 3566 27R L3 K3
2546 22n AOUT2
GND 20
21 F510 V_R_C SC2_YCVBS 3567 27R 2547 22n L2
1 AOUT2
G15 M11 47R 3515-4 PNX_ITU0_IN(0) 2535 B5 3578 D3
A_VR 21 2 3552 to VIO conn NC 0 0
22 VMUX5_OUT 3569 27R 2548 22n L1 AI3 F12 P11 47R 3515-3 PNX_ITU0_IN(1) 2536 B5 3579 D4
GND 22 F511 VMUX5_OUT 3 NC 1 1
VMUX5_OUT 23
23 2549 22n M4
D 75R 1% NC
F13
2 2
R11 47R 3515-2 PNX_ITU0_IN(2) 2537 B7 3580 D4
24 A2 F14 P12 47R 3515-1 PNX_ITU0_IN(3) 2538 C4 3581 D4
GND 24 F512 NC NC 3 3
U_B 3570 27R 2550 22n N1 B2 F15 DI_E R12 47R 3516-3 PNX_ITU0_IN(4)
AOUT1 25 AOUT1 1 NC NC 4 4 2539 C4 3582 E3
D GND 26
F560 2551
* 22n P3
2
B8
NC NC
F16
5
DVO_C
5
T12 47R 3516-4 PNX_ITU0_IN(5)
D 2540 C4 3583 E3
3581 47R Eu
F513 FR_CVBS 3571 27R 2552 22n P2 AI4 E10 E16 N13 47R 3516-2 PNX_ITU0_IN(6)
AOUT2 27 AOUT2 3 NC NC 6 6 2541 C4 3584 E3
2553 22n R2 H7 D13 P13 47R 3516-1 PNX_ITU0_IN(7)
3578 47R
3579 47R
GND 28 D NC NC 7 7
3580 47R
F507 6501 2542 C4 3585 E3

3524 47R
SC2_YCVBS 29
SC2_YCVBS H10
NC
GND 30
FR_YIN 1 2 NC C2 VSYNC
H11
NC NC
K11
0 CLK
N15 2
47R 7
3525-2 ITU0_IN_CLK 2543 C4 3586 E3
3526 3K0 1% F4 H12 K12 N16 1
47R 8
3525-1 ITU0_IN_HS
DAC_BIAS NC NC 1 HS
ITU0_IN_VS
2544 C4 3587 E3
HLW30S-2C7 DF3A6.8 3528 2K4 1% K6 H13 K13 DVO M15 4
47R 5
3525-4
RES_REF_V
NC H14
NC NC
K14
2 VS 2545 C4 3588 E4
3
3
NC NC 2546 D4 3589 E4
*
6502 2554 22n F3 H15 K15 DI_B L13 3
47R 6
3525-3 ITU0_IN_VALID
HLW9S-2C7 VIF IF_POS NC NC 4 DQ
FR_CIN 1 2 2555 22n F2 IF_NEG
J1
NC NC
J13
5
DVO
ODEV
L12 2547 D4 3590 E4
F517 J8 J14 F570
YFIN 9
FR_YIN
NC NC 6 2548 D4 3591 E4
DF3A6.8 2556 22n N3 K7 J15 C12 PHI_RDN
GND 8 F518 SIF P NC NC 7 0 2549 D4 3592 E4
FR_CIN 2557 22n N2 AI40 M5 E11 PHI_RDY
7 N GPIO 1 2550 D4 3593 E4
3
CFIN NC
M6 NC
J16 M16 3531 47R ITU1_IN_VALID
GND 6 F519 NC CLK 2 2552 D4 4501 F8
FR_CVBS AIN1R 3582 12K 3588 390R 2558 4u7 D5 M8 G12
E CVBSFIN
GND
5
4 F520 AINFL
AIN1L 3583 12K 3589 390R 2559 4u7 C5
IN1_R
IN1_L
P1
T5
NC
NC
PHI_D(7:0)
NC
NC
H9
G11
DQ
HS
DI_B
0
P14
R14
47R
47R
3517-1
3517-3
PNX_ITU1_IN(0)
PNX_ITU1_IN(1)
E 2553 D4
2554 E4
4502 F8
4503 F8
AINFL 3 NC NC VS 1
AIN2R 3584 12K 3590 390R 2560 4u7 B5 T14 47R 3517-4 PNX_ITU1_IN(2)
GND 2 F521 IN2_R DVO_D 2
R15
2555 E4 4504 H8
AINFR AIN2L 3585 12K 3591 390R 2561 4u7 A5 E4 PHI_D(0) D15 47R 3517-2 PNX_ITU1_IN(3)
AINFR 1 IN2_L S_IOUTP
E3
NC
PHI_D(1) D16
0 3
T15 47R 3518-4 PNX_ITU1_IN(4) 2556 E4 4505 H6
S_IOUTN NC 1 4
1501 c500 AINFR 3586 12K 3592 390R 2562 4u7 D4 PHI_D(2) C16 P15 47R 3518-2 PNX_ITU1_IN(5) 2557 E4 4507 I6
IN3_R 2 5
to FRONT BOARD AINFL 3587 12K 3593 390R 2563 4u7 B4 IN3_L OUT1_R
B7 LR1_R PHI_D(3) B15
3 6
P16 47R 3518-3 PNX_ITU1_IN(6) 2558 E4 4512 H9
A7 LR1_L PHI_D(4) B16 VIP_D N14 47R 3518-1 PNX_ITU1_IN(7) 2559 E4 4513 C13
OUT1_L 4 7
A4 PHI_D(5) A16
GNDA FBIN AUX1A 5 L14 3540 2560 E4 4514 C13
C3 F7 LR2_L PHI_D(6) A15 47R ITU1_IN_CLK
NC AUX1B OUT2_L
E7 LR2_R PHI_D(7) C13
6 CLK 2561 E4 4515 I10
OUT2_R 7 2562 E4 4517 I10
B3 VDDDIO 3539 4K7
NC AUX2A
HLW24S-2C7
F522 NC
A3
AUX2B PHI_CMD
B13
CLK
2563 E4 4519 C3
AIN1L A13 2564 F4 4522 F9
F AUDIO1_L
GND
24
23 F561
F523 AIN1R
NC
B1
A1
AUX3A XTALI
T6
PHI_CSN
PHI_WRN
D12
HCTL VIP
RST F 2565 G4 4523 C3
AUDIO1_R 22 VDDAADC NC AUX3B
T7 4522 D14 2566 G4 4524 C3
GND 21 F524 XTALO PP_SEL 2567 G12 4525 C3
AUDIO2_L
AIN2L B6
20 VRPOS_ADC
2568 G5 4526 B5
GND 19 F525 2564 470n C6
VRNEG_ADC XTOUT
L7 PNX_SD_OUT
*4501 F8
SD SD
A10 VIP_SD0_OUT
AUDIO2_R 18
AIN2R PNX_SCK_OUT
*4503
4502 G8
SCK I2S_I_1 WS
G9 PNX_WS0_IN 2569 G7 5500 A4
D6
3543
PNX_WS_OUT
* A9 F9 PNX_SCK0_IN
1R0
17 F526 2570 G8 5501 A12
VSSADAC2
GND VREF_DAC WS I2S_O SCK

VSSAOSC
VSSAADC
VSSADAC
F6 E9 PNX_FSCLK_IN
K2 VSSAPLL
AUDIO3_L 16 VREF0 AMCLK 2571 G2 5502 A8

VSSA1A
VSSA2A
VSSA3A
VSSA4A
AGND1
AGND2
C4 NC C8 D9
47u 6.3V
VSSA0
VSSA1
VSSA2
VSSA3
VSSA4
GND 15 F527 VREF_ADC SD SD_AUX NC

NC D8
2572 G2 5503 A11
2565
2566
100n
AUDIO3_R 14 F550 F551 SCK I2S_I_2

GND 13 F562 2571 NC E8 WS
2567 2573 H2 5504 A13
22p
2574 H2 5505 A6
2568
470n
F528 LR1_L
E5
E6
D3
M1
G5
R6
C1
L6
G4
J6
L5
K1
H4
J3
M2
T1
LR1_L 12 1504
10u 16V NC B10 C10 NC
GND 11 F529 SPDIF_I SPDIF_O 2575 H5 5506 A7
2572 LR1_R
G LR1_R 10
10u 16V 24M576
NC D11 B11 NC G 2576 I4 5507 B5
3519
1R0
GND 9 F530 IR_IN IR_OUT 2577 I2 5508 B7

D_KILL# 8 PNX_PIO30_DKILLN 3544
DAOUT
GND
7
6
F531 DAOUT
PHY_XIN
* 1M0
P6
CE OUT_RST
A11 NC 2578 I2
2579 I2
6500 I10
6501 D3
DAINCOAX 5 F532 DAINCOAX 2580 I3 6502 E3
F533 to DV 2569 2570
DAINOPT 4 DAINOPT 27p 27p VSSDI VSSDE VSSDMEM 3501 B13 7500-1 C5
GND 3 F534 3V3 3502 B13 7500-2 B9
c501
J9
L11
K10
E12
F11
G7
N8
M9
R10
N12
T13
R16
M14
L16
J12
G10
F10
E15
C15
A14
A12
B9
M12
H8
SIF 2 SIF VDDDIO
F563 PNX_PIO15_VIP_RSTN +3V3_VIP 3505-1 C14 7502 H5
GND 1 F565
from LECO 3505-2 C14 7503 I10
1502 LR2_L
*
*
*
XVIP XVIP 3505-3 C14 7504 I9
3553
3555
3557
AIO_0 conn
*
4K7
4K7
4K7
{AIN1L,AIN1R,AIN2L,AIN2R,AINFL,AINFR,LR1_L,LR1_R,LR2_L,LR2_R,PNX_SCK_OUT,PNX_WS_OUT,PNX_SD_OUT,PNX_FSCLK_OUT,PNX_SPDIF_OUT} 3505-4 B14 7506 I6
3545
LR2_R 4504
4K7
+3V3_VIP 3512 B13 7507 I6

H H
PNX_SPDIF_OUT
+5V 4505 4512 VIP_SD0_OUT 3513 C14 7508 I8

2575
PNX_WS0_IN 3515-1 D13 F500 B2
2532
100n
3534
12 PNX_SCK0_IN
10K
GND F535 7502
+3V3
3515-2 D13 F501 B2
11 2573 74HCT1G125GW
LR2_L 100n 3515-3 D13 F502 B2
*
10 10u 16V DAOUT
5
GND F536 VIP_RESET_GATE 3515-4 D13 F503 C2

2574
3554
3556
3558
9 2 DAINCOAX
4K7
4K7
4K7
5
LR2_R 8 from ASP

GND
8 10u 16V
3546 33R
3550 47R 4 2 3516-1 D13 F504 C2
7 PNX_SCK_OUT 1 4
7 F537 3516-2 D13 F505 C2
*
D_BCLK 6 EN 3536 6500 PNX_PIO15_VIP_RSTN
6 1
GND 5 3547 33R PNX_WS_OUT EN 7504 from LECO 3516-3 D13 F506 C2
2576
220p
5 F538 BC847BW
3
D_WCLK 4 7506 22K 3516-4 D13 F507 D2

3548 33R PNX_SD_OUT BAT54 COL
D_DATA0 4 F539 7503
3
74LVC1G125GW
3 BC847BW 3517-1 E13 F508 C2
3537
GND 3
47K
2 3549 33R {VIP_SD0_OUT,PNX_WS0_IN,PNX_SCK0_IN,PNX_FSCLK_IN}
D_MCLK
2 F540 PNX_FSCLK_OUT 3517-2 E13 F509 C2
1 4507 +3V3
GND
1 PNX_SPDIF1_IN 3517-3 E13 F510 D2
#
+3V3
3517-4 E13 F511 D2
1503 1507 HLW8S-2C7 {PNX_ITU1_IN(7:0),ITU1_IN_VALID,ITU1_IN_CLK}
HLW12S-2C7 3518-1 F13 F512 D2
22p
22p
22p
22p
I I
3559
FOR DTTM04
4K7
AIO_1 conn 3518-2 E13 F513 D2

5
DAINOPT 6 GND
2
5
3518-3 E13 F517 E2
NC
4 4517 3518-4 E13 F518 E2
2577
2578
2579
2580
PNX_PIO7_SPDIF2_IN 4 NC
*
1 4515
7507 EN 3 DAINDTT 3519 G7 F519 E2
74LVC1G125GW SPDIF_SW 2 NC 3523 B4 F520 E2
3
1 NC 3524 D4 F521 E2
* Not used (provision only) 1505 3139-243-36835_130-05_a2.eps 2007-07-17 3525-1 D13 F522 F2
HLW6S-2C7
7508 3525-2 D13 F523 F2
PDTC124EU
3525-3 E13 F524 F2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Digital: Microcontroller+Reset ASP+RESET
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1600 E2
1601 G1
F604 B2
F605 B2
1602 I2 F606 B2
1603 B2 F607 B2
1604 E9 F608 B2
3664
1605 C8 F609 B2
5VSTBY 3V3STBY +3V3 5VSTBY
910R 1% 1606 G2 F610 B2
7608 2601 B9 F611 B2
2
NCP301LSN 45 2602 B10 F612 C2
VCC 2603 B10 F613 C2
2614
100n
A NC
4
NC RESET
1
A 2604 B9
2605 B7
F614 C2
F615 D2
5 5VSTBY
NC 2606 E8 F616 D2
GND 5600 2607 F6 F621 D2
5VSTBY 3V3STBY +3V3 6603 BLM18P F650 2608 F8 F622 D2
2609 F5 F623 D2
3
BAT760 60R
2610 G5 F624 D2
220m 5.5V
100u 10V
2603
100n
2601
2602
2611 G8 F625 D2
2613 G6 F626 D2
GND 1
1603
* 4614
VFD_CLK
5VSTBY 3V3STBY 5VSTBY 2614 A4 F627 D2
VFD_CLK 2 F605
* 4615 2616 I7
2617 I8
F628 D2
F629 D2
3601
F604
10K
B B
GND 3 2604
DISP_DATA 4 F606 DISP_DATA 2618 C6 F630 D2
3602
3620
F607
10K
10K
DISP_CLK 5
F608
DISP_CLK 100n 2619 C8 F632 E2
DISP_STBN 6 DISP_CSN F653 3142 G11 F633 E2
STDBY_LEDN 7 F609 STDBY_LEDN
RC 8 F610 RC 2605
3143 F13 F634 E2
3604
GND 9 7600 3601 B7 F635 F2
F611 PDTC124EU 7604
TEMP_SENSE 10 TEMP_SENSE 470R 220n 3602 B5 F636 F2
39
40
78
F612 TMP87CH74F
KEY1 11 KEY1 PNX_PIO2_ASP_RST 3603 D8 F637 F2
F613 F651
Φ
VAREF
VDD
VKK
KEY2_3 12 KEY2_3
F614 7601 9 3604 B6 F638 F2
SEL_KEY2_3 13 F603 1 MC
PDTC124EU 3605 D9 F639 F2
1605
8M0
GND 14 XTAL
BAT54 COL
8 3606 D6 F640 G2
2619
10n
2
HLW14S-2C7-LF
6605
XASP F652 3607 D7 F641 G2
10
C C 3608 F8 F642 G2
RESET
to FRONT BOARD 5VSTBY
13 3609 C12 F643 G2
2618 3652 TEST
3610 C12 F644 H2
3659 100R 79 SCK1 3611 C12 F645 H2
COMM_0 conn 100n 10K DISP_CLK 3660 100R 80 73
3646 4K7
3647 4K7
3609 4K7
3610 4K7
3611 4K7
3612 4K7
DISP_DATA SI1 2 NC 3612 C12 F646 H2
HLW18S-2C7 1 74
F602 2
SO1 3
75
NC STDBY_LEDN 3614 F8 F647 H2
GND 18 NC V3 4 NC 3615 E8 F648 H2
F615 3 76
SCL_S3V3 17 SCL_S3V3 P50_OUT 5 NC 3662
SDA_S3V3 16 F616 SDA_S3V3 NC 4 6
77
NC 7606 3616 E8 F650 A8
5 BC847BW 3617 F6 F651 C9
GND 15 NC 1K0
F621 6
WSRO 14 WSRO NC PD<0:4> 3618 F6 F652 C9
F622
STBY 13
F623
STDBY
41 3619 F5 F653 B8
DD_ON 12 PNX_PIO27_DD_ON P0<0:7> 0 NC 3620 B6 F654 E9
F624 42
D D
FAN_A 11 FAN_A 1
FAN_B 10 F625 FAN_B
3V3STBY 5VSTBY 3V3STBY 5VSTBY 15
INT0 2
43
LOOP_THRU_ON
3621 F12 F655 F9
REGION_SEL_A F626 16 44 3622 F12 F656 G8
9 REGION_SEL_A STDBY INT1 V 3 FAN_A
REGION_SEL_B 8 F627
REGION_SEL_B NC 17 TC2 4
45
FAN_B 3623 E8 F667 F9
3603 22K 46
GND 7
F628 18
PPG 5
47
FBOUT 3624 F13 c600 E8
8SC1 / AFC 6 {PNX_SCL(0),PNX_SDA(0),PNX_SCL(1),PNX_SDA(1)} 3649 NC DVO 6 IMUTE 3625 F12
48
3606
3607
F629
10K
10K
HD_ON 5 PNX_PIO8_HD_ON 5VSTBY TC4 7 WSRO
*
3605
4 F630 8SC2_WSRI 10K VFD_CLK
19
PDO
3626 F12
8SC2/WSRI
IMUTE 3 F632 IMUTE 100R PWM P6<0:7> 3628 F4
F633 3648 100R 20
LOOP_THRU_ON 2 LOOP_THRU_ON BSN20 BSN20 DISP_CSN INT3 3629 F5
F634 7602 7603 49
YUV_ACTIVEN / YC_REAR_ACTIVE 1
21
TC1 8
50
AUDIO_MUX1_SEL_A 3630 F5
3623 P50_IN INT2 9 AUDIO_MUX2_SEL 3631 F8
*
1600 PNX_SDA(0) 4610 22 51
5VSTBY INT4 10 NC
3616 470R 52 3632 G4
to ANALOG BOARD PNX_SDA(1) 4611
10K RC TC3 V 11
53
YUV_ACTIVEN
3633 G8
E E
3615 12 AUDIO_MUX3_SEL_C / YC_REAR_ACTIVE
4604 54
8SC1 PNX_PIO4_ASP_IRQ P1<0:7> 13 AUDIO_MUX3_SEL_D 3634 G8
*
PNX_SCL(0) 4612 55 4617
100R 14 VIDEO_MUX3_SEL 3635 G8
4601 14 56
YUV_ACTIVEN INT5 15 WU 3636 G7
PNX_SCL(1) 4613 c600 2606 F654
STOP
15p
12
XTIN P7<0:7>
5VSTBY 3637 G8
32K768
11 3638 G11
4605
1604
3625 4K7
3626 4K7
3621 4K7
3622 4K7
3143 4K7
3624 4K7
XASP XTOUT 3665
5VSTBY 57
4602
2608 16 NC 3639 G12

58
#
F655 10K
5VSTBY
P2<0:2> 17
59
NC 3640 G12
#
XASP 15p 18 NC 3642 H3

3614 22R 23 60
FOME_AFC SCL V 19 NC
61 3643 H3
3617
2K2
SI0 20 NC
3608 22R 24 62 3644 G6
COMM_1 conn 3618 SDA 21
63
NC
3619
2K2
KEY1 SO0 22 NC 3645 G7

HLW14S-2C7 25 64
100R
F F 3646 C11
3630 NC 23 NC
SCK0
2607
100n
GND 14 KEY2_3 3647 C12
F635 5VSTBY
AUDIO_MUX3_SEL_C 13 AUDIO_MUX3_SEL_C 100R P3<0:2> P8<0:7>
3667 4K7 3648 E7
2609
100n
AUDIO_MUX1_SEL_A 12 F636 AUDIO_MUX1_SEL_A 5VSTBY F667

F637 26 65 3649 D8
AUDIO_MUX3_SEL_D 11 AUDIO_MUX3_SEL_D 0 24 REGION_SEL_A
10K 1%
3631 100R 27 66
GND 10 HDMI_CEC_INTn 1 25 REGION_SEL_B 3651 H8
28 67
3628
F638 SPDIF_SW
FBIN 9
F639
FBIN to VIP
29
2 26
68 4616 3652 C6
FOME 8 3629 30
3 AIN V 27 69 4603
HDMI_BE_CTRL VIP_RESET_GATE 3659 C9
GND 7 TEMP_SENSE 4 28
31 70 3660 C9
3668
F640 3633 1K0 to VIP
4K7
FBOUT 6 6 FBOUT from ASP 10K 3644 FOME_AFC 5 29 AUDIO_MUX5_SEL_A
*
32 71 3662 D13
3632
2610
F641 4606 3634 100R

1M0
10n
WU 5 5 WU FR_CIN 6 30 AUDIO_MUX5_SEL_B
3635 F656 33 72
3666
Digital Optical in
47K
GND 4 4 TUNER_ON 47K 8SC2_WSRI 7 31 AUDIO_MUX6_SEL 3664 A4
*
F642 4609 from VIP
AMUX2_SEL 3 AUDIO_MUX2_SEL 68K 3665 E12
*
3
2613
3645
F643
82K
10n
VIDEO_MUX3_SEL 2 2 VIDEO_MUX3_SEL P4<0:7> P9<0:7> 3666 G13
3636
3637
2611
3142
15K
47K
22K
10n
G GND 1 1
* 34
G 3667 F8
3638
3639
3640
4K7
4K7
4K7
8SC1
*
10
1601 # 1606 HLW6S-2C7 35 3668 G14
NC 11 AIN
36
NC 12 4601 E3
to ANALOG BOARD NC
37
13 4602 E2
4603 G12
P5<0:3>
VASS
4604 E4
VSS
4605 E3
38
4606 G3
COMM_2 conn {PNX_UART_TXD(1:0),PNX_UART_RXD(1:0)}
4609 G2
HLW9S-2C7 4610 E5
GND 9
+3V3 +3V3 4611 E5
H
G_TXD 8 F644 3642
* 100R PNX_UART_TXD(1)
H
4612 E5
*
F645 3643 100R PNX_UART_RXD(1)
G_RXD 7 4613 E5
F646
DIROUT 6 PNX_PIO29_IR_OUT from LECO 4614 B3
GND 5 4615 B3
P50_IN 4 F647 P50_IN to ASP
4616 F12
3651
7607
4K7
GND 3
F648 NCP303LSN29 4617 E13
P50_OUT 2 P50_OUT from ASP
2 F601
GND 1 INP 5600 A7
1 PNX_RESETN
1602 5
OUTP 6602 I8
CD 6603 A7
BAT54 COL
NC GND
to ANALOG BOARD 6605 C6
2616
2617
470p
6602
22n
FOR P50 and Gemstar EPG 7600 B7

4
7601 C5
I I 7602 E6
7603 E7
JTAG_RSTN 7604 B9
7606 D13
7607 H7
* Not used (Provision only) 3139-243-36835_130-06_a2.eps 2007-07-17 7608 A5
F601 H9
F602 C2
F603 C8
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Digital: Power Supply (PS)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 1700 C1
1701 C2
5700 A3
5701 B3
1702 D2 5702 C3
1703 D1 5704 D3
1704 H6 5705 D2
7700
1705 H6 5706 D3
LD29150PT 1727 D14 5707 E2
5700
BLM31 F709 1728 E14 5708 E4
2 4 1731 F11 5725 H8
IN OUT +VDDR
50R F707
1 ADJ 5 3700 3701 (+2.5V)
1734 H10 5727 G8
INH 1735 H11 7700 A5
NC
3702
3703
22K
10K
1K0 1% 33R
A GND
A 2700 A4
2701 A6
7701 A4
7702 B4
47u 6.3V
1K0 1%
3704
2701
2702
100n
2700
470n
2702 A6 7705 E6
3
3766 * 22R
{HDMI_SCL(1),HDMI_SDA(1)} ITU_OUT_VSYNC 40FLT-SM2-TB(LF)(SN) 2703 B4 7706 H4
7701
BC847B 4710 F720 2704 B5 7707 H5
40
HDMI_SDA(1) F721 2705 C3 7710 C8
39
+1V2 HDMI_CEC_INTn
* 3765 22R 38 2706 C4 7711 C7
HDMI_SCL(1) F722 F700 C1
PNX_ITU_OUT(7:0) 37 2708 F6
3705
3706
15K
1K0
4740 4741
36 2709 F7 F701 D1
ITU_OUT_CLK 3141 22R F723 35 3V3STBY
2710 F5 F702 D1
34
PNX_ITU_OUT(0) F724 2711 F6 F703 D1
33
{HDMI_SCL(1),HDMI_SDA(1),PNX_SCL(1),PNX_SDA(1)} 32 2720 D12 F704 D1
MT1 MT2 PNX_ITU_OUT(1) F725 31 3115 H5 F705 E1
PNX_SCL(1)
30 3116 H4 F706 E1
B 4742 4743
5701
7702
NCP565D2TR4G PNX_SDA(1)
PNX_ITU_OUT(2) F726 29
28
B 3141 B13 F707 A4
BLM31 F710
PNX_ITU_OUT(3) F728 3700 A5 F709 A6
27
2
IN OUT
4
+1V2 +3V3 +5V F729 26 3701 A6 F710 B5
MT3 MT4 PNX_ITU_OUT(4) F730
50R 25 3702 A3 F711 C4
5 1 NC (+1.20V)
100u 6.3V
F731
+3V3 24 3703 A3 F712 D1
2K7 1%
ADJ NC
2703
3707
2704
PNX_ITU_OUT(5)
100u 6.3V
F732
6p8
10u 25V
3763-1 3763-2 23 3704 A5 F713 C1
2705 GND
2706
22
3K3 3K3
PNX_ITU_OUT(6) F733 3705 B3 F714 E5
21
20 3706 B3 F715 E7
6
PNX_ITU_OUT(7) F734 3707 B5 F716 F6
19
3708
1R0
3723-1 22R
18 3708 C5 F720 A13
PNX_FSCLK_OUT F736 17 3709 C5 F721 A13
3764
1K0
F711 16
C C
3709 3723-2 22R 3712 F6 F722 A13
PNX_SCK_OUT F737 15
from ANALOG BOARD 8K2 1% 14 3713 F6 F723 B13
3723-3 22R F738
5702 PNX_SD_OUT 13 3714 F7 F724 B13
2
1700
1701 BLM31
1 1 3723-4 22R
12 3715 G4 F725 B13
4729
4728
F700 BSN20 BSN20 F739 11
3V3D 1 +3V3 7711 7710 PNX_SPDIF_OUT 3716 G5 F726 B13
3V3D 2 2.0A F 50R 10
F713 3724-2 22R F740 3717 D11 F728 B13
3V3D 3 PNX_WS_OUT 9
3
*
F712 4734 3720 D8 F729 B13
3V3D 4 +3V3 +3V3 +3V3 8
F701 3724-1 22R F741 3721 D7 F730 B13
GND 5 PNX_PIO10_HDMI_IRQ 7
12VD
GND
6
7
F702
F744
+12V
5704
3K3 3763-3 ITU_OUT_HSYNC
3730
* 22R
3724-3 22R F742
6
5
3722 H5
3723-1 C12
F731 B13
F732 B13
GND
5VD
8
9
F703
1702 BLM31
+5V
3763-4 3K3
PNX_PIO25_HDMI_RSTN
3724-4 22R
PNX_SDA(0) * 3771 22R
F743
4
3
3723-2 C12 F733 C13
3717 10K % 3777 22R 3723-3 C12 F734 C13
3721
3720
GND 10 1A F 5705 50R +3V3 SDA_ABT 2
22R
22R
D GND
5ND
11
12
F747
F704
BLM18P
5NV PSCAN_RESETN PNX_SCL(0)
1 D 3723-4 C12
3724-1 D11
F736 C13
F737 C13
*
13 14 HDMI_SDA(1) 3772 22R 1727
60R to V_Buffer 3724-2 C12 F738 C13
HDMI_SCL(1)
+3V3 3731 10K %3778 22R To/From HDMI
3724-3 D11 F739 C13
4733
4714
2720
100p
SCL_ABT OPTION ONLY
B12B-PH-SM4-TBT(LF) 3724-4 D11 F740 C13
*
4730
4731
5706 3730 D11 F741 D13
1703 BLM18P 3731 D11 F742 D13
F705
5VSTBY 1 5VSTBY 3738-1 F10 F743 D13
F748 to ASP
GND 2 60R
3738-2 F10 F744 D1
F706
3V3STBY 3
F714 3738-3 F10 F747 D1
B3B-PH-K % For ABT HDMI
+3V3_VIP 3738-4 F10 F748 E1
# For 7570 HDMI only
3739-1 G10 F751 H6
E 7705
! For CEC HDMI
E 3739-2 G10 F753 H6
NCP565D2TR4G 3739-3 F10 F754 H6
5707 5708
BLM31 BLM31 F715 3739-4 F10 F755 H5
2 4 1728 3740 G10 F760 F10
IN OUT +1V8
3773 22R
50R 50R
5 1 NC (+1.80V) HDMI_CEC_INTn 1 3741 G10 F761 F10
100u 6.3V
ADJ NC {VIP_ITU0_IN(2:9),VIP_ITU0_IN_CLK,VIP_ITU0_IN_VAL,VIP_ITU0_IN_SOP,VIP_ITU0_IN_LOCK} 2 3742 G10 F762 F10
5K1 1%
2708
2709
100u 6.3V
HDMI_BE_CTRL 3774 22R
6p8
3712
10u 25V
3
GND To/From DTTM 3743 H9 F763 F10
2711
2710
ITU_OUT_HSYNC 3775 22R 4

3744 H9 F764 F10
1731 OPTION ONLY 3776 22R
5
ITU_OUT_VSYNC 3745 H10 F765 G10
3
3738-4 6
VIP_ITU0_IN(2) F760
3V3STBY 1 DB_656(0)
HLW6S-2C7
3746 I9 F766 G10
3713
3738-3 22R 2 GND 3747 I9 F767 G10
VIP_ITU0_IN(3) F761 3 DB_656(1)
F F716 3714 VIP_ITU0_IN(4)
22R 3738-2
F762
4 GND
5 DB_656(2)
! DVDR7570 F 3748 I9
3749 I9
F768 G10
F769 G10
5K1 1% 3738-1 22R 6 GND 3750 H9 F770 G10
VIP_ITU0_IN(5) F763 7 DB_656(3) 3751 H9 F771 H10
22R 3739-4 8 GND 3756 G9 F772 H10
VIP_ITU0_IN(6) F764 9 DB_656(4)
+3V3
22R
3757 G9 F773 H10
3739-3 10 GND
VIP_ITU0_IN(7) F765 11 DB_656(5) 3758 G9 F774 H10
22R 3739-2 12 GND 3759 I9 F780 H10
VIP_ITU0_IN(8) F766 13 DB_656(6) 3763-1 B8 F781 I10
BLM18P
3739-1 22R 14 GND 3763-2 B8 F782 I10
5727
VIP_ITU0_IN(9) F767
60R
15 DB_656(7)
22R
3763-3 D9 F783 I10
+5V +5V 3740 16 GND
VIP_ITU0_IN_CLK F768 17 DB_656_CLK 3763-4 D7 F784 I10
G * G
3756
3741 22R 18 GND 3764 C8 F785 I10
VIP_ITU0_IN_VAL F769
+3V3 +3V3 10K 19 DB_IN_HS 3765 A13 F786 I10
22R 20 GND 3766 A13 F787 I10
*
3757 VIP_ITU0_IN_SOP
3742
F770 21 DB_IN_VS
3771 D13 F788 I10
3715
3716
10K
10K
10K 22R 22 GND

VIP_ITU0_IN_LOCK
23 GND 3772 D13
+ + 3V3_DTT
*
3V3_DTT 3758 10K 24 GND 3773 E13
+ BSN20 BSN20
PNX_PIO7_SPDIF2_IN
4722 F771 25 NC 3774 F13
7706 + 7707 4723
& 1705 3743 26 NC 3775 F13
PNX_SDA(1)
& 3116 22R & 3115 22R + 1704 PNX_SDA(1)
* F772 27 I2C_DB_SDA
3776 F13
&4735
F753
F751
1
1
2 SCL_5V PNX_SCL(1) * 3744 22R
F773
28 GND
29 I2C_DB_SCL 3777 D13
PNX_SCL(1) 2 3 GND 22R 30 GND 3778 D13
+ 4736 F754
3 4 5V F774 4710 A13
H H
+5V 30FLT-SM2-TB(LF)(SN)
4 5 SDA_5V 5725 4714 D12
+4737 F755 BLM18P 3V3_DTT1
B4B-PH-K B5B-PH-K +3V3
4722 G10
4723 H10
4738
4739
60R
100K
100K
3750
3751
HTS_IRQN + &
1734 1735 4724 I10
15FMN-BMT-A-TFT
& 3722 09FMN-BMT-A-TFT 4725 I10
+5V 3745 F780 1 1 GND 4726 I9
10K PNX_UART_TXD(1) 2 2 DB_RXD
47R
4727 I10
3 3 GND
PNX_UART_RXD(1) 3746 47R F781
4 4 DB_TXD 4728 C9
3747 47R F782 4729 C7
PNX_PIO13_DTT_RTS_1 5 5 DB_CTS
4724 F783
3748
6 6 NC / GND 4730 D13
PNX_PIO14_DTT_CTS_1 47R F784 7 7 DB_RTS
4725 F785 4731 D13
8 8 NC / GND
I 4726 F786 9
10 NC
9 GND / DB_RESETN I 4733 D12
4734 C11
3759
3V3_DTT1 * 4K7 3749
4727 11 GND
12 NC
4735 H5
4736 H5
# APAC
F787
DTT_RESETN 13 DB_RESETN 4737 H5
from EJTAG 47R 14 GND
4738 H5
& HTS F788 15 GND
4739 H6
To/From DTTM
+ URD
16 17 4740 B1
OPTION ONLY 4741 B2
4742 B1
3139-243-36835_130-07_a2.eps 2007-07-17 4743 B2
1 2 3 4 5 6 7 8 9 10 11 12 13 14
Digital: External ADC
1 2 3 4 5 6 7 8 9 10 2800 B1
2801 B1
2802 C1
2803 C1
2804 D1
7803 2805 D1
MC78FC33H 2806 B3
F830 3V3SW 2807 A7
2 3
5VSTBY IN OUT 2808 A3
A +5V
5NV
COM A 2809 A4
330u 16V
5802 5803 2810 C4
2807
BLM18P 5V_MUX BLM18P
5NV_MUX 2811 C4
1
+5V
60R 60R 2812 D5
6.3V
2813 C5
2809
47u 6.3V
2814 D6
2808
47u
2815 D6
2816 C6
2817 C6
AUDIO_MUX5_SEL_A 2818 C7
2819 D3
AUDIO_MUX5_SEL_B 3804 C1
B 3V3SW B 3805 C2
5V_MUX 3806 C2
2800 3807 D1
AIN2R 3V3SW
3808 D2
3814
1R0
1u0 3809 D2
2801 2806 5801
AIN1R
5V_MUX
100n 3V3SW BLM18P 3810 D4
7800
3811 C4
GND
1u0 HEF4052B 100n 2810
16
2802 2818 60R +3V3_MUX 3812 D5
10 VDD
47u 6.3V
AINFR 0 0 100n 3813 C5
16
9 4X
3815
2816
2817
100n
47K
9
1u0 1 3
3811
7801-2
LM833D
VDDA
Φ VRPVDDD 3814 B6
3815 C6
8
6 5
100K
100K
100K
3804
3805
3806
G4 24-BIT AUDIO
C 12
0 MDX
1K0
6
7
PNX_FSCLK_IN
3820 A A
8
SYSCLK
ADC 7807
+3V3_MUX
C 3816 D6
3817 C8
14 13 22R 74LVC1G125GW
5
3818 C8
4
1 2811 2813 3813 ADC_SD0_OUT
15 3 13 3817 22R 2
2 VINR DATAO 3819 D8
11 4
3 100n 47u 6.3V 10K
2803
7804 1
EN
3820 C6
1 5NV_MUX 2 UDA1361TS
AIN2L 0 VREF PNX_SCK0_IN 3823 E8
5 3 11 3818 22R
3
1u0 1 BCK 4802 D9
2 2
2804
4 5V_MUX
2812 3812
1 4803 D6
AIN1L 3 VINL
VEE VSS PNX_WS0_IN 4804 E7
1u0 47u 6.3V 10K 3819 22R
7801-1 6 12 5801 B9
GND
7
2805 3810 8 LM833D SFOR WS

3 AUDIO_MUX6_SEL 5802 A3
AINFL
1 7
47u 6.3V
1u0 1K0 PWON 5803 A4
D 2
D
2814
100n
2815
7800 C3
100K
100K
100K
14
3807
3808
3809
2819 3816 MSSEL 7801-1 D4

47K VSSA VRN VSSD 7801-2 C4
100n
5NV_MUX 7803 A6
4803
15
10
A A A 7804 C7
A A
5NV_MUX 4802 7805 E8
GND 7806 E9
4804 +3V3
+3V3_MUX 7807 C9
3823 7806 F830 A6
4K7 74LVC1G125GW
A
5
2
VIP_SD0_OUT
4
GND
E 7805
1
EN
E
3
AUDIO_MUX6_SEL PDTC124EU
PNX_SD0_IN
F F
3139-243-36835_130-08_a3.eps 2007-07-17
1 2 3 4 5 6 7 8 9 10
Layout: Digital Top View
Digital Top View 3139-243-36834-132-01-a1.pdf 2007-04-12

Layout: Digital Bottom View
Digital Bottom View 3139-243-36834-132-01-a1.pdf 2007-04-12

HDMI: FAROUDJA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 0005 I8
1100 D13
3158 C5
3159 A1
1101 E13 3161 C14
7100-2
D_DATA(31:0) FLI2310-LF-BD
1102 E13 3162 C6
7100-3
FLI2310-LF-BD 1911 F14 3163 A1
DATA BUS 2100 B11 3164-1 H13
3V3D
9 8
CbCr(2:11)
D_DATA(0) 1 1
50 7100-4 2101 B11 3164-2 G13
0 SDRAM 17 30 FLI2310-LF-BD
D_DATA(23) 3170 D_DATA(1) 2 2 2102 B12 3164-3 G13
51
1
31 48 2103 B12 3164-4 G13
D_DATA(22) 3167 10R D_DATA(2) 52
3 3
11
VIDEO 126
3102
CbCr(2) 2106 F5 3165 D14
2 0 0
A D_DATA(21) 10R 3163 D_DATA(3) 53
37
4 4
62
12 127
47R 3104 CbCr(3)
A 2107 F5
2108 F6
3166 D5
3167 A1
3105 A_ADDR(0) 3 1 1
49 88
D_DATA(20) 3159 10R D_DATA(4) 5 VDD 5 3107 47R 2109 F6 3169 D14
3V3D 10R 54 13 130 CbCr(4)
3108 A_ADDR(1) 4
63 112
2 2 2110 F6 3170 A1
D_DATA(19) 10R 3155 D_DATA(5) 55 114 3211 1R0 SDRAM_CLK_F 6 6
14 131
47R 3110 CbCr(5) 2111 F6 3172 D14
3111 10R A_ADDR(2) 5 SDRAM_CLKIN 3 3
10R 69
7 7
128 47R 2112 F7 3173 B1
D_DATA(18) 3151 D_DATA(6) 56 111 3113 1R0 15 132 3114 CbCr(6)
10R 3115 6 SDRAM_CLKOUT 4 4 2113 F7 3175 D14
81 75 55 49 41 35 9 3 43 29 15 1 A_ADDR(3)
D_DATA(31:0)
81 146
D_DATA(17) 10R 3147 D_DATA(7) 8 8 47R 3117 2114 F7 3176 B1
VDDQ 10R 57 110 +1V8 18 133 CbCr(7)
VDD 3118 7 SDRAM_DQM DQM_F 5 5 2115 F7 3177 B1
POWER
A_ADDR(4) 89 193
D_DATA(16) 3145 10R 9 9 3120 47R
D_DATA(8) 58 109 CSN_F 19 134 CbCr(8) 2116 F7 3178 B1
10R 3121 8 SDRAM_CSN VSS 6 6
A_ADDR(5) 2117 H5 3179 B1
1V8D
2 25 97 16
D_DATA(24) 10R 3173 4
0
SDRAM
0
26 D_DATA(9) 59 108 BA0_F 10 1
20 135
47R 3123 CbCr(9) 2118 H5 3180 B1
BLM18P
1 1 3124 10R A_ADDR(6) 9 SDRAM_BA0 7 7
5 27 113 36
5100
D_DATA(25) 3176 10R 2 2 D_DATA(10) BA1_F 11 2 3126 47R 2119 H6 3181 C1
7
3 2M x 32 3
60 10R 3127
60
10 SDRAM_BA1
107 21
0 0
136 CbCr(10)
2120 H6 3182 C1
8 61 A_ADDR(7) 124 68
D_DATA(26) 10R 3177 4 0 4 CASN_F 12 3 47R 3129 2121 H6 3183 F1
B 10
5 2k-1
A 5 62
3130 10R A_ADDR(8)
D_DATA(11) 61
11 SDRAM_CASN
106 22
1 1
137 CbCr(11)
B 2122 H6 3184 F1
F100
10R 11 63 129 80 47R
D_DATA(27) 3178 6 6 D_DATA(12) RASN_F 13 4
13 64 10R 64 105 23 140 2123 H7 3185 H12
7 7 3133 A_ADDR(9) 12 SDRAM_RASN 2 2 not used
74 65 139 96
2124 H7 3186 G1
4u7 35V
D_DATA(28) 10R 3179 76
8 8
66 D_DATA(13) 65 104 WEN_F 14 VDDCORE 5
24 141 3132-4 1K5
2100
2101
100n
2102
100n
2103
100n
9 9 3136 10R A_ADDR(10) 13 SDRAM_WEN 3 3 2125 H7 3187 G1
77 24 147 123 3132-3 1K5
Y(2:11)
D_DATA(29) 3180 10R 10 10 15 6
79 D_DATA(14) 66 103 A_ADDR(0) 25 142 3132-2 1K5 2126 H7 3188 G2
11 10R 3139 14 0 4 4
80 22 BA0_F 194 138 3132-1 1K5 2127 H2 3190 H2
D_DATA(30) 10R 12 0 16 7
SDRAM
3181 82 BA 23 D_DATA(15) 67 102 A_ADDR(1) 26 143
13 1 3142 10R 15 1 5 5 2132 F8 3193 H4
83 BA1_F 198 197
D_DATA(31) 3182 10R 14 D_DATA(16) A_ADDR(2) 17 8 3144 2133 F8 3195 H4
85 16 DQM_F 10R 70 101 27 144 Y(2)
31
15
D
0
71
16 SDRAM_DATA 2
159 160
6 6 2134 F8 3196 H13
10R 16 47R
D_DATA(7) 3119 33 DQM 1 28 D_DATA(17) 71 100 A_ADDR(3) 1 1
28 145 3146 Y(3) 2135 F8 3197 H13
17 2 17 3 7 7
10R 34
18 3
59 162
2 2
161 47R 2136 F9 3198 F12
3116 A_ADDR(4) 3149
C D_DATA(6) 36
19 3150
D_DATA(18) 72
18 4
99 ITU_OUT_2(0) 29
0
148 Y(4)
C 2137 F9 3199 F13
PLL
37 68 SDRAM_CLK_F 166 165
D_DATA(5) 10R 3112 20 CLK D_DATA(19) A_ADDR(5) ITU_OUT_2(1)
47R 3153 2138 F9 3200 H12
39 67 3V3D 10R 73 98 32 149 Y(5)
40
21 CKE
20 3154 CSN_F
19 5
163 164
1 1 2139 F9 3201 I13
3109 10R 22 CS SDRAM_ADDR 3157 47R
D_DATA(4) 42 17 D_DATA(20) 74 95 A_ADDR(6) ITU_OUT_2(2) 33 150 Y(6) 2140 F10 3202 F12
23 WE 3158 10R 20 6 2 2
10R 45
24 CAS
18 WEN_F 158 157 47R 2141 F10 3203 I2
D_DATA(3) 3106 47 19 D_DATA(21) 75 94 A_ADDR(7) ITU_OUT_2(3) 34 151 3161 Y(7)
25 RAS 10R 3162 21 7 3 3 2142 H8 3204 I12
48 CASN_F 184 183
D_DATA(2) 3103 10R 26 D_DATA(22) A_ADDR(8) 1 1 ITU_OUT_2(4) 3165 47R 2143 H8 3206 H13
50 14 10R 76 93 35 152 Y(8)
51
27
21 3166 RASN_F
22 8
172 171
4 4 2144 H9 3207 G4
10R 3101 28 2 2 47R 3169
D_DATA(1) 53 30 D_DATA(23) 77 92 A_ADDR(9) ITU_OUT_2(5) 38 153 Y(9) 2145 H9 3208 G4
29 10R 23 9 5 5
10R 54
30 NC 57 175
3 3
174 47R 2146 H9 3209 H4
3100 3172
RESERVED
D_DATA(0) 56 69 D_DATA(24) 78 91 A_ADDR(10) ITU_OUT_2(6) 39 154 Y(10) 2147 H9 3210 H12
31 24 10 R_VDD 6 6
70 178 177
10R 3122 4 4 47R 3175 2148 H10 3211 A9
D D_DATA(8) 73 D_DATA(25) 79
25
185
R_VSS
186
ITU_OUT_2(7) 40
7 7
155 Y(11)
D 2150 I13 4100 D13
3125 10R 5 5 47R
D_DATA(9) D_DATA(26) 82 2151 I5 4101 E13
26
167 187 2152 I6 4103 E13
D_DATA(10) 10R 3128 D_DATA(27) 83
6 6
4100
VSSQ VSS 27 ITU_OUT_2(0:7) 2153 I7 5100 B12
169 168
D_DATA(11) 3131 10R D_DATA(28) 7 F104 1100 5105 F101 2154 H13 5101 F5
84 78 52 46 38 32 12 6 86 72 58 44 84
7103 28
182 R_VDD
+12V
BLM18P
2155 E12 5102 H5
D_DATA(12) 10R 8 200mA
not used
3134 MT48LC2M32B2P D_DATA(29) 85 not used 2156 E12 5104 H8
2155
100n
29
10R 2157 E12 5105 D13
D_DATA(13) 3137 D_DATA(30) 86 4101 not used
30 2158 F13 5106 E13
1V8D
D_DATA(14) 10R 3140 D_DATA(31) F106 1101 5106 F102 3100 D1 5107 E13
87
31 +5V
BLM18P
3101 D1 7100-1 F2
D_DATA(15) 3143 10R 350mA
3102 A14 7100-2 A11
E E
2156
100n
10R 3103 D1 7100-3 A8
4103 not used 3104 A14 7100-4 A12
ADDRESS BUS F110 F108 1102 5107 F103 F105 3105 A6 7102 F12
+3V3
BLM31
3106 C1 7103 D5
1.5A T 3107 A14 7104 I6
2157
100n
CONTROL BUS +3V3 3108 A6 F100 B12
R_VDD R_VDD
7100-1 2158 3109 C1 F101 D13
FLI2310-LF-BD 7102
74LVC1G125GW 3110 A14 F1017 H1
+3V3
5
100n
2 3111 A6 F102 E13
195 MISC 117
F115 3135 4 3112 C1 F103 E13
VO_CLK
not used
TEST_OUT1
1 HDMI 3113 A9 F104 D12
3184
3183
4K7
4K7
47R EN
BLM31
F 116
F
5101
3114 A14 F105 E14

50R
TEST_OUT0 1911
3
F1140 3115 A6 F106 E12
44
DEV_ADDR0 IN_SEL
41
F109 SDRAM FAROUDJA 3202
F1139
1 3116 C1 F108 E12
3V3D SDA0 2 3117 A14 F109 F6
43 181 22R
DEV_ADDR1 1 3198 3
F1137 3118 A6 F110 E12
4u7 35V
4u7 35V
SCL0 4
206 180
2107
100n
2108
100n
2111
100n
2135
100n
3119 C1 F1103 I14
2106
2109
100n
2110
100n
2112
100n
2113
100n
2114
100n
2115
100n
2116
100n
2132
2133
100n
2134
100n
2136
100n
2137
100n
2138
100n
2139
100n
2140
100n
2141
100n
2 22R 3199 5
not used
F1135
3186
3187
4K7
4K7
6 3120 B14 F1105 I14

3 176 22R
3 ITU_OUT(0) 3148-4
F1133
7 3121 B6 F1107 I14
RESERVED 8 3122 D1 F1109 H14
7 173 22R
4 ITU_OUT(1) 3148-3 9
F1131
10
3123 B14 F111 G4
208 179 3124 B6 F1113 H14
SDA0
SCL0
5 ITU_OUT(2) 3148-2 22R 11
F1129
12 3125 D1 F1115 H14
G 1
6
170
ITU_OUT(3) 22R 3148-1 F1127
13 G 3126 B14 F1117 H14
F111 14
5 118 3207 100R 3127 B6 F1118 H14
0 P_HSYNC ITU_OUT(4) 3164-4 22R 15
F112
+1V8 +3V3 F1125
16
3128 D1 F1119 H14
3188 4 119 3208 100R F1124
1 P_VSYNC 22R 3164-3 17 3129 B14 F112 G4
ITU_OUT(5) F1123
10R 18 3130 B6 F1121 H14
10 120
BLM18P
BLM18P
CTLOUT 2 ITU_OUT(6) 3164-2 22R 19 3131 D1 F1123 G14
F1121
5102
5104
3190 20 3132-1 C14 F1124 G14
156 121 22R
3V3D OE 3 ITU_OUT(7) 3164-1 21
F114 4K7 F113 F116
F1119
22
3132-2 B14 F1125 G14
PSCAN_RSTn 47 122 1V8D 22R 2154 F1118 3132-3 B14 F1127 G14
RESET_N 4 R_VDD 3196 23
100n F1117
3209 FSCLK12_OUT
not used
24 3132-4 B14 F1128 H14
42 125 22R
4u7 35V
4u7 35V
10u 16V
not used
TEST CLKOUT P_CLK 3200 F1115
25 3133 B6 F1129 G14
2127
2117
2118
100n
2119
100n
2120
100n
2121
100n
2122
100n
2123
100n
2124
100n
2125
100n
2126
100n
2142
2143
100n
2144
100n
2145
100n
2146
100n
2147
100n
2148
1n0
100R 3193 SCK12_OUT 26 3134 E1 F113 H6

H 90
TEST_IN SDATA
46
SDA0 22R 3197 F1113
27 H 3135 F12 F1131 G14
3195 10R SD_OUT 28
188 45 22R 3136 B6 F1133 G14
0 SCLK SCL0 3210 29
F1128
10R SPDIF_OUT 30 3137 E1 F1135 G14
189 196
1 0 22R 3206 31 3139 B6 F1137 F14
F1109
TEST WS12_OUT 32 3140 E1 F1139 F14
190 199 22R
F1017 2 1 3185 33
VO_CLK_2 F1107
34
3142 C6 F114 H2
115 200 +3V3 INT_HDMI
3 2 22R 3201 35 3143 E1 F1140 F14
7104 F1105
HDMI_RSTn 36 3144 C14 F115 F12
207 201 LF18ABDT 22R
3 3204 F1103
37 3145 B1 F116 H8
D1_IN F117 PSCAN_RSTn 38 3146 C14 F117 I7
2 202 1 3 22R
4 IN OUT +1V8 39
3147 A1 SW01 I9
not used
40
I 6 203 COM 41 42
I
2150
100p
5 3148-1 G13 SW02 I9
3148-2 G13 SW03 I10
192 204
47u 6.3V
6 0005 3148-3 G13

2
40FLZ-RSM2-R-TB(LF)(SN)
2153
2151
100n
2152
100n
3203 191 205 BRACKET 3148-4 G13
PSCAN_RSTn
7
10R 3149 C14
SW01 SW02 SW03 3150 C5
3151 A1
3153 C14
3154 C6
3155 A1
HDMI Columbus at CR 3139-243-32736-130_1.pdf 2006-02-17 3157 C14
1 2 3 4 5 6 7 8 9 10 11 12 13 14
HDMI: PROG SCAN DAC
1 2 3 4 5 6 7 8 9 10 11 12 13 1920 E13
1921-1 E12
F204 A9
F205 A12
1921-2 G12
1921-3 H12
2250 A6
2251 A7
+3V3 +2V5 2252 G4
2253 A9
+3V3 +5V
2254 A10
7250 4251 2255 A2
LF25CDT
2256 C3
A 1
IN OUT
3
5253
+3V3D_VDAC
5250 F204 5251 F205 A 2258 A1
not used BLM21
+5V_PS 2259 A2
4u7
COM 2260 B3
16V
4u7 35V
2261 B3
2255
100n
2259
2251
2250
100n
2258
100n
2253
100n
2254
4u7
2262 B3
47u
2
2263 B3
2260 2266 C2
220u 4V
2267 C4
2268 C2
2261 2269 D2
2270 D4
100n
B 2262
B 2271 D4
2272 D4
2273 D2
100n 2274 D4
2275 D6
2263 2276 D11
100n
2277 F11
2278 H11
2256 2280 G2
2281 G2
PSCAN_RSTn
10n 2282 F5
2284 D8
C 2266
C 2285 D9
2286 D10
+3V3D_VDAC
F201
2290 F8
47u 16V 2291 F9
2267
2292 F10
F202
2268 2296 H8
10n +5V_PS 2297 H9
1n0 3255 D8
+2V5 +2V5 +2V5 +2V5 +2V5 +2V5 2286 3256 F8
2269 2270 7251
5254 5255
AD8091ART
100n
3257 H8
5
3 3258 D8
100n 1n0 3266
1
3259
22R
3259 D6
D D
4u7 2u2
4 75R 1%
2273 F203 2274 3260 D5
3260
3255
2271
100n
2272
100n
3258
2284
2285
3265
3271
1K2
3261
10K
1K2
1K2
1K2
22p
22p
10K
2
3261 D5
220u 4V
2276
4254
3267
1K2
100n 100n
3262 D6
7253 3263 D5
41
10
56
3263
3264
ADV7320KSTZ
10K
10K
3264 D5
1
75R 1%
VAA
3262
2275
VDD_IO
47K
VDD
1n0
51 45 3265 D9
Not used
3291
ITU_OUT(0:7) 52
0 VIDEO COMP1
36 3266 D11
3268
1K2
1 COMP2
ITU_OUT(0) 53
2
ENCODER 1921-1 3267 D10
ITU_OUT(1) 54 50 YELLOW 3268 E10
BZX384-C4V7
ITU_OUT(2) 3 S_HSYNC
55 49 1
ITU_OUT(3) 4 S_VSYNC 3269 F8
58 S 48
6251
ITU_OUT(4) 59
5 S_BLANK
2 YKC21-3930 3270 F9
6
E ITU_OUT(5)
ITU_OUT(6)
60
61
7
8
P_HSYNC
P_VSYNC
23
24
P_HSYNC
P_VSYNC E 3271 D9
3272 F11
ITU_OUT(7) 62 25 3273 F10
9 P_BLANK
CbCr(2:11)
3274 E6
CbCr(2) 14 33
0 RESET 3274 Not used 3275 G2
CbCr(3)
CbCr(4)
15
16
1
44
SCL0
+5V_PS PSCAN 3276 G6
2 A 3278 10R 1920
CbCr(5) 17 43 SDA0 3277 G6
ANALOG BOARD
3 B 2292 F2001
CbCr(6) 18 42 7252-1 GND 3278 E6
4 C 10R AD8092AR F2002 1
CbCr(7) 26 C DAC 39
5 D 5256 5257 100n 2 Y 3279 F10
8
CbCr(8) 27 38 3 GND
CbCr(9) 28
6 E
37 1 3272 F2004 3 3280 H8
7 F 4u7 2u2 4 PB
CbCr(10) 29 4252 2 3281 G5
8 75R 1% F2006 5 GND
3282 G5
3256
CbCr(11) 30 32
2290
2291
3270
3294
3269
1K2
1K2
1K2
1K2
22p
22p
VO_CLK PR
F F
4
Y(2:11) 9 CLKIN_A 6
63 4253 10R 3283 G5
3273
1K2
CLKIN_B 7 GND
220u 4V
Y(2) 2 22
2277
4255
0 SCLK 3284 H5
Y(3) 3 21
Y(4) 4
1 SDA
19
P_CLK 3285 H5
2 I2C 07FMN-BMT-A-TFT 3286 H5
Y(5) 5 20 +3V3D_VDAC
not used
3 ALSB
75R 1%
Y(6) 6 47 +3V3D_VDAC 3287 H9
2282
Not used
15p
4 RSET1
Y(7) 7 Y 35
3279
3292
3288 H11
1K2
5 RSET2
Y(8) 8 31
6 RTC_SCR_TR 3289 H10
Y(9) 9 46 1921-2
not used
7 VREF WHITE 3290 H10

3277
3276
Y(10) 12
4K7
4K7
BZX384-C4V7
8 3291 E11
Y(11) 13 3
9
3292 F11
6252
3275 2280
34 4 YKC21-3930 3293 H11
not used
EXT_LF
2252
100n
3294 F9
G G
680R 3n9 DGND
AGND GND_IO
3295 H9
40
11
57
64
4250 G6
2281
4251 A2
4250
+2V5 Not used

820p
4252 F5
3281 3282 3283 4253 F5
+5V_PS 4254 D12
2K7 1% 10R 330R 1%
7252-2 4255 F12
5258 5259
AD8092AR 4256 H12
8
5 5250 A7
3284 3285 3286 7 3288
4u7 2u2 5251 A10
2K7 1% 10R 330R 1% 6 75R 1% 5253 A2
3257
3280
2296
2297
3287
3295
1K2
1K2
1K2
1K2
22p
22p
H
4
H 5254 D9
220u 4V
3289
2278
4256
1K2
5255 D9
5256 F9
5257 F9
75R 1%
5258 H9
Not used
3293
5259 H9
3290
1K2
1921-3 6251 E11
RED
6252 G11
BZX384-C4V7
5
6253 I11
6253
6 YKC21-3930 7250 A1
7251 D10
7252-1 F10
I I 7252-2 H10
7253 D3
Not used F2001 F12
F2002 F12
F2004 F12
F2006 F12
F201 C3
F202 C3
HDMI Columbus at CR 3139-243-32736-130_2.pdf 2006-02-17 F203 D3
1 2 3 4 5 6 7 8 9 10 11 12 13
HDMI: HDMI Tx
1 2 3 4 5 6 7 8 9 10 11 12 13 1300 H12
1930 A13
F305 A5
F306 C3
1931 I5 F307 H13
2300 A1 F308 B13
+5V +3V3 2301 A2 F3101 I6
2302 A3 F3103 I6
2303 A3 F3105 I6
2304 A3 F3107 I6
not used
BLM21
+3V3 2306 B5 F3109 I5
5305
7300
LM317MDT 1930
5303 F305 2307 B5 F311 A13
TX2+_1 F311
3 2
F301 5300 F302 +3V3A_HDMI_T 1 2308 B6 F3111 I5
IN OUT +3V3_PLL1_T BLM21 2 2309 B6 F3113 I5
47u 16V
TX2-_1 F312
120R 1%
BLM18A 3
A A
10u 16V
ADJ TX1+_1 F313 2310 B3 F312 A13
2315
100n
2316
100n
2314
47u 16V
47u 16V
4
2311 B3 F313 A13
2300
2329
100n
3305
2301
2302
100n
2304
100n
2303
5
TX1-_1 F314
1 6 2312 B3 F314 A13
TX0+_1 F315
7 2314 A5 F315 A13
120R 1%
+3V3_HDMI_T +5V 8 2315 A5 F316 A13
TX0-_1 F316
9
+3V3 TXC+_1 F317 2316 A6 F317 A13
3309
7307 10
5301 PCA9512DP 2317 D13 F318 B13
F303 11
TXC-_1 F318
2318 C1 F319 B13
8
5302 F304 +3V3_HDMI_T 12
BLM21 VCC2 VCC
+3V3_PLL2_T F308 13 2319 C1 F320 B13
47u 16V
3314
3319
3320
2334
100n
3316
2333
100n
10K
4K7
4K7
10K
BLM18A 14 2320 C2 F321 B13
10u 16V
5 TX_DDC_SCL F319
2306
2308
100n
2309
100n
2307
100n
390R 1%
ACC 15
TX_DDC_SDA F320 2321 C2 F322 B13
2310
100n
2312
100n
2311
16
2322 C2
3310
2330
1u0
17
B B
3361
3363
3365
3367
TX_DDC_SCL
+5V_HDMI 18 2323 C3
2 3
SCL SCL 19 2324 D6
OUT IN F321 20 21
7 6 TX_DDC_SDA 22 23 2325 I4
SDA SDA
GND 2326 H11
3362 V
3364 V
3366 V
3368 V
F322
2327 I11
4
DC1R019JDA
2328 I12
+3V3_HDMI_T 2329 A1
2330 B1
2333 B11
V
2334 B9
+1V8
3300 E10
5304 7303
F306 3301 E10
C BSN20 +5V
C
HDMI_RSTn
+1V8_HDMI_T 7302
BSN20 not used 3302 E10
BLM21
47u 16V
3303 E10
+3V3A_HDMI_T
+1V8_HDMI_T
+3V3_HDMI_T
SDA0
SCL0
+3V3_PLL2_T
+3V3_PLL1_T
3304 E10
2318
2320
100n
2323
100n
2319
100n
2321
100n
2322
100n
3305 A2
3306 E10
6305 BAV99W
6306 BAV99W
+3V3_HDMI_T
+3V3_HDMI_T
3313 3307 E10
3357 2317
47K 3308 E10
7301 3309 A2
74LVC1G08GW 4K7 100n
3318
3315
22R
3310 B2
5
1R0
1
HPD 4 3313 C6
2324 3314 B9
2
3324
3323
3317
1R0
1R0
1R0
D D
38
23
3315 D6
16
59
74
28
34
13
48
71
45
4
BZX384-C6V8
not used
not used
1n0
3316 B9
3355
3
4K7
AVCC CVCC18 IOVCC PVCC
3322
6301
44 40
47K
CSDA HDMI NC 3317 D5
43
3356
41
CSCL TRANSMITTER 19
3318 D6
CI2CA DSDA 3354 3319 B10
4K7 DSCL 20
42 RESET 47K 3320 B11
INT 17 INT_HDMI 3322 D13
66 18 HPD
P_CLK IDCK HPD 3323 D9
Y(0) 79 24
3325 3326 3324 D9
0 EXT_SWING +3V3_HDMI_T 3325 E9
Y(1) 78 1 4R7 470R 1%
Y(2) 77 2 TXC+ 27 3300 10R TXC+_1 3326 E9
Y(3) 76 26 3301 10R TXC-_1 3328 G2
3 TXC-
E CbCr(0)
CbCr(1)
75
70
4
5
TX0+
TX0-
30
29 3303 10R
3302 10R TX0+_1
TX0-_1 E 3329 G2
3332 G3
CbCr(2) 69 33 3304 10R TX1+_1
6 TX1+ 3333 G3
CbCr(3) 68 32 3306 10R TX1-_1
7 TX1-
Y(4) 67 8 TX2+ 36 3307 10R TX2+_1 3339 H6
Y(5) 65 35 3308 10R TX2-_1 3340 H6
9 TX2-
Y(6) 64 10 3341 H6
Y(7) 63 21
Y(8) 62
11 D RSVDL 3342 H7
12 7304 3343 I3
Y(9) 61 13
Y(10) 58 SII9030CTU 3344 H5
14
Y(11) 57 3345 H5
15
CbCr(4) 56 16 3346 H6
CbCr(5) 55 82
17 3347 H5
F CbCr(6)
CbCr(7)
54
53
18
19
83
84 F 3348 H5
CbCr(8) 52 20 85 3349 H6
CbCr(9) 51 21 86 3350 H6
CbCr(10) 50 87
22 3351 H11
CbCr(11) 49 88
23
89
3352 H11
3353 I11
Y(1)
Y(0)
1 VIA 90
CbCr(1)
CbCr(0)
HSYNC
2 VSYNC 91 3354 D9
92 3355 D5
80 DE 93 3356 D5
94
4300 3357 D12
3333
3328
3329
3332
5 95
10K
10K
10K
10K
SPDIF 3361 B12

4301 6 96
MCLK
G 4302
4303
12
11
SCK
WS
97
G 3362 B12
3363 B12
3364 B12
4304 10
9
SD0 3365 B12
SD1 +12V 3366 B12
8
81 GND_HS
SD2
7
SD3
3367 B12
AGND CGND IOGND PGND
3368 B12
4300 G6
22
39
25
31
37
3
15
46
60
73
14
47
72
+5V 4301 G6
7305
4302 G6
LE50ABD
4303 G6
3351
3344
3345
3346
3339
3340
4R7
22R
22R
22R
10K
10K
4304 G6
H H
200mA
1300
7306 3352 5300 A3
8
390R
3349
3350
3347
3348
3341
3342
22R
22R
22R
22R
10K
BC857BW VIN 5301 B5

1K0 F307
5 1 5302 B3
INHIBIT VOUT +5V_HDMI
P_HSYNC
5303 A5
4 5304 C1
2326
100n
BZX384-C6V8
NC GND
5305 A2
2u2 50V
P_VSYNC
2328
6304
2 3 6 7
6301 D13
SPDIF_OUT 6304 I13
6305 D10
F3111
F3113
F3109
F3101
F3107
F3105
F3103
FSCLK12_OUT
6306 D11
7300 A1
3343
2325
10K
10p
7301 D11
I I
SCK12_OUT
WS12_OUT
SD_OUT
7302 C9
1931
2327
3353
10K
1u0
7303 C10
7304 F8
13
12
11
10
9
8
7
6
5
4
3
2
1
13FMN-BMT-A-TFT 7305 H11

not used not used 7306 H10
7307 A9
F301 A2
F302 A3
F303 B5
HDMI Columbus at CR 3139-243-32736-130_3.pdf 2006-02-17 F304 B3
1 2 3 4 5 6 7 8 9 10 11 12 13
HDMI: COLUMBUS
1 2 3 4 5 6 7 8 9 2400 A7
2401 A7
2402 A7
7401 2403 A6
LF15ABDT
F401 F400
2404 A6
5400
2405 A6
Not used for DVDR9000H 1V5_COLUM 3 1
+3V3
BLM18P 2406 A6
COM 2407 A5
2408 A5
10u 16V
10u 16V
A A
2408
100n
2407
100n
2406
100n
2405
100n
2404
100n
2403
100n
2402
100n
2401
100n
2400
100n
2410
2409
2
2409 A8
ITU_OUT(0:7) ITU_OUT_2(0:7)
2410 A7
Jumper 2411 B7
4400-1 2412 B7
ITU_OUT(0) ITU_OUT_2(0)
2413 B7
ITU_OUT(1)
4400-2
ITU_OUT_2(1) 2414 B7
2415 B6
4400-3
ITU_OUT(2) ITU_OUT_2(2) 2416 B6
4400-4 2417 B6
ITU_OUT(3) ITU_OUT_2(3) F402 5401 2418 B6
3V3_COLUM +3V3
ITU_OUT(4) 4401-1 ITU_OUT_2(4) BLM18P 2419 B5
2420 D5
4401-2
B B 3400 D6
10u 16V
2419
100n
2418
100n
2417
100n
2416
100n
2415
100n
2414
100n
2413
100n
2412
100n
2411
4401-3 3401 D4
3402 D4
ITU_OUT(7) 4401-4 ITU_OUT_2(7) 3403 D1
3404 E1
3405 E5
3406 E5
4408 7400-1
VO_CLK VO_CLK_2
T6TU5XBG
3607 F2
3608 F2
L14 3609 F2
DQM
K15
RAS 4400-1 A2
K14 P12 4400-2 A2
CAS 1
C C
J14 R12
J15
CLK 2
P11
4400-3 B2
Not used for DVDR7300H P6
WE
0
3
4
5
P10
R10
4400-4 B2
4401-1 B2
3V3_COLUM 1V5_COLUM R6
1 6
P9 4401-2 B2
P5 7 P8 4401-3 B2
2
R5 R8
R1
3
DQ
8
R13
4401-4 B2
BLM18P
used
4 9 4408 C2
3V3_COLUM R2 R14
3401
5402
F403 not4K7
5 10
R3 R15 4409 D2
6 A 11
3V3_COLUM
3402
1V5_COLUM
2420
P3
7 12
P15 4410 D2
R4 N15
F404
8 13 4411 E1
P4 M14
3400
4K7
4K7 100n
R7
9 14
M15
4412 E1
10 15 4413 E2
D D
P7 L15
11 16
4414 F2
C4
C12
G3
G13
L13
M3
N3
N8
N11
N14
P13
B8
C7
C8
C11
D3
E13
H13
K3
N6
N9
N1
7400-2 VO_CLK
H1
CLKASA CLKASB
G1
VO_CLK_2 5400 A8
4409 T6TU5XBG 5401 B8
HDMI_RSTn
not used AVD B13 A1
4410 F405 G15
VDDS CTRL VDDC WEA WEB 5402 D5
PSCAN_RSTn DAVA DAVB 7400-1 C7
3V3_COLUM
3403 not used F406 ITU_OUT(0:7) ITU_OUT_2(0:7) 7400-2 D2

H15
CLKSEL DI9 DO9
4K7
ITU_OUT(7) B7
0 0
G2 ITU_OUT_2(7) 7401 A8
4413 F407 H14 C14 B9 F2
1 1 F400 A8
4411 A9 E2
3V3_COLUM 3404 not used F408 G14 D14 B10
2 2
E1
F401 A7
A0IIC 3 3 F402 B7
4K7 A10 4 YA D2
YB 4
3V3_COLUM A7 C15 B11 5 5 D1 F403 D4
656SEL
E E F404 D5
4412 A11 C2
6 6
B12 C1 F405 D2
3405 7 7
D15 A15 A12 B1
F409
F15
SDA SDA0 8 8 F406 D2
100R
F410 3406 F407 E2
E15 B15 A13
F411 SCL SCL0 VA
E14 100R F408 E2
F412
F413
F14 A14
HREF F409 E1
F410 E1
A2 M2
0 0 F411 E1
not used
A8 D4 B3 M1
3607
3608
3609
10K
not used 10K
10K
F414 1 1 F412 E1
F1 N2 ITU_OUT(0) A3 L2 ITU_OUT_2(0)
F415 2 2
H3 ITU_OUT(1) B4 3 UVB 3 L1 ITU_OUT_2(1) F413 E1
VSS
ITU_OUT(2) A4
4
UVA
4
K2 ITU_OUT_2(2) F414 F5
AVS ITU_OUT(3) B5 DO K1 ITU_OUT_2(3)
4414
5 5 F415 F5
F F
ITU_OUT(4) A5 DI J2 ITU_OUT_2(4)
M13
C10
C13
D13
N10
N12
N13
R11
6 6
B14
K13
P14
F13
J13
C3
C5
C6
C9
N4
N5
N7
R9
B2
E3
P2
P1
ITU_OUT(5) B6 J1 ITU_OUT_2(5)
F3
L3
J3
7 7
ITU_OUT(6) A6 H2 ITU_OUT_2(6)
8 8
F481 F482
F483 F484
HDMI Columbus at CR 3139-243-32736-130_4.pdf 2006-02-17
1 2 3 4 5 6 7 8 9
Layout: HDMI Top View
HDMI Columbus at CR Top View_8 3139-243-32736-132-a1.pdf 2007-05-10

Layout: HDMI Bottom View
HDMI Columbus at CR Bottom View_8 3139-243-32736-132-a1.pdf 2007-05-10

IC Internal Block Diagrams 3139 785 32801 8. EN 129
8. IC Internal Block Diagrams

8.1 Analog Board
IC7202 - CS4344 – Digital To Analogue Converter
BLOCK DIAGRAM
3.3 V or 5 V
Switched
Interpolation Multibit Capacitor Left
De-emphasis Filter ∆Σ Modulator DAC and Output
Filter
Switched
PCM Interpolation Multibit Capacitor Right
Serial Audio
Serial Filter ∆Σ Modulator DAC and Output
Input Interface Filter
Internal
Voltage
Reference
Figure 8-1
PIN DESCRIPTION AND CONFIGURATION
SDIN 1 10 AOUTR
DEM/SCLK 2 9 VA
LRCK 3 8 GND
MCLK 4 7 AOUTL
VQ 5 6 FILT+
Pin Name # Pin Description

SDIN 1 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.
2 De-Emphasis/External Serial Clock Input (Input) - used for de-emphasis filter control or external serial
DEM/SCLK
clock input.
3 Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio
LRCK
data line.
MCLK 4 Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters.
VQ 5 Quiescent Voltage (Output) - Filter connection for internal quiescent voltage.
6 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling
FILT+
circuits.
7 Left Channel Analog Output (Output) - The full scale analog output level is specified in the Analog Char-
AOUTL
acteristics specification table.
GND 8 Ground (Input) - ground reference.
VA 9 Analog Power (Input) - Positive power for the analog and digital sections.
10 Right Channel Analog Output (Output) - The full scale analog output level is specified in the Analog
AOUTR
Characteristics specification table.
� PIN CONFIGURATION
EN 130 8. 3139 785 32801 IC Internal Block Diagrams
IC 7101 - NJW2244M - 3-INPUT VIDEO SWITCH WITH 75Ω DRIVER

NJM2244L
BLOCK DIAGRAMNJM2244D
NJM2244M
� BLOCK DIAGRAM
Pin Connection
� INPUT CONTROL SIGNAL-OUTPUT SIGNAL
SW1 SW2 OUTPUT SIGNAL
L L VIN1
H L VIN2
L/H H VIN3
note): Input clamp Voltage is about 2/5 of Supply Voltage
Figure 8-2
PIN DESCRIPTION AND CONFIGURATION
� PIN CONFIGURATION
NJM2244L
NJM2244LNJM2244D
NJM2244M
� BLOCK DIAGRAM Figure 8-3
Pin Connection
� INPUT CONTROL
SW1 SW2
L L
� INPUT CONTROL SIGNAL-OUTPUT
H SIGN
L
L/H H
SW1 SW2 OUTPUT SIGNAL
note): Input clamp V
L L VIN1
8.2 Digital Board
IC7300 - TSB41AB1 - IEEE 1394a-2000 ONE-PORT CABLE TRANSCEIVER/ARBITER
BLOCK DIAGRAM
CPS
LPS Received Data
ISO Decoder/Retimer
Link
CNA† Interface
I/O
SYSCLK
LREQ TPA+
CTL0
TPA–
CTL1
D0
D1
D2
Cable Port
D3
D4 Arbitration TPB+
D5 and Control TPB–
D6 State Machine
D7 Logic
PC0
PC1
PC2
C/LKON
R0 Bias Voltage
R1 and
Current
TPBIAS Generator
Crystal
XI
Oscillator,
Transmit Data XO
PLL System,
PD Encoder FILTER0
and Clock
RESET FILTER1
Generator
† CNA output is only available in the 64-pin PAP package
Figure 8-4
PIN CONFIGURATION
PHP PACKAGE
(TOP VIEW)
PLLGND
FILTER1
FILTER0
PLLVDD
RESET
DGND
DGND
DVDD
DVDD
LREQ
XO
XI
48 47 46 45 44 43 42 41 40 39 38 37
SYSCLK 1 36 AGND
CTL0 2 35 AVDD
CTL1 3 34 R1
D0 4 33 R0
D1 5 32 AGND
D2 6 31 TPBIAS
TSB41AB1
D3 7 30 TPA+
D4 8 29 TPA–
D5 9 28 TPB+
D6 10 27 TPB–
D7 11 26 AGND
PD 12 25 AVDD
13 14 15 16 17 18 19 20 21 22 23 24
DV DD
PC0
PC1
PC2
SE
ISO
DGND
CPS
LPS
SM
C/LKON
TESTM
Figure 8-5
PIN DESCRIPTION
TERMINAL
TYPE I/O DESCRIPTION
NAME PAP NO. PHP NO.
AGND 32, 33, 39, 26, 32, 36 Supply – Analog circuit ground terminals. These terminals should be tied together to the
48, 49, 50 low-impedance circuit board ground plane.
AVDD 30, 31, 42, 25, 35 Supply – Analog circuit power terminals. A combination of high frequency decoupling
51, 52 capacitors near each terminal is suggested, such as paralleled 0.1 µF and 0.001
µF. Lower frequency 10 µF filtering capacitors are also recommended. These
supply terminals are separated from PLLVDD and DVDD inside the device to provide
noise isolation. They should be tied at a low-impedance point on the circuit board.
C/LKON 19 15 CMOS I/O Bus manager contender programming input and link-on output. On hardware reset,
this terminal is used to set the default value of the contender status indicated during
self-ID. Programming is done by tying the terminal through a 10-kΩ resistor to a high
(contender) or low (not contender). The resistor allows the link-on output to override
the input. However, it is recommended that this terminal should be programmed
low, and that the contender status be set via the C register bit.
If the TSB41AB1 is used with an LLC that has a dedicated terminal for monitoring
LKON and also setting the contender status, then a 1-kΩ series resistor should be
placed on the LKON line between the PHY and LLC to prevent bus contention.
Following hardware reset, this terminal is the link-on output, which is used to notify
the LLC to power up and become active. The link-on output is a square-wave signal
with a period of approximately 163 ns (8 SYSCLK cycles) when active. The link-on
output is otherwise driven low, except during hardware reset when it is
high-impedance.
The link-on output is activated if the LLC is inactive (LPS inactive or the LCtrl bit
cleared) and when:
a) the PHY receives a link-on PHY packet addressed to this node, or
b) the PEI (port-event interrupt) register bit is 1, or
c) any of the CTOI (configuration-time-out interrupt), CPSI
(cable-power-status interrupt), or STOI (state-time-out
interrupt) register bits are 1 and the RPIE (resuming-port
interrupt enable) register bit is also 1.
Once activated, the link-on output continues active until the LLC becomes active
(both LPS active and the LCtrl bit set). The PHY also deasserts the link-on output
when a bus reset occurs unless the link-on output would otherwise be active
because one of the interrupt bits is set (that is, the link-on output is active due solely
to the reception of a link-on PHY packet).
NOTE: If an interrupt condition exists which would otherwise cause the link-on
output to be activated if the LLC were inactive, the link-on output is activated when
the LLC subsequently becomes inactive.
CNA 3 N/A CMOS O Cable-not-active output. This terminal is asserted high when there is no incoming
bias voltage.
CPS 24 20 CMOS I Cable power status input. This terminal is normally connected to cable power
through a 400-kΩ resistor. This circuit drives an internal comparator that is used to
detect the presence of cable power. This terminal should be tied directly to DVDD
supply if application does not require it to be used.
CTL0 4 2 CMOS I/O Control I/Os. These bidirectional signals control communication between the
CTL1 5 3 TSB41AB1 and the LLC. Bus holders are built into these terminals.
D0 6 4 CMOS I/O Data I/Os. These are bidirectional data signals between the TSB41AB1 and the
D1 7 5 LLC. Bus holders are built into these terminals.
D2 8 6
D3 9 7
D4 10 8
D5 11 9
D6 12 10
D7 13 11
TERMINAL
DGND 17, 18, 63, 14, 46, 47 Supply – Digital circuit ground terminals. These terminals should be tied together to the
64 low-impedance circuit board ground plane.
DVDD 25, 26, 61, 21, 44, 45 Supply – Digital circuit power terminals. A combination of high-frequency decoupling
62 capacitors near each terminal is suggested, such as paralleled 0.1 µF and
0.001 µF. Lower frequency 10 µF filtering capacitors are also recommended.
These supply terminals are separated from PLLVDD and AVDD inside the device to
provide noise isolation. They should be tied at a low-impedance point on the circuit
board.
FILTER0 54 38 CMOS I/O PLL filter terminals. These terminals are connected to an external capacitor to form
FILTER1 55 39 a lag-lead filter required for stable operation of the internal frequency multiplier PLL
running from the crystal oscillator. A 0.1 µF ±10% capacitor is the only external
component required to complete this filter.
ISO 23 19 CMOS I Link interface isolation control input. This terminal controls the operation of output
differentiation logic on the CTL and D terminals. If an optional Annex J type isolation
barrier is implemented between the TSB41AB1 and LLC, the ISO terminal should
be tied low to enable the differentiation logic. If no isolation barrier is implemented
(direct connection), or TI bus holder isolation is implemented, the ISO terminal
should be tied high to disable the differentiation logic. For additional information
refer to TI application note Galvanic Isolation of the IEEE 1394-1995 Serial Bus,
SLLA011.
LPS 15 13 CMOS I Link power status input. This terminal monitors the active/power status of the link
layer controller and controls the state of the PHY-LLC interface. This terminal
should be connected through a 10-kΩ resistor either to the VDD supplying the LLC,
or to a pulsed output which is active when the LLC is powered (see Figure 9). A
pulsed signal should be used when an isolation barrier exists between the LLC and
PHY. (See Figure 10.)
The LPS input is considered inactive if it is sampled low by the PHY for more than
2.6 µs (128 SYSCLK cycles), and is considered active otherwise (that is, asserted
steady high or an oscillating signal with a low time less than 2.6 µs). The LPS input
must be high for at least 21 ns to guarantee that a high is observed by the PHY.
When the TSB41AB1 detects that LPS is inactive, it places the PHY-LLC interface
into a low-power reset state. In the reset state, the CTL and D outputs are held in
the logic zero state and the LREQ input is ignored; however, the SYSCLK output
remains active. If the LPS input remains low for more than 26 µs (1280 SYSCLK
cycles), the PHY-LLC interface is put into a low-power disabled state in which the
SYSCLK output is also held inactive. The PHY-LLC interface is placed into the
disabled state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the LCtrl
register bit is set to 1, and is considered inactive if either the LPS input is inactive
or the LCtrl register bit is cleared to 0.
LREQ 1 48 CMOS I LLC request input. The LLC uses this input to initiate a service request to the
TSB41AB1. Bus holder is built into this terminal.
PC0 20 16 CMOS I Power class programming inputs. On hardware reset, these inputs set the default
PC1 21 17 value of the power class indicated during self-ID. Programming is done by tying
PC2 22 18 these terminals high or low. Refer to Table 9 for encoding.
PD 14 12 CMOS I Power-down input. A high on this terminal turns off all internal circuitry except the
cable-active monitor circuits, which control the CNA output (64-terminal PAP
package only). Asserting the PD input high also activates an internal pulldown on
the RESET terminal to force a reset of the internal control logic. (PD is provided for
legacy compatibility and is not recommended for power management in place of
IEEE 1394a-2000 suspend/resume LPS and C/LKON features.)
TERMINAL
PLLGND 57, 58 41 Supply – PLL circuit ground terminals. These terminals should be tied together to the
low-impedance circuit board ground plane.
PLLVDD 56 40 Supply – PLL circuit power terminals. A combination of high-frequency decoupling
capacitors near each terminal is suggested, such as paralleled 0.1 µF and 0.001
µF. Lower frequency 10 µF filtering capacitors are also recommended. This supply
terminal is separated from DVDD and AVDD inside the device to provide noise
isolation. It should be tied at a low-impedance point on the circuit board.
R0 40 33 Bias – Current setting resistor terminals. These terminals are connected through an
R1 41 34 external resistor to set the internal operating currents and cable driver output
currents. A resistance of 6.34 kΩ ±1.0% is required to meet the IEEE Std
1394-1995 output voltage limits.
RESET 53 37 CMOS I Logic reset input. Asserting this terminal low resets the internal logic. An internal
pullup resistor to VDD is provided so only an external delay capacitor is required for
proper power-up operation (see power-up reset in the Application Information
section). The RESET terminal also incorporates an internal pulldown which is
activated when the PD input is asserted high. This input is otherwise a standard
logic input, and may also be driven by an open-drain type driver.
SE 28 23 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For
normal use this terminal may be tied to GND through a 1-kΩ pulldown resistor or
it may be tied to GND directly.
SM 29 24 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For
normal use this terminal should be tied to GND.
SYSCLK 2 1 CMOS O System clock output. Provides a 49.152-MHz clock signal, synchronized with data
transfers, to the LLC.
TESTM 27 22 CMOS I Test control input. This input is used in manufacturing test of the TSB41AB1. For
normal use this terminal should be tied to VDD.
TPA+ 37 30 Cable I/O Twisted-pair cable A differential signal terminals. Board traces from the pair of
positive and negative differential signal terminals should be kept matched and as
TPA– 36 29 Cable I/O short as possible to the external load resistors and to the cable connector.
TPB+ 35 28 Cable I/O Twisted-pair cable B differential signal terminals. Board traces from the pair of
positive and negative differential signal terminals should be kept matched and as
TPB– 34 27 Cable I/O short as possible to the external load resistors and to the cable connector.
TPBIAS 38 31 Cable I/O Twisted-pair bias output. This provides the 1.86 V nominal bias voltage needed for
proper operation of the twisted-pair cable drivers and receivers, and for signaling
to the remote nodes that there is an active cable connection.
XI 59 42 Crystal – Crystal oscillator inputs. These terminals connect to a 24.576-MHz parallel
XO 60 43 resonant fundamental mode crystal. The optimum values for the external shunt
capacitors are dependent on the specifications of the crystal used (see crystal
selection in the Application Information section). When an external clock source is
used, XI should be the input and XO should be left open, and the clock must be
supplied before the device is powered on.
IC7301 – TPS2051AD - CURRENT-LIMITED POWER-DISTRIBUTION SWITCHES
BLOCK DIAGRAM
TPS2041A
Power Switch
†
IN CS OUT
Charge
Pump
Current
EN‡ Driver
Limit
OC
UVLO
Thermal
GND Sense
† Current sense
‡ Active high for TPS205xA series
TPS2042A
Figure 8-6
OC1
PIN CONFIGURATION
GND Thermal
T
Sense
EN1‡TPS2041A, TPS2051A
D PACKAGE Driver
Current
Limit
(TOP VIEW)
Charge
Pump
†
CS OUT1
UVLO
GN
Power Switch
GND IN
1 8 CS
† OUT OUT2
IN Charge
Pump 2 7 OUT I
Current
INEN2‡
3
Driver
6
Limit
OUT OC2 EN1
EN† 4
Thermal
Sense
5 OC EN2
† Current sense
‡ Active high for TPS205xA series
Figure 8-7
TPS2043A, TPS2053A TP
PIN DESCRIPTION
TPS2041A and TPS2051A

TERMINAL
NO. I/O DESCRIPTION
NAME
TPS2041A TPS2051A
EN 4 – I Enable input. Logic low turns on power switch.
EN – 4 I Enable input. Logic high turns on power switch.
GND 1 1 I Ground
IN 2, 3 2, 3 I Input voltage
OC 5 5 O Overcurrent. Logic output active low
OUT 6, 7, 8 6, 7, 8 O Power-switch output
TPS2042A and TPS2052A

TERMINAL
NO. I/O DESCRIPTION
NAME
TPS2042A TPS2052A
EN1 3 – I Enable input. Logic low turns on power switch, IN-OUT1.
EN2 4 – I Enable input. Logic low turns on power switch, IN-OUT2.
EN1 – 3 I Enable input. Logic high turns on power switch, IN-OUT1.
EN2 – 4 I Enable input. Logic high turns on power switch, IN-OUT2.
GND 1 1 I Ground
IN 2 2 I Input voltage
OC1 8 8 O Overcurrent. Logic output active low, for power switch, IN-OUT1
OC2 5 5 O Overcurrent. Logic output active low, for power switch, IN-OUT2
OUT1 7 7 O Power-switch output
OUT2 6 6 O Power-switch output
IC7500 – SAA7136AE – MULTISTANDARD AUDIO/VIDEO DECODER
BLOCK DIAGRAM
IN1_Left Stereo OUT1_Left

Analog BUFFER Audio Audio OUT1_Right
IN1_Right
Output Stereo OUT2_Left
IN2_Left NF/Audio Stereo OUT2_Right
Format DSP MUX
DACs
IN2_Right
Front End
16-bit conversion
IN3_Left Stereo ADC dBx expander (***)
Audio Processing
IN3_Right I 2S I 2S
I2S
Volume control Sound
I2S Bass, Treble and Audio
Outputs
SPDIF Balance
I 2S I 2S
Sound Sound Decoder SRC
Audio SAICO
Inputs Analog Sound Input Dual FM/NICAM Incredible Sound
SPDIF
BTSC SPDIF
SSIF Control Unit EIAJ
VIP_Host_Audio VIP
audio
AUX Inputs FSW

FSW M 3-Bit
AV U AV/DC
D-C VIP
X ADC Status bits Video
SSIF & RGB(**)/YPbPr VBI Slicer Video Scaler Port D
AI40P
AI40N Analog 10-Bit Scaler Event Handler DVO_D_X
AI41 Video Video
Video Processing
AI42 Digital Video Task B S

AI43 Front End ADC
C
Comb Filter RAW VBI A P
S-video NAICO Decoder Soft D
LO Digital
AI31 Analog 10-Bit Mixer C Task A (Video) E S
AI32 Video Video 8-bit/
I H- V- R T
Dig.
Video Video
10-bit
AI33 Front End ADC Component PRE Scaler Output Output
Video CVBS Analog Scaler EDDI
Ports
Inputs Video
Processing
AI21 Analog 10-Bit
Input
AI22 Video Video
AI23 Front End ADC Control Scaler PLL ITU
Unit SDTV/HD VMI
CVBS H,V
AI11 Sync.
AI12
Analog 10-Bit Processing
AI13 Video Video Port C
IF_POS(*) Front End ADC
IF_NEG(*) DVO_C_X
low IF
Video CVBS (*)

Low IF
Digital Digital DAC
V_IOUTP
Data IF(*) Audio V_IOUTN
Inputs I2C Programming PHI DAC SSIF (*)
DI_A_x read back Register Array FIFO S_IOUTP
DI_B_x S_IOUTN
Dig. Video IN
Programming and Control
DI_E_x IRQ &

Initiator Main Control INT_A
Remote Control VIP_Host_Audio IR out

IR in
Receiver Remote Control
TS data Transmitter
Port A
(DI_A_x) TS/PS In VIP Host I2C Slave PHI
Port B
Processing
(DI_B_x)
2
VIP Host Port with I C Bus Silent PHI Bus
TS - Out & Audi - In I2C Bus
(*)only
SAA7136E, (**) only SAA7136E/AE/DE,
(***) only SAA7136E/AE/BE Programming and Control Ports
Fig.2 System Block Diagram of SAA7136
Figure 8-8
PIN CONFIGURATION
Table 1 Pin Configuration (BGA 256 top view)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
A AUX3A NC AUX2B AUX1A IN2_Left VDDA(3V3) OUT1_Left IF_AGC I2S_I_1_WS I2S_O_S RST_ VSSD(3V3) VIP_HCT VSSD VIP_D6 VIP_D5
OUT_N L
B AUX3B NC AUX2A IN3_Left IN2_Right VRPOS_ADC OUT1_Right NC VSSD SPDIF_I IR_OUT VDDD(3V3) VIP_CLK VDDD(3V3) VIP_D3 VIP_D4
C AGND1 VSYNC AUX1B VREF_ADC IN1_Left VRNEG_ADC VDDA(3V3) I2S_I_2_SD VDDD(3V3) SPDIF_O VDDD(1V8) GPIO_0 VIP_D7 VDDD(3V3) VSSD VIP_D2
D VDDA VDDA(1V8) VSSA IN3_Right IN1_Right VREF_DAC VDDD(1V8) I2S_I_2_SCK I2S_O_ VDDD(1V8) IR_IN VIP_RSN DI_E_7 PP_SEL VIP_D0 VIP_D1
(3V3) SD_AUX
E V_IOUTN V_IOUTP S_IOUTN S_IOUTP VSSA VSSA OUT2_Right I2S_I_2_WS I2S_O_ NC GPIO_1 VSSD VDDD(1V8) VDDD(3V3) VSSD DI_E_6
AMCLK
F AI11 IF_NEG IF_POS DAC_ VDDA(3V3) VREF0 OUT2_Left I2S_I_1_SD I2S_O_SCK VSSD VSSD DI_E_1 DI_E_2 DI_E_3 DI_E_4 DI_E_5
Bias
G AI13 AI12 VDDA(3V3) VSSA VSSA VDDA(3V3) VSSD I2S_I_1_SCK I2S_O_WS VSSD DI_B_VS DI_B_DQ DI_A_8 DI_A_9 DI_E_0 VDDD(3V3)
H AI23 AI22 AI21 VSSA VDDA(3V3) AI1D NC VSSD DI_B_HS NC NC NC NC NC NC VDDD(3V3)
J NC VDDA(1V8) VSSA VDDA(3V3) AI2D VSSA VDDA(3V3) NC VSSD DI_A_CLK VDDD(1V8) VSSD DI_B_5 DI_B_6 DI_B_7 DI_B_
CLK
K VSSA VSSA AOUT2 VDDA(3V3) AOUT1 RES_REF_V NC DI_A_2 DI_A_3 VSSD DI_B_0 DI_B_1 DI_B_2 DI_B_3 DI_B_4 VDDD(3V3)
L AI33 AI32 AI31 VDDA(3V3) VSSA AGND2 XTOUT SI_VSYNC DI_A_4 DI_A_ VSSD DVO_ODE DVO_DQ DVO_D_C VDDD(3V3) VSSD
LOCK V LK
M VSSA VSSA VDDA(3V3) AI3D NC NC D_CON_1 NC VSSD DI_A_VAL DVO_C_0 VSSD VDDD(3V3) VSSD DVO_VS GPIO_2
N AI41 AI40N AI40P VDDA(3V3) SDA INT_A D_CON_2 VSSD DI_A_5 VDDD(1V8) VDDD(1V8) VSSD DVO_C_6 DVO_D_7 DVO_CLK DVO_HS
_C
P NC AI43 AI42 TDO SCL_SILENT CE VDDD(1V8) DI_A_0 DI_A_6 VDDD(3V3) DVO_C_1 DVO_C_3 DVO_C_7 DVO_D_0 DVO_D_5 DVO_D_6
R VDDA(3V3) AI4D TCK TDI SDA_SILENT VSSA VDDA(1V8) DI_A_1 VDDD(3V3) VSSD DVO_C_2 DVO_C_4 VDDD(3V3) DVO_D_1 DVO_D_3 VSSD
T VSSA TRST_N TMS SCL NC XTALI XTALO VDDD(3V3) DI_A_7 DI_A_SOP VDDD(3V3) DVO_C_5 VSSD DVO_D_2 DVO_D_4 VDDD(3V3)
Analog Processing Pins Digital Processing Pins
Figure 8-9
8.3. HDMI Board

7253 1921
Y YUV
8bit ITU656
Progressive
27MHz Video DAC Pb
Cinch
ADV7320 Pr *Provision Only
1911 7400 7100
YPbPr 1920
0.5mm 10p FFC Connector
7P Analog
8bit ITU656 Columbus 8bit ITU656 Faroudja 20bit YCbCr FFC Board
27MHz T6TU5XBG 27MHz FL2310 Con
7304
I2C
HDMI Tx 1930
I2S SII9030CTU TDMS
SPDIF 19P
Addr Bits HDMI
7103 DDC Level Con
1931 Shifter
32bit SDRAM Buffer
1.0mm 13p FFC Con
MT48LC2M3282P
SPDIF I2S1
I2SØ I2S2
I2S3
Figure 8-10
8.3.1 IC7253 - ADV7320KSTZ - Multi-Format 216 MHz Video Encoder
HD PIXEL Y SHARPNESS &

INPUT DE- TEST- Y COLOR
ADAPTIVE
INTER- CR PATTERN CR COLOR PS 8X
FILTER CB COLOR
CLKIN_B LEAVE CONTROL 4:2:2TO HDTV 2X
4:4:4 DAC
CB
P_HSYNC\ DAC
P_VSY NC\ TIMING
CLOCK
P_BLANK GENERATOR CONTROL
DAC
& PLL
U UV SSAF RGB
S_HSYNC\ TIMING DAC
S_VSYNC\ V MATRIX
GENERATOR
S_BLANK
DAC
SD 16X
CB
CLK IN_A SYNC DAC
DE- TEST- DNR COLOR- LUMA & FS C CGMS
INS ER- 2XOVER-
INTER- CR PATTERN GAMMA CONTROL CHROMA SAMPLING MODULA-- WSS
LEAV E TION FILTERS
SD PIXEL TION
INPUT Y
Figure 8-11
PIN DESCRIPTION
Pin Name Input/Output Function

DGND G Digital Ground
AGND G Analog Ground
CLKIN_A I Pixel Clock Input for HD ( 74.25MHz O nly , PS O nly ( 27MHz), SD Onl y
(27MHz).
C LKIN_B I Pixel Clock Input. Requires a 27MHz reference clock for Progressive Sca n
Mode or a 74.25MHz (74.1758MHz) reference clock in HDTV mode. This
Clock is only used in dual Modes.
COMP1, 2 O Compensation Pin for DACs. Connect 0.1uF Capacitor from COMP pin to
VAA .
DAC A O CVBS/ GREEN/ Y / Y analog output.
DAC B O Chroma/ BLUE/ U / Pb analog output.
DAC C O Luma/ RED/ V / Pr analog output.
DAC D O In SD onlyu mode: CVBS/Green/Y analog outptu, in HD only mode and

simultaneous HD/SD mode: Y/Green [HD] analog output.
DAC E O In SD onlyu mode: Luma/Blue/U analog outptu, in HD only mode and

simultaneous HD/SD mode: Pr/Red analog output.
DAC F O In SD onlyu mode: Chroma/Red/ V analog outptu, in HD only mode and

simultaneous HD/SD mode: Pb/Blue [HD] analog output.
P_HSYNC I Video Horizontal Sync Control Signal for HD in simultaneous Sd/HD

mode and HD mode only.
P_VSYNC I Video Vertical Sync Control Signal for HD in simultaneous SD/HD mode and
HD mode only.
P_BLANK I Video Blanking Control signal for HD in simultaneous SD/HD mode and HD
mode only.
S_BLANK I Video Blanking Control S ignal for SD only.
S_HSYNC I Video Horizontal S ync Control S ignal for SD only.
S_VSYNC I Video Vertical Sync Control Signal for SD only.
Y9-0 I SD or Progressive scan/ HDTV input port for Y data.

Input port for interleaved Progressive Scan data. The LSB is set up
on pin Y0. For 8-bit data input LSB is set up on Y2.
C9-C0 I Pro gressive Scan/ H DTV input port :4:4 input mode this port is used for
the Cb[Blue/U] data. The LSB is set up on pin C0. For 8-bit data input LSB is
set up on C2.
S9-S0 I SD or Progressive Scan/HDTV input port for Cr [Red/V] data in 4:4:4 input
mode. LSB is set up on pin S0. For 8-bit data input LSB is set up on S2 .
RESET I This input resets the on-chip timing generator and sets the ADV7310/11
into Default Register setting. Reset is an active low signal.
R SET1,2 I A 3040 Ohms resistor must be connected from this pin to AGND and is used
to control the amplitudes of the DAC outputs.
SCLk I I2C Port Serial Interface Clock Input .

SDA I/O I2C Port Serial Data Input/Output .
ALSB I/O TTL Address Input. This signal sets up the LSB of the I2C address.
When this pin is tied low the I2C filter is activated which reduces noise on the
I2C interface.
VDD_IO P Power supply for digital i/ps and o/ps
VDD P Digital power supply
VAA P Analog power supply
VREF I/O Optional External Voltage Reference Input for DACs or Voltage Reference
Output (1.235V).
EXT_LF I External Loop filter for the internal PLL.
RTC_SCR_TR I Multifunctional Input: Real Time Control (RTC) input, Timing Reset input,
Subcarrier Reset input.
I2 C I This Input Pin must be tied High (V DD_IO ) for the ADV7310/ADV7311 to interfac e
over the I2 C port.
GND_IO
PIN CONFIGURATION
S _V SYNC
S_HSY NC
CLKIN_B
GND_IO
DGND
V DD
S1
S0
S9
S8
S7
S6
S5
S4
S2
S3
6 4 63 6 2 6 1 6 0 5 9 5 8 57 56 5 5 5 4 53 52 51 5 0 49
VDD_IO 1 48 S_BLANK
PIN 1
Y0 2 IDENTIFIER 47 RS ET 1
Y1 3 46 V RE F
Y2 4 4 5 COMP1
Y3 5 ADV7320
4 4 DAC A
KSTZ
Y4 6 4 3 DA C B
TOP VIEW
Y5 7 (Not to Scale) 4 2 DAC C
Y6 8 4 1 VAA
Y7 9 4 0 AGND
VDD 10 3 9 DAC D
DG ND 11 3 8 DAC E
Y8 12 37 DAC F
Y9 1 3 36 COM P2
C0 14 35 R SE T 2
C1 1 5 3 4 E XT_LF
C2 16 3 3 RES ET
17 1 8 1 9 2 0 21 2 2 2 3 2 4 2 5 2 6 2 7 2 8 29 30 3 1 32
RTC_S CR_TR
C8
C9
C5
C6
P _HSYNC
P_VS YNC
C7
A LSB
SDA
SCLK
P_B LA NK
I2C
C3
C4
C LK IN_A
Figure 8-12
8.3.2 IC7400 - T6TU5XBG - Columbus 2D/3D Comb filter and spatial / temporal noise reduction system
BLOCK DIAGRAM
CONTROL A(11:0) DQ(16:1)
CLKASA
Memory Interface Noise
HREF
Measurement
VA 656
Test
Generator
CLKASB
Pattern
Test
Generator
YVB(8:0)/
Do(9)
Mux
656 Encoder
Mux
Local Regression
Noise Reduction
656 Decoder
YA(8:0)/
PAL & NTSC
SEL656
SWAN 3D
3D Comb
Di(9)
&
WEB/DAVB
WEA/DAVA UVB(8:0)/Do(8:0)
Mux
UVA(8:0)/Di(8:0)
SEL656
SNDA, SNCL, SNRST

SNERT Interface
BST
SDA, SCL Interface
IIC Interface
A0IIC
TRST
TDO
TMS
TCK
TDI
Figure 8-13
PIN DESCRIPTION
Signal name Pin no. I/O Short description

WEB/DAVB A1 Out Write enable B / Data valid B
UVA0/Di0 A2 In UV input 0 / 656 Data Input 0
SEL656 A7 In Select 656
TST1 A8 In Test input 1.
YA2 A9 In Luminance input 2
VA A13 In Vertical synchronisation
HREF A14 In Horizontal reference signal
SDA A15 I/O IIC Serial Data
YB8 B1 Out Luminance output 8
VSS B2 Ground
UVA1/Di1 B3 In UV input 1 / 656 Data Input 1
YA0/Di9 B7 In Luminance input 0 / 656 Data Input 9
BISTEN B8 In Build In Self Test Enable
YA1 B9 In Luminance input 1
WEA/DAVA B13 In Write Enable input from picnic/656 Data input valid
VSS B14 Ground
SCL B15 In IIC Serial Clock
YB7 C1 Out Luminance output 7
YB6 C2 Out Luminance output 6
VSS C3 Ground
VDDS C4 3.3 V supply voltage
VSS C5 Ground
VSS C6 Ground

VDDC C7 1.5V Core supply voltage
VSS C9 Ground
VSS C10 Ground
VDDS C12 3.3 V supply voltage
VSS C13 Ground
SNDA C14 I/O Snert Data
SNRST C15 In Snert Reset
YB5 D1 Out Luminance output 5
YB4 D2 Out Luminance output 4
VDDC D3 1.5V Core supply voltage
N.C. D4
VSS D13 Ground
SNCL D14 In Snert Clock
TCK D15 In Boundary scan test, Test clock
YB3 E1 Out Luminance output 3
YB2 E2 Out Luminance output 2
VSS E3 Ground
VDDC E13 1.5V Core supply voltage
TMS E14 In Boundary scan test, Test Mode Select
TDO E15 Out Boundary scan test, Test Data Out
TST2 F1 In Test input 2
YB1 F2 Out Luminance output 1
VSS F3 Ground
VSS F13 Ground
TRST F14 In Boundary scan test, Reset
TDI F15 In Boundary scan test, Test Data In
CLKASB G1 Out Clock ASB
YB0/Do9 G2 Out Luminance output 0 / 656 Data output 9
VDDS G3 3.3 V supply voltage
VDDS G13 3.3 V supply voltage
A0IIC G14 In IIC address select
Reset G15 In Resets the 656-outputs and SDRAM Data I/Os to tri-
state and resets the (asynchronous) IIC transceiver. +
defauls. Reset is active low.
CLKASA H1 In Clock ASA
UVB8/Do8 H2 Out UV output 8 / 656 Data output 8
TST3 H3 In Test input 3
VDDC H13 1.5V core supply voltage

CLKEXT H14 In External clock input
CLKSEL H15 In External clock select
UVB7/Do7 J1 Out UV output 7 / 656 Data output 7
UVB6/Do6 J2 Out UV output 6 / 656 Data output 6
VSS J3 Ground
VSS J13 Ground
CLK J14 Out SDRAM Clock
WEN J15 Out SDRAM Write Enable Not. Active Low.
UVB5/Do5 K1 Out UV output 5 / 656 Data output 5
UVB4/Do4 K2 Out UV output 4 / 656 Data output 4
VDDC K3 1.5V core supply voltage
VSS K13 Ground
CASN K14 Out SDRAM Column Access Not. Active Low.
RASN K15 Out SDRAM Row Access Not. Active Low.
UVB3/Do3 L1 Out UV output 3 / 656 Data output 3
UVB2/Do2 L2 Out UV output 2 / 656 Data output 2
VSS L3 Ground
VDDS L13 3.3 V supply voltage
DQM L14 Out SDRAM Data mask
DQ16 L15 I/O SDRAM Data bit 16
UVB1/Do1 M1 Out UV output 1 / 656 Data output 1
UVB0/Do0 M2 Out UV output 0 / 656 Data output 0
VDDS M3 3.3 V supply voltage
VSS M13 Ground
DQ14 M14 I/O SDRAM Data bit 14
DQ15 M15 I/O SDRAM Data bit 15
AVD N1 PLL Supply Voltage
N.C. N2
VDDS N3 3.3 V supply voltage
VSS N4 Ground
VSS N5 Ground
VDDC N6 1.5V core supply voltage
VSS N7 Ground
VDDC N9 1.5 V core supply voltage
VSS N10 Ground
VSS N12 Ground
VSS N13 Ground

DQ13 N15 I/O SDRAM Data bit 13
AVS P1 PLL Ground
VSS P2 Ground
A7 P3 Out SDRAM Address bit 7
DQ7 P8 I/O SDRAM Data bit 7
VDDS P13 3.3 V supply voltage
VSS P14 Ground
A4 R1 Out SDRAM Address bit 4
DQ8 R8 I/O SDRAM Data bit 8
VSS R9 Ground
VSS R11 Ground
8.3.3 IC7100 - FLI2310 - Faroudja Digital Video Format Converter
BLOCK DIAGRAM
Port 2
8-bit Noise Reducer,
656 Input Input Processor Vertical and 16/20/24-bit
Deinterlacer, Frame Output
with Auto Sync Horizontal RBG/YCrCb
Rate Converter and Processor
and auto Adjust Scalers Digital Outputs
Port 1 SDRAM interface
8/16/24-bit
RGB/YCrCb
Input
Vertical and
Clock 2Mx32 Horizontal
Generation SDRAM Enhancers
PLLs (external)
Figure 9-25: FLI2310 – Simplified Internal Block Diagram
Figure 8-14
PIN CONFIGURATION Figure 3.1: Pinout Information
FIELD ID_PORT2
IN_CLK_PORT2
HSYNC_PORT2
DAC_GR_AVDD
DAC_VREFOUT
AVDD_PLL_BE2
VSYNC_PORT2
DAC_GR_AVSS
AVSS_PLL_BE2
AVDD_PLL_SDI
AVDD_PLL_BE1
AVSS_PLL_BE1
AVSS_PLL_SDI
AVDD_PLL_FE
AVSS_PLL_FE
DAC_VREFIN
DAC_AVDDG
DAC_AVDDR
DAC_G_OUT
DAC_AVSSR
DAC_R_OUT
DAC_AVSSG
DAC_AVDDB
DAC_AVSSB
DAC_B_OUT
DAC_COMP
DAC_PVDD
DAC_AVDD
DAC_AVSS
DAC_PVSS
DAC_RSET
PLL_PVDD
XTAL OUT
PLL_PVSS
DAC_VDD
DAC_VSS
VDDcore8
D1_IN_7
D1_IN_6
D1_IN_5
D1_IN_4
D1_IN_3
D1_IN_2
D1_IN_1
D1_IN_0
XTAL IN
VSScore
TEST2
TEST1
TEST0
VDD9
VSS
170
160
205
200
195
190
185
175
165
180
HSYNC1_PORT1 1 OE
VSYNC1_PORT1 155 G/Y/Y_OUT_7
FIELD ID1_PORT1 G/Y/Y_OUT_6
IN_CLK1_PORT1 G/Y/Y_OUT_5
HSYNC2_PORT1 5 G/Y/Y_OUT_4
VSYNC2_PORT1 G/Y/Y_OUT_3
FIELD ID2_PORT1 150 G/Y/Y_OUT_2
VDD1 G/Y/Y_OUT_1
VSS G/Y/Y_OUT_0
IN_CLK2_PORT1 10 VSS
B/Cb/D1_0 VDD8
B/Cb/D1_1 145 R/V/Pr_OUT_7
B/Cb/D1_2 R/V/Pr_OUT_6
B/Cb/D1_3 R/V/Pr_OUT_5
VDDcore1 R/V/Pr_OUT_3
VSScore 140 R/V/Pr_OUT_2
B/Cb/D1_5 VSScore
B/Cb/D1_6 VDDcore7
R/Cr/Cb Cr_0 R/V/Pr_OUT_0
R/Cr/Cb Cr_1 135 B/U/Pb_OUT_7
R/Cr/Cb Cr_2 B/U/Pb_OUT_6
R/Cr/Cb Cr_7 VSS
G/Y/Y_0 VDD7
VDD2 30 B/U/Pb_OUT_1
VSS B/U/Pb_OUT_0
G/Y/Y_1 125 CLKOUT
G/Y/Y_2 VSScore
G/Y/Y_3 VDDcore6
G/Y/Y_4 35 CTLOUT4
VDDcore2 CTLOUT3
VSScore 120 CTLOUT2
G/Y/Y_5 CTLOUT1
G/Y/Y_6 CTLOUT0
G/Y/Y_7 40 TEST OUT1
IN_SEL TEST OUT0
TEST 115 TEST3
DEV_ADDR1 SDRAM CLKIN
DEV_ADDR0 VSS
SCLK 45 VDD6
SDATA SDRAM CLKOUT
RESET_N 110 SDRAM DQM
VDD3 SDRAM CSN
VSS SDRAM BA0
SDRAM DATA(0) 50 SDRAM BA1
SDRAM DATA(1) SDRAM CASN
SDRAM DATA(2)
100
105 SDRAM RASN

85
90
95
70
80
65
75
55
60
SDRAM DATA(3)
SDRAM DATA(4)
SDRAM DATA(5)
SDRAM DATA(24)
SDRAM DATA(31)
SDRAM DATA(6)
SDRAM DATA(7)
SDRAM DATA(8)
SDRAM ADDR(6)
SDRAM DATA(10)
SDRAM DATA(12)
SDRAM DATA(13)
SDRAM DATA(14)
SDRAM DATA(16)
SDRAM DATA(17)
SDRAM DATA(18)
SDRAM DATA(21)
SDRAM DATA(25)
SDRAM DATA(26)
SDRAM DATA(27)
SDRAM DATA(28)
SDRAM DATA(9)
SDRAM ADDR(9)
SDRAM ADDR(8)
SDRAM ADDR(7)
SDRAM ADDR(5)
SDRAM ADDR(4)
SDRAM ADDR(3)
SDRAM ADDR(2)
SDRAM ADDR(1)
SDRAM ADDR(0)
SDRAM DATA(11)
SDRAM DATA(15)
SDRAM DATA(19)
SDRAM DATA(20)
SDRAM DATA(22)
SDRAM DATA(23)
SDRAM DATA(29)
SDRAM DATA(30)
TEST IN
SDRAM ADDR(10)
VSS
VDDcore3
VDDcore4
VDDcore5
SDRAM WEN
VDD4
VSScore
VDD5
VSS
VSScore
VSScore
Package: 208-pin PQFP

Note: The pinout of FLI2310, which does not have the integrated DACs, differs from the FLI230x only in
relation to the DAC related pins. The pin differences between
Figure 8-15 the FLI230x and FLI2310 are detailed in
following pin descriptions.
PIN DESCRIPTION
Pin Voltage Pull up/

No Pin Name I/O Type Tolerance Drive Pulldown Description
1 HSYNC1_PORT1 Input 5v Horizontal sync or reference -CTL1 of Port 1
2 VSYNC1_PORT1 Input 5v Vertical sync or reference -CTL1 of Port 1
3 FIELD ID1_PORT1 Input 5v Odd/Even Field identification -CTL1 of Port 1
4 IN_CLK1_PORT1 Input 5v Data Clock input -CTL1 of Port 1
5 HSYNC2_PORT1 Input 5v Horizontal sync or reference –CTL2 of Port 1
6 VSYNC2_PORT1 Input 5v Vertical sync or reference –CTL2 of Port 1
7 FIELD ID2_PORT1 Input 5v Odd/Even Field identification –CTL2 of Port 1
8 VDD1 Power 3.3 V - Power pin for IO
9 VSS Ground Ground
10 IN_CLK2_PORT1 Input 5v Data Clock input –CTL2 of Port 1
11 B/Cb/D1_0 Input 5v Port 1 – Digital video input (Blue/Cb/D1)
16 VDDcore1 Power 1.8 V - Power pin for core
17 VSS Ground Ground
21 R/Cr/CrCb_0 Input 5v Port 1 – Digital video input (Red/Cr/CrCb)
29 G/Y/Y_0 Input 5v Port 1 – Digital video input (Green/Y)
41 IN_SEL Output 5v 8 mA Output to select external video mux
42 TEST Input 5v Connect to Ground
43 DEV_ADDR1 Input 5v Device address setting 1
44 DEV_ADDR0 Input 5v Device address setting 0

45 SCLK I/O 5v 8 mA 2-wire serial control bus clock
46 SDATA I/O 5v 8 mA 2-wire serial control bus data
47 RESET_N Input 5v PU Reset
48 VDD3 Power 3.3 V – Power pin for IO
50 SDRAM DATA(0) Tristate I/O 5v 4 mA PD SDRAM data bus *
80 VDDcore4 Power 1.8 V – Power pin for core
90 TEST IN Input 5V Test input-Connect to ground

91 SDRAM ADDR(10) Tristate O/P 5v 8 mA SDRAM address bus *
104 SDRAM WEN Tristate O/P 5v 8 mA SDRAM write enable *
105 SDRAM RASN Tristate O/P 5v 8 mA SDRAM row address select *
106 SDRAM CASN Tristate O/P 5v 8 mA SDRAM column address select *
107 SDRAM BA1 Tristate O/P 5v 8 mA SDRAM bank select 1*
108 SDRAM BA0 Tristate O/P 5v 8 mA SDRAM bank select 0*
109 SDRAM CSN Tristate O/P 5v 4 mA SDRAM CS *
110 SDRAM DQM Tristate O/P 5v 8 mA SDRAM DQM *
111 SDRAM CLKOUT Output 5v 12 mA Clock out to SDRAM *
114 SDRAM CLKIN Input 5v Trace delayed SDRAM Clock in
115 TEST3 Input Test input – Connect to ground
116 TEST OUT0 Output Test output – leave open
117 TEST OUT1 Output Test output – leave open
Control signal output selectable as HSync1/
118 CTLOUT0 5v 8 mA
Tristate O/P CSync/HRef/Monitor coast
Control signal output selectable as
119 CTLOUT1 5v 8 mA
Tristate O/P VSync1/CRef/VRef/Film Indicator
Control signal output selectable as Monitor
120 CTLOUT2 5v 8 mA
Tristate O/P coast/HRef/VDD_en / HSync2
Control signal output selectable as Film
121 CTLOUT3 5v 8 mA
Tristate O/P Indicator/VRef/backlight_en/VSync2
Control signal output selectable as CRef/Field
122 CTLOUT4 5v 8 mA
Tristate O/P ID/CSync/Monitor coast
125 CLKOUT Tristate O/P 5v 12 mA Output data rate clock
126 B/U/Pb_OUT_0 Tristate O/P 5v 8 mA Digital video output – Blue/U/Pb

136 R/V/Pr_OUT_0 Tristate O/P 5v 8 mA Digital video output – Red/V/Pr
148 G/Y/Y_OUT_0 Tristate O/P 5v 8 mA Digital video output – Green/Y
156 OE Input 5v Output data enable for Digital video output
157 PLL_PVDD Power 1.8 V – Power pin for PLL pads
158 PLL_PVSS Ground Ground for PLL pads
159 AVSS_PLL_BE1 Ground PLL Ground
160 AVDD_PLL_BE1 Power 1.8 V – Power pin for PLL
161 AVDD_PLL_BE2 Power 1.8 V – Power pin for PLL
162 AVSS_PLL_BE2 Ground PLL Ground
163 AVSSPLL_SDI Ground PLL Ground
164 AVDDPLL_SDI Power 1.8 V – Power pin for PLL
165 AVDDPLL_FE Power 1.8 V – Power pin for PLL
166 AVSSPLL_FE Ground PLL Ground
167 R_VSS Ground Ground
168 R_VDD1.8 Power 1.8 V
170 Reserved - Leave open
171 R_VDD Power 3.3 V

188 TEST0 Input 5v Test pin – connect to ground
191 XTAL IN Input External parallel crystal oscillator
192 XTAL OUT Output External parallel crystal oscillator
195 CLK_PORT 2 Input 5v 4 mA Port 2 - Data Clock input
196 D1_IN_0 Input 5v 4 mA Port 2 - ITU-R BT656 digital data input
206 FIELD ID_PORT 2 Input 5v 4 mA Port 2 - Odd/Even Field identification
207 VSYNC_ PORT 2 Input 5v 4 mA Port 2 - Vertical sync or reference
208 HSYNC_PORT 2 Input 5v 4 mA Port 2 - Horizontal sync or reference
Note:1) * - The connection of these pins depends on the type of external SDRAM used. See Appendix 3
2) For 16/20 bit Y and muxed C output modes see Appendix 2 for pin configuration
8.3.4 IC7304 – Sil9030CTU-7 – HDMI Transmitter
BLOCK DIAGRAM
CSDA I2 C E-DDC DSDA

CSCL Slave Master DSCL
CI2CA Registers INT

----------------
Configuration Receiver Sense + Interrupt Logic HPD
Logic Block
RESET#
HDCP HDCP
Encryption Keys
Engine EEPROM
Video Data encrypted EXT_SWING

IDCK data
Capture / TXC±
D[23:0]
DE Gen /
4:2:2 to
4:4:4
CSC XOR PanelLink
HSYNC
656 TMDS TX0±
VSYNC Digital
Logic Core TX1±
DE Block TX2±
SPDIF
MCLK Audio Data audio data
SCK Capture
WS
SD[3:0]
Logic
Block
Figure 8-16
PIN CONFIGURATION
EXT_SWING
PGND1
PGND2
RSVDL
PVCC1
PVCC2
AGND
AGND
AGND
AVCC
AVCC
TXC+
TX2+
TX1+
TX0+
TXC-
TX2-
TX1-
TX0-
NC
24
23
22
21
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CI2CA 41 DSCL
20
RESET# 42 DSDA
19
CSCL 43 HPD
18
CSDA 44 INT
17
CVCC18 45 16 CVCC18
CGND 46 15 CGND
IOGND 47 14 IOGND
IOVCC 48 13 IOVCC
SiI 9030
D23 49 12 SCK
D22 50 11 WS
D21 51 80-Pin TQFP 10 SD0
D20
(Top View) SD1
52 9
D19 53 8 SD2
D18 54 7 SD3
D17 55 6 MCLK
D16 56 5 SPDIF
D15 57 4 CVCC18
D14 58 3 CGND
CVCC18 59 2 VSYNC
CGND 60 1 HSYNC
66
70
74
76
62
63
64
65
67
68
69
71
72
73
61
75
78
80
77
79
IOVCC
IOGND
CGND
D13
D12
D11
D10
IDCK
D8
D7
D6
D5
CVCC18
D4
D3
D9
DE
D2
D1
D0
Figure 8-17
277 (3X)
240
276 (4X)
274 (2X)
1008
185
EN 158
230
273
1003 259
9.
265
269 (4X)
261 (DVDR3570/90H EU) (3X)
263 (DVDR3570/90H AP/LATAM) (7X)
278 (DVDR3575/77/95/97H EU) (3X)
262 (DVDR3570/90H EU) (3X)
264 (DVDR3570/90H AP/LATAM)
279 (DVDR3575/77/95/97H EU) (3X)
270 (4X)
1007
Exploded View of the set
250
190 (DVDR3570/90H AP/LATAM,

3139 785 32801
180 DVDR3575/77/95/97H)

DVDR3575/77/95/97H)
257 (4X)
275
DVDR3575/77/95/97H)
258 (DVDR3570/90H EU) (3X)
281 (DVDR3575/77/95/97H &
DVDR3570H AP/LATAM) (2X)
DVDR3575/77/95/97H)
189
161
Figure 9-1
1001
253 (2X) 1004
254
268 (4X)
183
187
1002 (--1011) 1005

1002 (--1012)
252 (4X) 192 (DVDR359XH)
267 (2X)
122
272 (4X)
121
186
130
101
Exploded view & Service parts list
P001
191 (DVDR359XH) (4X)
271 (4X)
127
P002
110
184
260
255
188
256 (2X)
1002 (--1010) 193
125
124
126
251
181
123
128
182
UPDATE SCREWS COUNT & Exploded View 3139-249-40921-110-1-a2.pdf 2007-04-24
129 07 ADD INDICATION FOR DVDR359XH SPECIFIC ITEMS
04-24
Exploded view & Service parts list 3139 785 32803 9. EN 159
DVDR3570H/75/97 DVDR3590H/75/97
0110 313924415631 COVER TRAY 0110 313924416861 COVER TRAY
0180 313924126261 SPRING EMC 0180 313924126261 SPRING EMC
0181 313924126291 SPRING AV 0181 313924126291 SPRING AV
0185 313911426671 BUSH, AC CORD 0185 313911426671 BUSH, AC CORD
0190 313924416811 SHIELD HDMI 0190 313924416811 SHIELD HDMI
0193 313924160931 SPRING ESD DVDR3570H 0191 313924409101 HDD DAMPER
0230 313924126301 PLATE REAR 0193 313924160931 SPRING ESD DVDR3570H
0240 313924124232 COVER TOP 0230 313924126301 PLATE REAR
0271 252220098475 SCR PAN TORX ST BK #6-32X6 0240 313924124232 COVER TOP
0271 252220000027 SCR WAFER PH STZN BU 6/32X12
0341 242254901506 REMOTE CONTROL 0341 242254901506 REMOTE CONTROL
0345 242207098231 MAINSCORD IEC /97 only 0345 242207098231 MAINS CORD IEC /97 only
0345 242207098233 MAINSCORD AUS 7A5 1M8 VH BK B 0345 242207098233 MAINSCORD AUS 7A5 1M8 VH BK B
/75 only /75 only
0350 242207600718 CBLE CINCH 1M5 CINCH RDYEWH B 0350 242207600718 AV CABLE 1M5
0487 242207600885 CBLE IEC-M 1M47 IEC-F BK B 0487 242207600885 RF CONNECTING CABLE
1001 313924851681 ANALOG BOARD 1001 313924851681 ANALOG BOARD
1002 313924852031 FRONT BOARD 1002 313924852031 FRONT BOARD
1003 313924851712 PCBAS DIGI DVDR3570H AP BOARD 1003 313924851712 PCBAS DIGI DVDR3570H AP BOARD
1004 313924713532 PSU BOARD PIE 1004 313924713532 PSU BOARD PIE
1005 282206200172 HDD 3.5” 160GB WD1600AVBB-63SY 1005 282206200152 HDD 3.5” 250GB ST3250820ACE B
1006 313924889141 PSCAN HDMI BOARD 1006 313924889141 PSCAN HDMI BOARD
1007 313924800333 DRIVE D5.2 CLOSED 1007 313924800333 DRIVE D5.2 CLOSED
1008 282203100057 FAN 12VDC 1.2W 2850RPM B 1008 282203100057 FAN 12VDC 1.2W
8001 313924102151 CBLE VH 05P/140/05P VH 20ST BK 8001 313924102151 CBLE VH 05P/140/05P VH 20ST BK
8002 313911027881 CBLE PH 06P/180/06P PH 26ST BK 8002 313911027881 CBLE PH 06P/180/06P PH 26ST BK
8003 313924103801 CBLE EH 04P/140/04P LC-L UL 8003 313924103801 CBLE EH 04P/140/04P LC-L UL
8004 313924103761 CBLE EH 04P/280/04P LC-L UL 8004 313924103761 CBLE EH 04P/280/04P LC-L UL
8005 313911028311 CBLE PH 12P/280/12P PH 26ST BK 8005 313911028311 CBLE T PH 12P/280/12P PH 26ST BK
8006 310330890611 CWAS 03PH/03PH 220 BK AWG26 8006 310330890611 CWAS 03PH/03PH 220 BK AWG26
8007 313924102101 FFC FOIL 24P/220/24P BD 1MMP 8007 313924102101 FFC FOIL 24P/220/24P BD 1MMP
8012 313911035501 FFC FOIL 08P/180/08P 1MMP BD 8012 313911035501 FFC FOIL 08P/180/08P 1MMP BD
8013 310330890562 CWAS 05PH/05PH 340 5P BK 26S 8013 310330890562 CWAS 05PH/05PH 340 5P BK 26S
8017 313924102141 CBLE IDE 40P/340/40P IDE UL 8017 313924102141 CBLE IDE 40P/340/40P IDE UL
8018 313924102651 CBLE IDE 40P/380/40P IDE UL 8018 313924102651 CBLE IDE 40P/380/40P IDE UL
8019 242207600786 CBLE USB-A 0M3 PH 5P BK B 8019 242207600786 CBLE USB-A 0M3 PH 5P BK B
8026 313924102211 FFC FOIL 40P/140/40P BD 0.5MMP 8026 313924102211 FFC FOIL 40P/140/40P BD 0.5MMP
8030 313911027931 CBLE PH 07P/100/07P PH 26ST BK 8030 313911027931 CBLE PH 07P/100/07P PH 26ST BK
P001 314107942981 CAB FRONT ASSY P001 314107942981 FRONT CABINET ASSY
P002 314107936761 FRAME ASSY P002 314107936761 FRAME ASSY
EN 160 9. 3139 785 32803 Revision List
10 REVISION LIST
Version 1.0
* Initial Release
Version 1.1
* Adding information for DVDR3590H/97
* Deleting DVDR3570H/55/96 information
* Update Service Parts List
Version 1.2
* Adding diversity information
* Adding VFD display info while formatting HDD
Version 1.3
* Adding information for DVDR3590H/75

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HDD & DVD Recorder DVDR3570H/75/97

Contents Page Contents Page

©Copyright 2007 Philips Consumer Electronics B.V. Eindhoven, The Netherlands.

1. Technical Speciﬁcations and Connection Facilities

1.1 PCB Locations

Basic Engine Digital Board

Standby Board (Behind

1.2 General: Audio Performance:

Audio analogue Mono :

Tuning Principles: 1.5 Digital Inputs / Outputs

Input voltage Y : 1Vpp ± 3dB 1.6.1 SNR

Output voltage : 1.8Vrms ± 2dB Disc Media Speeds

Set Dimension W x H x D : 435 x 43 x 324 mm

1.9 Laser Output Power & Wavelength

Output power during reading : 1.0mW

Output power : 1.2mW

2. Safety Information, General Notes & Lead Free Requirements

2.1.1 General Safety 2.2.1 General

Note: Use of controls or adjustments or performance of

2.3 Lead Free Requirement • Special information for BGA-ICs:

• On our website www.atyourservice.ce.Philips.com you

 BGA-de-/soldering (+ baking instructions)

Due to lead-free technology some rules have to be respected by the

• Use only lead-free solder alloy Philips SAC305 with

A Connecting Recorder and TV B Connecting Recorder and TV

Television ( rear) Satellite dish/

AUDIO 1 AUDIO 2 S-VIDEO IN Country selection is

Finding the viewing channel D Press OK to start automatic analogue channel

Country Selection Previous Next

recording. To Hard Disk

F Press OK again to start copying.

4.1 Dismantling of the DVD Tray cover manually

Insulation Sheet Insulation Sheet

Figure 4-4: Front Panel Service Position

4.3 Dismantling of the Basic Engine

2 1) Remove 4 mounting screws as shown in ﬁgure 5 to

Figure 4-1: Unlock the tray loader

2) Remove the Tray cover 110 as shown in Figure 2.

Figure 4-2: Remove the tray cover

Figure 4-5: Basic Engine mounting screw

Figure 4-3: Unscrew the screws to detach front panel

Figure 4-6: Basic Engine Service Position

Figure 4-8: PSU Board Service Position

Figure 4-7: PSU remove mounting screws

Figure 4-9: Remove mounting screws for HDD

2) Flip over the HDD Assembly to see the mounting screws

Notes: Only the special type of screws as described in

4.6 Dismantling of HDMI Board 4.7 Dismantling of the Digital Board

Figure 4-10: Remove mounting screws for HDMI Board

2) Remove the HDMI Shield 190 for HDMI Board Service

Figure 4-11: HDMI Board Service Position.

Figure 4-14: Analogue Board Service Position (Rear Plate 230

Figure 4-13: Digital Board Service Position

5. Firmware Upgrading and Useful Firmware Hints, Diagnostic

5.1.1. Preparation to upgrade ﬁrmware

1. Unzip the zip-archive ﬁle

5.1.2. Procedure to apply the ﬁrmware upgrade:

1. Power up the set

Developer name: Royal Philips

5.2. Procedure for checking Development Version Info Screen

1) Power up the set

(c)PHILIPS 2006 Version Information:

5.3 Procedure for Formatting HDD drive