Professional Documents
Culture Documents
7.3 Reading the Data EEPROM Additionally, the WREN bit in EECON1 must be set to
Memory enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code
To read a data memory location, the user must write the execution (i.e., runaway programs). The WREN bit
address to the EEADR register, clear the EEPGD con- should be kept clear at all times, except when updating
trol bit of the EECON1 register and then set control bit, the EEPROM. The WREN bit is not cleared by
RD. The data is available on the very next instruction hardware.
cycle; therefore, the EEDATA register can be read by
After a write sequence has been initiated, EECON1,
the next instruction. EEDATA will hold this value until
EEADR and EEDATA cannot be modified. The WR bit
another read operation, or until it is written to by the
will be inhibited from being set unless the WREN bit is
user (during a write operation).
set. Both WR and WREN cannot be set with the same
The basic process is shown in Example 7-1. instruction.
At the completion of the write cycle, the WR bit is
7.4 Writing to the Data EEPROM cleared by hardware and the EEPROM Interrupt Flag
Memory bit, EEIF, is set. The user may either enable this
interrupt or poll this bit. EEIF must be cleared by
To write an EEPROM data location, the address must
software.
first be written to the EEADR register and the data writ-
ten to the EEDATA register. The sequence in
Example 7-2 must be followed to initiate the write cycle. 7.5 Write Verify
The write will not begin if this sequence is not exactly Depending on the application, good programming
followed (write 55h to EECON2, write 0AAh to practice may dictate that the value written to the
EECON2, then set WR bit) for each byte. It is strongly memory should be verified against the original value.
recommended that interrupts be disabled during this This should be used in applications where excessive
code segment. writes can stress bits near the specification limit.
8.2 Operation
Example 8-1 shows the instruction sequence for an 8 x 8
unsigned multiplication. Only one instruction is required
when one of the arguments is already loaded in the
WREG register.
Example 8-2 shows the sequence to do an 8 x 8 signed
multiplication. To account for the sign bits of the
arguments, each argument’s Most Significant bit (MSb)
is tested and the appropriate subtractions are done.
Wake-up if in
INT0IF Idle or Sleep modes
INT0IE
TMR0IF
TMR0IE
TMR0IP
(1)
RBIF
RBIE
RBIP
INT1IF Interrupt to CPU
PIR1<6:0> INT1IE Vector to Location
PIE1<6:0> INT1IP 0008h
IPR1<6:0>
INT2IF
PIR2<7:0> INT2IE
PIE2<7:0> INT2IP
IPR2<7:0>
GIEH/GIE
PIR3<7:0>
PIE3<7:0>
IPR3<7:0> IPEN
PIR4<2:0>
PIE4<2:0> IPEN
IPR4<2:0> GIEL/PEIE
PIR5<2:0> IPEN
PIE5<2:0>
IPR5<2:0>
High Priority Interrupt Generation
INT2IF
INT2IE
INT2IP
Note 1: The RBIF interrupt also requires the individual pin IOCB enables.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note 1: A mismatch condition will continue to set the RBIF bit. Reading PORTB will end the
mismatch condition and allow the bit to be cleared.
2: RB port change interrupts also require the individual pin IOCB enables.
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown