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2. Asynchronous protocal converter for Two phase Delay insensitive Global communication
access Efficiency
8. Fast enhancement of validation test sets for improving the Struct at Fault coverage of
RTL circuits
10. Fpga Implementation of FFT Algoritham For real time Applications and DSP application
Computations
14. VLSI Design Of Diminished-One Module 2N+1 Adder Using Circular CarrySelection
Number System
18. Desigining Efficient Online Testable Reversible AddersWith New Reversible Gate
19. Novel Area-Efficient FPGA Architecture For Fir Filtering With Symmetric Signal
Extension
25. A Fast VLSI Dessign Of Sms4 Cliper Based On Twisted BDDS-Box Architecture
26. An Improved RC6 Algorithm With the Same Structure Of Encryption and Decryption
28. A New Low Power Test Pattern Generator Using A Variable -Length Ring Counter
29. Power Optimization of Linear Feedback Shift Register for low power BIST
34. Low-Power Leading-Zero Counting And Anticipation Logic For High-Speed Floating
Point Unit
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