EEE 105 Lab Exercises 6 and 7

Multi-Cycle MIPS Processor I and II

1 Introduction
This document contains specifications for two lab exercises. Each exercise is worth 20 points. Therefore,
supporting all required instructions in this document will merit you 40 points. Take careful note of the
differences in coverage and deadline!

2 Specifications
You are to implement a multi-cycle processor that supports a subset of the MIPS instruction set.
The subset required for Lab 6 is given in Table 1. You may refer to Lab 5 specs for additional information
on the required instructions. (They are exactly the same set!) Note that for ANDI, ORI, and XORI, the
immediate is zero-extended.
For Lab 7, you are required to support the instructions in Table 2 on top of those already supported in
Lab 6. Additional information on Lab 7 instructions is provided in Sec. 2.1.
Again, in cases where the instruction encoding does not match any of the supported instructions, the
processor simple performs a NOP (No Operation) and does not change the processor state (i.e. no writes to
register file and memory) except for the PC which is incremented normally.
You may want to use your single-cycle processor as a starting point - i.e. ’slice’ it up and insert appropriate
registers. Alternatively, you may start with the library provided for Labs 6 and 7 (see files attached to UVLê
bins). In any case, please use the register file from the me6-7 library. You can check if you are using
the correct register file if you can see labels such as R01, R02, etc. above the registers. In controlling your
datapath, you are allowed - in fact, encouraged - to use one-hot encoding.

Table 1: Instructions to be supported for Lab 6.

Instruction [31:26] [25:21] [20:16] [15:11] [10:6] [5:0]
ADD 000000 rs rt rd XXXXX 100000
SUB 000000 rs rt rd XXXXX 100010
AND 000000 rs rt rd XXXXX 100100
OR 000000 rs rt rd XXXXX 100101
NOR 000000 rs rt rd XXXXX 100111
XOR 000000 rs rt rd XXXXX 100110
SLT 000000 rs rt rd XXXXX 101010
SLL 000000 XXXXX rt rd shamt[4:0] 000000
SRL 000000 XXXXX rt rd shamt[4:0] 000010
ADDI 001000 rs rt imm[15:11] imm[10:6] imm[5:0]
SLTI 001010 rs rt imm[15:11] imm[10:6] imm[5:0]
ANDI 001100 rs rt imm[15:11] imm[10:6] imm[5:0]
ORI 001101 rs rt imm[15:11] imm[10:6] imm[5:0]
XORI 001110 rs rt imm[15:11] imm[10:6] imm[5:0]

Table 2: Instructions to be supported for Lab 7.

Instruction [31:26] [25:21] [20:16] [15:11] [10:6] [5:0]
LW 100011 rs rt imm[15:11] imm[10:6] imm[5:0]
SW 101011 rs rt imm[15:11] imm[10:6] imm[5:0]
BEQ 000100 rs rt imm[15:11] imm[10:6] imm[5:0]
BNE 000101 rs rt imm[15:11] imm[10:6] imm[5:0]
J 000010 addr[25:21] addr[20:16] addr[15:11] addr[10:6] addr[5:0]

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2.1 Additional information for Lab 7
The LW instruction computes for the address in memory of the item to be loaded by adding the base
address and the offset. The register containing the base address is rs while the offset is encoded in the
imm field. The offset encoded in the imm field is a byte address. After computing for the address, the
corresponding data, which is 4 bytes long (1 word), is fetched from memory and is saved to register rt.
The SW instruction is similar to the LW instruction in terms of computing for the effective memory
address. The only difference is that instead of fetching from the data memory and storing to register rt, the
data stored in the register rt is written to the data memory, with the address specified by the computed
memory address. Data is also assumed to be 4 bytes long.
The BEQ instruction compares the contents of rs and rt. If the contents are not equal, program
flow proceeds normally. Otherwise, the next instruction executed is the instruction with address (PC + 4 +
branch offset), where the program counter (PC) is the address of the currently executing BEQ instruction.
The branch offset is specified in the imm field of the instruction encoding. However, unlike the LW and SW
instructions, the imm field in the BEQ instruction now specifies a word address instead of a byte address.
Take note that all memories to be used are byte-addressable; thus, you may need to perform additional
operations to consider this.
The BNE instruction executes exactly in the same manner as BEQ expect that the branching condition
is now when the contents of rs and rt are not equal.
The jump instruction J branches unconditionally to a certain instruction memory address. For the J
instruction, the PC is changed to a value of {PC[31:28], addr[25:0], 2’b00{ instead of the normal (PC
+ 4).

3 Bonus
If your Lab 7 multi-cycle datapath can also support interrupt handling, you earn 4 bonus pts.
A simplified block diagram of the interrupt handler logic is shown in Fig. 1. Make sure you provide the
logic necessary to drive the interrupt handler’s control signals properly. To ensure that the processor loads
the ISR code when an interrupt signal is encountered, PC should jump to address 0x8000 (the address space
allocated for the ISR is 0x8000 to 0xFFFC).When an ERET is encountered in the ISR, PC should then go
back to where it was right before going into the ISR.

Figure 1: Simplified interrupt handler logic.

To test for the ISR’s behavior, you will have to make two codes: one for the “main” code, and another
for the ISR. You should dump these two codes into their corresponding ROMs within the INST MEM block.
Make sure that you are able to demonstrate what happens during the ISR, and that the processor is actually
able to enter the ISR when an interrupt signal is encountered. Of course, you should also make sure that
the processor is able to exit the ISR and go back to whatever line of code it was implementing in the “main”
INST MEM.

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4 Test Environment
Similar to Lab 5, test your processor by supplying it with instructions to run (and an initial state of the
data memory, when necessary). To simulate running instructions in your processor, you need to dump the
instruction (and data) memory to a text file in hexadecimal format. In your MARS IDE, select File →
Dump Memory.

5 Submission
Now this is where things can get confusing so if you have any doubts, DO NOT BE AFRAID TO ASK!

5.1 Upload deadlines

The deadlines for uploading your submissions are indicated in their respective UVLê bins. Quick reference:
Lab 6 archive must be uploaded by April 20; Lab 7 archive must be uploaded by April 27.
Both deadlines are by lab end. These upload deadlines are NOT the same as the checking deadlines,
though!
You may use late credits, but risk losing your in-class demo points if are you unable to demo by checking
deadline.

5.2 Checking dates

You must sign-up for a checking slot.
Make sure that your submission is final, NOT DRAFT, before your checking time slot.

During checking, your submission should run without further modifications. It should be final; after
all, you have marked it final. If I do allow you to modify your submission after you have marked your
submission as final, that is my prerogative and done out of consideration for you. You are NOT entitled
to these concessions and should not rely on them nor demand that they be given to you. Please keep that
in mind. Any deductions I impose because you did not follow instructions are not subject to negotiation.
Q&A time should not be spent on debugging your submission.
There are two checking dates, April 13 and April 27. These are NOT open lab sessions, so attendance
will be checked during these dates. But what if you already had Labs 6 and 7 checked by April 13? Will
you have to show up on April 27 for nothing? Won’t there be any early submission bonus (ESB)? Table 3
presents different scenarios that will hopefully address such questions.

Table 3: Early submission scenarios. ’Checked’ means demo + Q&A was com-
pleted on that date. ’Submitted’ means submission archive is uploaded and
marked as final submission. ESB stands for early submission bonus. The ’date’
covers until end of lab session.

Date Lab 6 Lab 7 ESB Remarks

checked checked 5 Excused for April 27 session
checked submitted 4 Lab 7 checking on April 27
April 13 submitted submitted 3 Labs 6 and 7 checking on April 27
submitted - 1 Labs 6 and 7 checking on April 27
- submitted - No ESB. Must submit Lab 6 first.
submitted submitted 1 Labs 6 and 7 checking on April 27
April 20 submitted - - No ESB. Lab 6 upload deadline.
- submitted - No ESB. Must submit Lab 6 first.
April 27 Lab 7 upload deadline. Checking deadline for both Labs 6 and 7.

ESB for interrupt handling is +1 pt, if submitted by April 20 along with the rest of your Lab 7 datapath.

5.3 Deliverables
Upload one .zip archive for each lab exercise using the corresponding submission bins.

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 Even if you will have both Labs 6 and 7 checked at the same time, you still have to separate Lab 6 files
from Lab 7 files. This is because you are supposed to finish Lab 6 first before you work on Lab 7.
Each archive should include all logisim files (.circ) and auxiliary files (such as .asm files and hex dumps)
necessary to demo your work. Make sure that all the files within the archive are located in a flat structure,
with no subdirectories/folders containing the required files. The filename format for the archive should be
EEE105 ME5 <Surname> <Initial of given name>. Again, be reminded that demerits given to those who
fail to follow instructions are not subject to negotiation.

5.4 Grading
The grading breakdown for Labs 6 and 7 are given in Tables 4 and 5, respectively.

Table 4: Grading breakdown for Lab 6.

Item Points per item Subtotal
In-class demo + Q&A 4 4
ADD, SUB, AND, OR 1 4
NOR, XOR, SLT, SLL, SRL, ADDI, SLTI, ANDI, ORI, XORI 1.2 12
TOTAL 20

Table 5: Grading breakdown for Lab 7.

Item Points per item Subtotal
In-class demo + Q&A 5 5
LW, SW, BEQ, BNE, J 3 15
TOTAL 20

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