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EE141 Integrated Circuits2nd
Arithmetic Circuits
Full-Adder
A B
Sum
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
The Binary Adder
A B
Sum
S = A B Ci
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Express Sum and Carry as a function of P, G, D
VDD
Ci A B
A B
A
B
Ci B
VDD
A
X
Ci
Ci A S
Ci
A B B VDD
A B Ci A
Co B
28 Transistors
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
A Better Structure: The Mirror Adder
VDD
VDD VDD A
A B B A B Ci B
Kill
"0"-Propagate A Ci
Co
Ci S
A Ci
"1"-Propagate Generate
A B B A B Ci A
24 transistors
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Mirror Adder
Stick Diagram
VDD
A B Ci B A Ci Co Ci A B
Co
GND
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
The Mirror Adder
• The NMOS and PMOS chains are completely symmetrical.
A maximum of two series transistors can be observed in the carry-
generation circuitry.
• When laying out the cell, the most critical issue is the minimization
of the capacitance at node Co. The reduction of the diffusion
capacitances is particularly important.
• The capacitance at node Co is composed of four diffusion
capacitances, two internal gate capacitances, and six gate
capacitances in the connecting adder cell .
• The transistors connected to Ci are placed closest to the output.
• Only the transistors in the carry stage have to be optimized for
optimal speed. All transistors in the sum stage can be minimal
size.
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Transmission Gate Full Adder
P
VDD
VDD Ci
A
P S Sum Generation
A A P Ci
A P VDD
B B
VDD A
P
P Co Carry Generation
Ci Ci Ci
A
Setup P
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
One-phase dynamic CMOS adder
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
One-phase dynamic CMOS adder
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EE141 Integrated Circuits2nd
Arithmetic Circuits
One-phase dynamic CMOS adder
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
The Ripple-Carry Adder
A0 B0 A1 B1 A2 B2 A3 B3
S0 S1 S2 S3
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Inversion Property
A B A B
Ci FA Co Ci FA Co
S S
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Minimize Critical Path by Reducing Inverting Stages
A0 B0 A1 B1 A2 B2 A3 B3
S0 S1 S2 S3
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Carry Look-Ahead Adders
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EE141 Integrated Circuits2nd
Arithmetic Circuits
Carry-Lookahead Adders
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EE141 Integrated Circuits2nd
Arithmetic Circuits
Carry-Lookahead Adders
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Look-Ahead: Topology
Expanding Lookahead equations: VDD
Co k = G k + P k G k – 1 + P k – 1 Co k–2 G3
G2
G1
All the way:
G0
Co k = Gk + P k G k – 1 + P k – 1 + P 1 G 0 + P 0 Ci 0
Ci,0
Co,3
P0
P1
P2
P3
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Manchester Carry Chain
VDD
Pi
VDD
Pi
Ci Co
Gi
Co Gi
Ci
Di
Pi
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Manchester Carry Chain
VDD
P0 P1 P2 P3
C3
Ci,0
G0 G1 G2 G3
C0 C1 C2 C3
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Manchester Carry Chain
Stick Diagram
Propagate/Generate Row
VDD
Pi Gi Pi + 1 Gi + 1
Ci - 1 Ci Ci + 1
GND
Inverter/Sum Row
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Carry-Bypass Adder
P0 G1 P0 G1 P2 G2 P3 G3 Also called
Carry-Skip
Ci,0 C o,0 C o,1 Co,2 Co,3
FA FA FA FA
P0 G1 P0 G1 P2 G2 P3 G3
BP=P oP1 P2 P3
Ci,0 C o,0 Co,1 C o,2
FA FA FA FA
Multiplexer
Co,3
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Carry-Bypass Adder (cont.)
Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15
Setup tsetup Setup Setup Setup
tbypass
M bits
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Carry Ripple versus Carry Bypass
tp
ripple adder
bypass adder
4..8 N
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Carry-Select Adder
Setup
P,G
Carry Vector
Sum Generation
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Carry Select Adder: Critical Path
Bit 0–3 Bit 4–7 Bit 8–11 Bit 12–15
Setup Setup Setup Setup
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Linear Carry Select
Bit 0-3 Bit 4-7 Bit 8-11 Bit 12-15
(1)
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Square Root Carry Select
Bit 0-1 Bit 2-4 Bit 5-8 Bit 9-13 Bit 14-19
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Adder Delays - Comparison
50
40 Ripple adder
30
Linear select
20
10
Square root select
0
0 20 40 60
N
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
“O” Operator
Definizione
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Properties of the “O” operator
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Properties of the “O” operator
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Group Generate and Propagate
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Group Generate and Propagate
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Group Generate and Propagate
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Look-Ahead - Basic Idea
A0 , B 0 A1, B1 ••• AN-1, BN-1
Ci,0 P0 Ci,1 P1
Ci, N-1 PN-1
S0 S1 ••• SN-1
Co k = f A k B k Co k–1 = G k + P k Co k –1
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Logarithmic Look-Ahead Adder
A0 F
A1 A2 A3 A4 A5 A6 A7
A0
tp N
A1
A2
A3
F
A4
A5
A6 tp log2(N)
A7
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Brent-Kung BLC adder
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Folding of the inverse tree
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EE141 Integrated Circuits2nd
Arithmetic Circuits
Folding the inverse tree
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Dense tree with minimum fan-out
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Dense tree with simple connections
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Carry Lookahead Trees
Co 0 = G 0 + P 0 Ci 0
Co 1 = G 1 + P 1 G 0 + P 1 P 0 Ci 0
Co 2 = G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C i 0
= G 2 + P 2 G 1 + P 2 P 1 G 0 + P 0 Ci 0 = G 2:1 + P2:1 C o 0
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
© Digital
(A0, B0) S0
(A1, B1) S1
(A2, B2) S2
(A3, B3) S3
(A5, B5) S5
(A6, B6) S6
(A7, B7) S7
(A8, B8) S8
(a 1, b 1) S1
(a 2, b 2) S2
(a 3, b 3) S3
(a 5, b 5) S5
(a 6, b 6) S6
(a 7, b 7) S7
(a 8, b 8) S8
(a 10, b 10 ) S 10
(a 11, b 11 ) S 11
(a 12, b 12 ) S 12
(a 13, b 13 ) S 13
(a 14, b 14 ) S 14
(a 15, b 15 ) S 15
Arithmetic Circuits
© Digital
(a 0, b 0) S0
(a 1, b 1) S1
(a 2, b 2) S2
(a 3, b 3) S3
(a 5, b 5) S5
Sparse Trees
(a 6, b 6) S6
(a 7, b 7) S7
(a 8, b 8) S8
(a 9, b 9) S9
(a 10 , b 10 ) S 10
(a 11 , b 11 ) S 11
(a 12 , b 12 ) S 12
16-bit radix-2 sparse tree with sparseness of 2
(a 13 , b 13 ) S 13
(a 14 , b 14 ) S 14
(a 15 , b 15 ) S 15
Arithmetic Circuits
© Digital
(A0, B0) S0
(A1, B1) S1
(A2, B2) S2
Brent-Kung Tree
(A4, B4) S4
Tree Adders
(A5, B5) S5
(A6, B6) S6
(A7, B7) S7
(A8, B8) S8
(A9, B9) S9
VDD
Clk
G i = a i bi
Clk
P i = a i + bi ai
ai bi
bi
Clk
Clk
Propagate Generate
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Example: Domino Adder
VDD
VDD
Clkk Clkk
Pi:i-2k+1 Gi:i-2k+1
Pi:i-k+1 Pi:i-k+1
Gi:i-k+1
Pi-k:i-2k+1 Gi-k:i-2k+1
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Example: Domino Sum
VDD VDD Keeper
Clk Clkd
Sum
Gi:0
Clk Si0
Clkd
Clk
Gi:0
Si1
Clk
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits
Adders – Summary
© Digital
EE141 Integrated Circuits2nd
Arithmetic Circuits