TOSHIBA ‘TMPZB4C30A TMPZ84C30AP-6 / TMPZ84C30AM-6 / TMPZ84C30AT-6 TMPZ84C30AP-8 TLCS-Z80 CTC : COUNTER TIMER CIRCUIT 1, GENERAL DESCRIPTION AND FEATURES ‘The TMPZ84C30A (hereinafter referred to as CTC) is CMOS version of 280 CTC and has been designed to provide low power operation. The TMPZ84C30A is fablicated using Toshiba’s CMOS Silicon Gate Technology. ‘The principal functions and features of the CTC are as follows. (1) Compatible with the Zilog 280 CTC. (2) Low power consumption. 4mA Typ. (@5V @6MHz) ~- 'TMPZ84C30AP-6/AM-G/AT-6 5mA Typ. (@5V @8MHz) ~~ 'TMPZ84C30AP-8 10HA Max. (@5Y, Stand-by) (3) DC to 6MHzoperation ~- TMPZ84C30AP-6/AM-6/AT-6 DC to 8MHzoperation ~: 'TMPZ84C30AP-8 (4) Single 5V power supply and single-phase clock. 5V 410% (6MHz VERSION) 5V + 5% (8MHz VERSION) (3) Capable of driving Darlington transistors. (6) Four independent counter/timer channels each of which is capable of independently selecting Timer Mode and Counter Mode. (7) Each channel is provided with a prescaler to divide system clock into 16 or 256. (8) Built-in interrupt control logical operation circuit allows priority processing of interrupt in Daisy-chain structure and automatic loading of 8 bit interrupt vector on the system bus. (9) Four channels occupy 4 successive positions in the Daisy-chain structure. Most significant channel is Channel 0 and least significant channel is Channel 3. (10) In both modes, at the zero count, the content of the time constant register is automatically loaded on the down counter, (11) In either Counter Mode or Timer Mode, the content of the down counter is readable by the microprocessor (hereinafter referred to as MPU). (12) Interrupt function available in 280 MPU Mode 2. Mpuze0-197TOSHIBA TMP284C30A (13) _In Timer Mode, the timer operation is selectable at the rise or fall of the starting trigger. In addition, in Counter Mode the decrement (-1) of the content of the down counter either at the rise or fall of external clock is selectable. (14) Programming to generate interrupt by zero count by the down counter in each channel is possible. 40 pin DIP package, 40 pin SOP, 44 pin PLCC package. Note: 280 is a trademark of! log Inc., U.S.A. MPUZ80-198TOSHIBA ‘TMPZ84C30A 2. PIN CONNECTIONS AND PIN FUNCTIONS 2.1 PIN CONNECTIONS (Top View) ‘The pin connections of the CTC are as shown in Figure 2.1 and Figure 2.2. ofr \7 a bo, ¥BSYRSaRRRY os2 » io, eaanen 263 25 Bo BSUS y Paaiaaiaa oe 25 Bo, wsqes 7 33 eo ne vats 2 Ave wai 6 @ Pi beer TOES omemane? PUIG gor yep 20770517 Yarstacsntes22 FICLAMTG ned tt 35: B cueteeo zero; a Twrenceara 21 Fleuerne, 20701 7 12 twrzaacaoars 38 Ne rehton 23 3 Revere: 2710, 3 zo Heme, “eo dia ap cuertrer TOR 10 9 cy, ned 48 a beuwmes ods 2 Fos ode pac i oo Neg 19 bes wrG 2 17 RESET 18192021 22232425262728 eid ws be wide 15 lax oyepeegeeee - eevopestpgy Figure 2.1. DIP, SOP Pin Connections Figure 22 44-Pin PLCC Package 2.2. PIN NAMES AND FUNCTIONS VO pin names and functions are as shown in Table 2.1 Table 2.1. Pin Names and Functions (1/2) Number |inpuvOutput| Pin Name | Number |mputlOus Function rr) vo~o7 | 8 ate |Sbitbidirectional databus The read signal FT 1 Input | This signal is used in combination with TORQ and CE signals for [transfer of data and chaanel control words between MPU and CTC. 2c/700 The Zero CounvTimer Out signal. In either the Timer mode, or ~ 1 Output | counter mode, pulses are output from these pins when the down zeTo2 counter has reached zero. / WO request signal oR + | Input This signal is used in combine with RD and TE signals for transfer of data and channel control words between MPU and CTC [interruption enabie output Controls interruptions by subordinate peripheral S's in the Daisy- 10 1 Output |chain structure. This terminal becomes H level only when the IEl terminalis at H level and MPU is not providing the intertuption [service to channels in CTC MpUzE0-199