2015 International Conference on Recent Developments in Control, Automation and Power Engineering (RDCAPE)

Optimization and Scaling of an SOI TFET with Back

Gate Control
S. K. Mitra*, R. Goswami* and B. Bhowmick*
Department of Electronics and Communication Engineering,
National Institute of Technology Silchar,
Silchar-788010, Assam, India

Abstract— A hetero gate dielectric SOI TFET is presented here.

The device performance is observed in TCAD. The effect of
channel doping on the device characteristics is studied.
Moreover, the effect of different gate dielectrics on the ON
current, OFF current, band-to-band generation rate due to
different body layer thickness, and variation of oxide thickness
effect on ON and OFF currents are observed. The variation of
transfer characteristics, band-to-band generation rate for various
back gate voltages are also observed. In comparison with the
conventional TFET, the proposed device provides higher ON
state current and a better ON state to OFF state current ratio
and Subtheshold Swing. Moreover, the Tunnel FET ON state is
independent of back gate voltage, only the subthreshold region is
varying with back gate voltage unlike MOSFET.
Keywords— Band-to-band tunneling; hetero-gate; BTBT
generation rate
II. DEVICE STRUCTURE AND OPERATION
The 2-D structure of the proposed device is shown in Fig. 1.
The basic structure is an SOI (silicon-on-insulator) p-i-n
double gate device operating under reverse biased condition.
This device can operate both in n-mode and p-mode [11]. As
mentioned, we have used SiO2 only dielectric, HfO2 only
dielectric, and hetero-gate dielectric. In hetero-gate structure,
a low-K gate oxide (SiO2 with dielectric constant 3.9) at the
drain side and high-K oxide (HfO2 with dielectric constant 22)
at the tunneling junction are used. To reduce the ambipolar
current at the drain side, low-K gate oxide is used.

I. INTRODUCTION (Heading 1)
MOSFETS are based on drift and diffusion mode of carrier
transport where subthreshold swing depends on thermal
voltage and at the least it can be  60 mV dec [1]. Therefore,
a device can be designed which uses other mode of carrier
transport so that it can provide better switching characteristics
[2]. In our device we have considered band-to-band (BTBT)
tunneling [3]-[4]. However, devices based on this mechanism
fail to meet the ITRS requirements [5].
Tunneling current is a quantum mechanical effect that shows Fig. 1 Device Structure
exponential dependence on tunnel width [6, 7, 8]. The on This device has body layer thickness t s = 30 nm , oxide
current in case of silicon Tunnel FET is lower than that of the thickness 2 nm for SOI TFET. A high doping level, yet still
ITRS requirement [5]. Here SOI based Tunnel FET is realistic in terms of a design to be fabricated is used. In this
investigated with hetero-gate dielectric. This device has paper, the doping concentration of source, drain, and channel
several superior properties compared to conventional TFET. are 1021 , 5 × 1019 , and 1016 cm −3 , respectively. The Si layer
Furthermore, due to the strong back-to-front gate coupling thickness below the BOX is 5nm, and BOX is 15 nm thick.
effect, the threshold voltage can be controlled with back gate The abrupt doping profile is used here. This is a gate-drain
bias without the need of using different channel doping underlap device.
concentrations and, thus, avoiding variability due to random
dopant fluctuations [9]. III. RESULTS AND DISCUSSION
The objective of the paper is to optimize the ON current and
Doping dependent mobility model is used. Device simulation
OFF Current for variation of different gate dielectrics like
has been done in TCAD [12]. In Fig. 2, the
silicon dioxide (SiO2) only gate, Hafnium oxide (HfO2) only
gate, and hetero-gate dielectric (SiO2+HfO2), body layer I D − VG characteristic of the proposed device has been plotted
thickness, oxide layer thickness. The effect of band-to-band for various back gate voltage. It has been observed that the
generation rate on back gate voltage and body layer thickness subthreshold region of drain current is sensitive to the
is also presented. The control of back gate voltage on variation of back gate voltage, while the on state is
MOSFET is already established in literature [10]. independent of the back gate voltage variation. Based on Ion

978-1-4799-7247-0/15/$31.00 ©2015 IEEE 7

 2015 International Conference on Recent Developments in Control, Automation and Power Engineering (RDCAPE)

calculation, it can be shown that drain current is lower due to It has been optimized from Fig. 8 that oxide thickness is
small channel mobility [13]. This has been demonstrated that optimized at 2 nm for various gate dielectrics. In case of
back gate bias would induce high electric field and lead to low optimization of ON current for gate oxide thickness, the best
channel mobility in MOSFET. But in case of proposed ON current is obtained at 1 nm. Considering Fig. 8 and Fig. 9,
structure with the back gate bias the OFF current increases due we can say that the best optimized gate oxide thickness is 1
to increase in ambipolar nature of TFET with increased back −12
gate bias. The ambipolar current is responsible for increase in nm since OFF current is in the range of 10 A/ μ m and ON
the leakage current in TFET [14]-[15]. The proposed device is −4
current in the range of 10 A/ μ m. The OFF state current is
free from channel length modulation effect as the I D − VG reduced because of the presence of a minimum in the surface
characteristics for different channel lengths (gate lengths) are potential and a negative electric field in the channel, as a result
almost same as shown in Fig. 3. The electrical parameters of which we get a better ON/OFF current ratio and a better
have been optimized for various gate dielectrics. A better SS.
value of subthreshold swing, OFF current, ON current can be
obtained in hetero-gate dielectric in Fig. 4. The actual value of
SS in MOSFET is much higher than 60 mV/dec which results
in increased I off and thus become a major concern for low
standby power (LSTP) digital applications [16]-[17]. Our
device is a hetero-gate dielectric to achieve steeper
subthreshold slope. Tunneling takes place from valence band
of the P + source to the intrinsic channel’s conduction band.
Fig. 5 shows that with reduced body layer thickness the ON
current increases. Actually ON current for tunnel FET depends
on the electric field at the tunneling junction. Reduction in
body layer thickness induces high localized field in the tunnel
junction and created abrupt nonlocal current and hence current
Fig. 2 I D − VG characteristics at various back gate voltages. VG 2 is the
increases. The current in case of TFET is given by
back gate voltage.
³
I d = q GB 2 B dV

(1)
where GB 2 B is the band-to-band generation rate given by

E
2 § ·
1. 5
E gi
GB 2 B = A exp ¨ − B ¸ , where E is the electric field,
E gi ¨ E ¸
© ¹
E gi is energy band gap, and A and B are Kane’s parameters
[18].
Due to positive biasing in the back gate voltage OFF state
degrades. But the increase of negative biasing OFF state
degrades at lower doping. But as doping increases, better OFF
state can be achieved as shown in in Fig. 6. In Fig. 7 band-to-
band generation rate is plotted for various body layer Fig.3 I D − VG characteristics at different gate lengths. Lg is the gate length.
thicknesses and for various combinations of gate dielectrics.
The generation rate is found to be more for HfO2 gate
When VD is equal to 0 V, the inversion charge in the channel is
dielectric near the tunneling junction. For -2V back gate
voltage band-to-band generation is observed in the drain controlled by the gate bias as similar in a MOS capacitor
region also. device. Increasing VD bias, the Fermi potential increases, this
The ON current is defined at VG = 1 V , VD = 0.7 V , and OFF effect is similar to increasing VG , thus increasing the
current is defined at VG = 0 V , VD = 0.7 V , where VG , VD are tunnelling current at the P+/channel junction. It results in
the front gate and drain voltages with respect to source. The gradual reduction in inversion charge in the channel and
increase in OFF current is due to increased band to band increase in electric field for BTBT generation. For high
generation rate in drain. Band-to-band generation rate is less enough value of VD, the channel is fully depleted and the
for SiO2 gate dielectric.Due to accumulation of holes, the OFF potential rise leads to enhanced BTBT generation at the
current in drain side is increased i.e., the ambipolarity effect is channel/N+ junction.
increased. The only major difference between fabrication of TFET and
that of MOSFET is that the implants of both N+ and P+ regions
on device are required to create the p---i---n structure.

8
 2015 International Conference on Recent Developments in Control, Automation and Power Engineering (RDCAPE)

IV. CONCLUSION
The proposed SOI structure with back gate control has ON
−4 −12
current 10 A/ μ m and OFF current 10 A/ μ m. With the
change in back gate voltage, OFF current can be better
optimized by controlling the ambipolarity of the device. SS is
found to be 58 mV/dec. The device is free from channel length
modulation and can be used for digital applications.

Fig. 4 Drain current at different gate dielectrics.
Fig.5 Variation of ON current with body layer thickness.
Fig.6 Effect of Back gate bias on different channel doping.
Fig.7 BTBT generation rate with different back gate voltage
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Fig.9 Variation of ON current with oxide thickness.