Designs of 60 GHz Front-Ends in SiGe BiCMOS Technology

Yaoming Sun and Srdjan Glisic

IHP, Frankfurt Oder, Germany
sun@IHP-microelectronics.com

Abstract

This paper reports a newly fabricated 60 GHz front-end (FE) in a 0.25 um SiGe BiCMOS
technology. The TX and RX FE chips have been mounted onto application boards through
wire-bonding. Maximum error-free transmission is 5 meter in a typical indoor environment
with an OFDM modulation. A differential Colpitts VCO has been designed to improve the
phase noise performance. Its tuning range is from 55 to 57.9 GHz. The measured phase noise
is 100.5 dBc/Hz at 1 MHz offset.

I. Introduction

The 60 GHz ISM band provides an enormous frequency resource for high-data-rate
applications. Due to the specific attenuation of oxygen absorption, this band can be dedicated
to short-range communications [1]. Furthermore, channel measurements have shown smaller
RMS delay spreads at 60 GHz than at low frequencies [2], which indicates a wider coherent
bandwidth. Recently, the IEEE 802.15.3c WPAN task group has made a significant progress
with the Wireless HD consortium on some common parameters such as centre frequencies
and channel bandwidth.

With the scaling down of feature size, fast transistors have been developed in silicon-based
technologies. A low-cost receiver working at the 60 GHz band in CMOS technology has been
reported in [3]. SiGe BiCMOS technologies combine both high-speed bipolar transistors with
relatively high breakdown voltages and digital CMOS transistors lending themselves to high
integration levels. By using SiGe technologies, high data-rate communications at 60 GHz
have been successfully demonstrated [4][5].

This paper reports a newly fabricated 60 GHz transceiver FE pair, where differential design
approach is again adopted. The receiver FE is similar to the one reported in [5] with some
building blocks re-optimized. The transmitter FE includes an up-converter, a buffer amplifier,
an on-chip 60 GHz image rejection filter and a PA. The transceiver pair has been assembled
into applications boards by wire boding. These boards are tested in an OFDM transceiver
chain and clear constellations have been measured.

II. Transceiver Front-End and Building Blocks

A. Receiver FE

The transceiver FE features a heterodyne architecture with a 5 GHz fixed IF. There are three
building blocks in the receiver FE, a differential LNA, a Gilbert cell mixer and a 56 GHz
PLL. It has the same building block diagram as in [5]. The 512 divider of the PLL is re-
optimized for a 3 V DC supply. The receiver FE chip photo is shown in figure 1. Notice that
the PLL has been rotated in this chip to achieve a better symmetry between the two
differential paths. Many redundant bond-pads have been added in chip periphery for a low
inductance ground connection, which is of extreme importance in using bond wires. One

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input of the LNA is terminated by an on-chip 50  resistor since the available antenna is
single-ended. This RX FE chip is assembled onto a receiver board designed on a low-cost
Rogers substrate. Figure 2 shows the connection bond-wires and the bond-wire compensation
structure. Even though the on-wafer measurement results are similar to [6], the wireless
measurement shows an improvement in conversion gain of 6 to 10 dB due to the improved
ground connection.

B. Transmitter FE

Figure 3 depicts the building block diagram of a newly designed transmitter FE chip, where
the PLL is identical to the one in RX FE. A Gilbert cell is used as the up-converter core,
which is followed by a buffer amplifier. The buffer amplifier is a three-stage common-emitter
amplifier [7]. A hairpin BPF is inserted before the PA in order to reject the image frequency
at around 51 GHz. The BPF has an insertion loss of 11 dB at 61 GHz, and it provides an
image rejection of 24 dB at 51 GHz. In order to overcome the BPF’s insertion loss, a high
gain PA is required.
The used PA employs a three-stage cascode topology. One stage of the PA is shown in
figure 5. Load inductors are designed symmetrically between the two differential paths. Its
measured small-signal gain and 1-dB compression point are as high as 33 dB and 17.2 dBm,
respectively. The highest power-added-efficiency is measured to be 10.2% at 61.5 GHz.
Figure 4 shows the TX chip photo, where all blocks are marked out [7]. It occupies a chip
area of 1.8 x 1.4 mm2.

C. VCO Design

A new differential Colpitts VCO has been designed to improve the PLL phase noise. A
differential cascode buffer is added after the VCO core to isolate the load. The inductors are
center-taped to allow DC controls at the taps. A resistor is used as the tail current source. The
VCO core is shown in figure 6, and the chip photo is shown in figure 7. It consumes 0.6 x 0.7
mm2 chip area with bond-pads. The VCO core and output buffer draw 24 mA DC current
from a 3.3 V supply. Its tuning range is from 55 GHz to 57.9 GHz. The phase noise at
57 GHz is –100.5 dBc/Hz at 1 MHz offset, as is shown in figure 8.

III. Real Environment Test of the Transceiver FE

The TX FE chip is also assembled onto an application board through wire bonding as
reported in [7]. Vivaldi antennas are integrated onto the transceiver boards. A bond-wire
compensation structure similar to the one in [5] is integrated on-board. A 5 GHz direct QPSK
modulator/demodulator pair is used as IF modem [8]. The OFDM BB signal is generated by
an FPGA board, and it is converted to analogue domain by a high speed DA converter.
Another FPGA board with a high-speed AD converter converts the demodulated BB signal
into digital domain.

In a typical indoor environment, the maximum error-free transmission distance is 5 meter. A

measured constellation diagram at a distance of 5 meter is shown in figure 9, where the signal
is OFDM QPSK with a 3/4 coding rate. The data rate is 360 Mbit/s. In this setup, PA power
is 6 to 10 dB lower than its P1dB since OFDM requires a linear amplification. Since the
Vivaldi antenna is single-ended, both TX FE and RX FE waste 3 dB power dissipated in the
loading resistors. The link budget can be further improved by 3 dB corresponding to two
times transmission distance should a differential antenna is used.
 Conclusion

A pair of newly fabricated transmitter and receiver frond-end for 60 GHz wireless data
transmissions has been reported. The two chips are mounted into cavities and wire bonded to
application boards, where on-board Vivaldi antennas are integrated. In real in-door
environment, error-free transmission has been measured. To improve PLL phase noise, a
56 GHz VCO has been redesigned with a phase noise of -100.5 dBc/Hz at 1 MHz offset.

Acknowledgment
This work was funded by the German Federal Ministry of Education and Research (BMBF)
under grant number 01 BU 371 (WIGWAM).

References

[1] P.F.M Smulders, “60 GHz radio: prospects and future directions’, Proceedings
Symposium IEEE Benelulx Chapter on Communications and Vehicular Technology”,
2003, Eindhoven, pp. 1-8.
[2] Haibing Yang et al., “Indoor Channel Measurements and Analysis in the Frequency
Bands 2 GHz and 60 GHz”, 2005 IEEE 16th International Symposium on Personal,
Indoor and Mobile Radio Communications. pp. 579-583.
[3] B. Razavi, “A 60 GHz Direct-Conversion CMOS Receiver,” ISSCC Dig. Tech. Papers,
Feb. 2005, pp. 400-401.
[4] Scott K. Reynolds et al., “A Silicon 60-GHz Receiver and Transmitter Chipset for
Broadband Communications”, IEEE Journal of Solid-state Circuits, Vol. 41, No, 12,
December 2006, pp. 2820-2830.
[5] Yaoming Sun et al., “An Integrated 60 GHz Transceiver Front-End for OFDM in
SiGe:BiCMOS”, Proc. of 16th Wireless World Research Forum (WWRF16), Shanghai,
China, Apr. 2006.
[6] Yaoming Sun et al., “A Fully Differential 60 GHz receiver Front-End with Integrated
PLL in SiGe:C BiCMOS”, The 1st European Microwave Integrated Circuits conference
(EuMIC), 2006, pp. 198-201.
[7] Srdjan Glisic et al., “A Fully Integrated 60 GHz Transmitter Front-End with a PLL, an
Imange-Rejection Filter and a PA in SiGe”, Accepted by IEEE 34th European Solid
State Circuits Conference (ESSCIRC), 2008.
[8] K. Schmalz et al., “An Integrated 5 GHz Wideband Quadrature Modem in SiGe:C
BiCMOS Technology”, Tech. Digg. of the 36th European Microwave Conference, Sept.
2006, pp. 1656-1659.

Figure 1. Receiver chip photo. Figure 2. RX chip assembly.

Figure 3. Building block diagram of the TX FE. Figure 4. TX FE chip photo.

Figure 5. One cascode stage of the PA. Figure 6. Colpitts VCO core.

Figure 7. Chip photo of the VCO. Figure 8. Phase noise measurement at 57 GHz.

Figure 9. Measured constellation diagram.