IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO.
7, JULY 2012 1161
A Low-Power Low-Cost Design of Primary
Synchronization Signal Detection
Chixiang Ma, Student Member, IEEE, Hao Cao, and Ping Lin, Member, IEEE
Abstract—Synchronization is an important component of a
practical communication system. Furthermore, network entry
including synchronization is important. Since the detection of
primary synchronization signal (PSS) is the first step of network
entry in long term evolution (LTE) systems, thus it may be a
critical path for practical systems. Therefore, tradeoff between
performance and low power consumption and low cost of PSS
detection needs to be made carefully. This paper presents a
new synchronization method for low power and low cost design.
The approach of a 1-bit analog-to-digital converter (ADC) with
down-sampling is compared with that of a 10-bit ADC without
down-sampling under multi-path fading conditions defined in
LTE standard for user equipment (UE) performance test [5]. The
simulation results of PSS are obtained on several kinds of chan-
nels. The simulation results explicitly show that the performance
of the method with down-sampling for 1-bit ADC does not degrade
even if frequency offset exists. Based on the simulation results,
different implementation architectures and their synthesis report
and analysis are present. A low-power low-cost design with high
performance to detect PSS is derived in this paper.
Index Terms—Low cost, low power, matched filter, primary syn-
chronization signal (PSS).
I. INTRODUCTION
T HE explosive growth of cell phone users and the in-
creasing demand for broadband wireless access has led
to the development of long term evolution (LTE) to replace the
wideband code division multiple access (WCDMA)-based air
interface by the 3rd Generation Partnership Project (3GPP).
Several minimum requirements of LTE include packet data
support with peak data rates of 300 Mbps in the downlink and
75 Mbps in the uplink, a low maximum latency of 10 ms MAC
layer round trip delay, and flexible bandwidth scalability. These
requirements result to the adoption of orthogonal frequency
division multiplexing (OFDM)-based modulation and mul-
tiple access, multiple-input-multiple-output (MIMO) antenna
schemes, and adaptive modulation and coding with advanced
channel coding, space time coding and hybrid automatic repeat
request (ARQ) protocols.
Synchronization sequence is more important because its de-
tection affects not only search time but also performance of
demodulation. The 3GPP working group undertakes plenty of
rigorous evaluation of different kinds of sequence to enhance
Manuscript received August 26, 2010; revised January 20, 2011; accepted
April 20, 2011. Date of publication May 31, 2011; date of current version June
01, 2012.
The authors are with Beijing Embedded System Key Lab, Beijing Univer-
sity of Technology, Beijing 100124, China (e-mail: machixiang@emails.bjut.
edu.cn; jackycaohao@emails.bjut.edu.cn; pinglin@bjut.edu.cn).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TVLSI.2011.2152866
1063-8210/$26.00 © 2011 IEEE
the performance of search time. Consequently, it was decided
to adopt Zadoff-Chu (ZC) sequences as the downlink primary
synchronization signal (PSS) and the uplink random access pre-
amble. The ZC sequences are a group of general-chirp-like se-
quences with good correlation properties [1]. To identify the cell
and obtain synchronization, PSS is detected while cell search
takes place. Currently used matched filters [2]–[4] are compu-
tation-intensive since they require a large number of constant
complex multiplications.
The main objective of this paper is to propose an efficient
and accurate PSS detection method with low power and low
cost. The system model, channel model, and PSS definition
are introduced in Section II. A brief review of the matched
filter approach is presented in Section III. Afterwards, both the
method of 1-bit ADC with down-sampling and that of 10-bit
ADC without down-sampling for PSS detection are discussed
in Section IV whereas their simulation results are shown in
Section V. Section VI addresses different implementation
architectures of PSS detection. Finally, conclusion remarks are
given in Section VII.
II. SYSTEM MODEL AND PROBLEM DEFINITION
A. OFDM System Model With Carrier Frequency Offset (CFO)
3GPP adopt OFDM to improve spectrum efficiency. In
OFDM systems, a sequence of complex data symbols is
considered as orthogonal subcarriers during the th OFDM
block, the sequence of data symbols is defined as follows:
(1)
The sequence of data symbols is modulated using an -point
inverse discrete Fourier transform (IDFT) process that produces
the sequence
(2)
where is the normalized -by- IDFT matrix and is
(3)
Consequently, the th sample in the sequence can be ex-
pressed as
(4)
In fading channels, a time-domain guard interval, which is
named as cyclic prefix (CP), is created by copying the last
samples of the IDFT output and appending them at the begin-
ning of the OFDM symbol to be transmitted. So the transmitted
OFDM block consists of samples.
1162 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 7, JULY 2012

TABLE I TABLE II
DELAY PROFILES FOR E-UTRA CHANNEL MODELS EXTENDED PEDESTRIAN MODEL

TABLE III
EXTENDED VEHICULAR MODEL

At the receiver side, after removing the first CP samples,

the received sequence

(5)

is obtained [9]

(6)

where represents the normalized CFO, and represents

the effect of the accumulated phase rotation caused by the CFO
TABLE IV
on the time domain samples EXTENDED TYPICAL URBAN MODEL

(7)
(8)

denotes the channel frequency response during the th

OFDM block

(9)

represents a zero-mean complex white Gaussian noise

sample with variance .
Assuming that the receiver sampling clock is aligned to that TABLE V
of the transmitter, then the th element of can be expressed CHANNEL MODEL PARAMETERS
as

(10)

B. Channel Propagation Model

The evolved universal terrestrial radio access (E-UTRA)
channel model is recommended, since PSS is a component of
LTE. It can evaluate the proposed method more reasonable and
practical to use of E-UTRA channel model.
There are delay profiles, Doppler spectra and channel corre-
lation matrices in E-UTRA channel model. Then there are too
many combinations of these components. First of all, delay pro-
files are introduced.
The delay profiles are selected to be representative of low,
medium and high delay spread environments. The resulting
model parameters are defined in Table I and the tapped delay
line models are defined in Tables II–IV [5].
The Doppler spectra are selected to be representative of low,
medium and high Doppler spread environments. Then, the max
Doppler frequency is 5, 70, and 300 Hz, respectively.
The combinations of delay profiles and Doppler spectra are
also defined in [5]. Only five combinations can be used to eval-
uate the performance measurements of receiver in multi-path
fading environment. Table V shows all the combinations.
Finally, the channel correlation matrices are also selected
to be representative of low, medium and high channel correla-
tion environments. Since 4-by-4 simulations will be given in
MA et al.: A LOW-POWER LOW-COST DESIGN OF PRIMARY SYNCHRONIZATION SIGNAL DETECTION
TABLE VI
DIFFERENT CORRELATION CONSTANT
TABLE VII
ROOT INDICES FOR THE PSS
next section, thus 4-by-4 correlation matrices is provided as
follows [5]:
(11)
where and is define in Table VI [5], and denotes Kro-
necker product.
C. PSS
A synchronization channel (SCH) is specified in LTE system
to transmit PSS and secondary synchronization signal (SSS) [1].
The sequence used for the PSS is generated from a
frequency-domain ZC sequence [1] according to
(12)
where the ZC root sequence index is given by Table VII [1].
The three different ZC sequences are orthogonal to each
other, and each sequence corresponds to a sector identity which
is in the range of 0 to 2. The ZC sequence is chosen for its
good periodic autocorrelation and cross-correlation properties.
In particular, these sequences have a low frequency offset
sensitivity, which is described in [8]. Thus, it is easy to detect
PSS during the initial synchronization because the ZC sequence
has the flat frequency domain autocorrelation property and the
low frequency offset sensitivity.
III. FUNDAMENTAL DETECTION METHOD
The main function of PSS is to detect the boundary of a frame
where non-coherent detection method has to be used at the re-
ceiver since there is no known reference information initially.
Matched filter is a basic non-coherent detection method that
can be used to detect PSS efficiently.
1163
The sequence in (12) is mapped to the subcarriers around DC
and transformed to time domain by 64-point IDFT. To detect
this signal at the receiver, the correlation with the time-
domain signal of the ZC sequence is calculated [2]–[4]
(13)
where is the successive 64-by-1 received signal vector, is
the DFT matrix, and is 64-by-1 vector composed of
punctured at DC.
Then, from (13), the coefficients of the matched filter can be
obtained
(14)
where
(15)
and the matched filter can be expressed
(16)
where is the received signal.
IV. PRACTICAL DETECTION METHOD
From the power consumption perspective, a 10-bit analog-to-
digital converter (ADC) uses more power than a 1-bit ADC since
the 10-bit pipelined ADC has several power amplifiers in it.
Typically, the power consumption of a 1-bit 122.88 MHz ADC
composed of one comparator is about 200 W, while the power
consumption of a 10-bit 122.88 MHz pipelined ADC is about
50 mW. To come up with a low-power solution, a method of
PSS detection using 1-bit ADC is proposed.
PSS is transmitted periodically, twice per frame which lasts
10 ms. The sampling rate of the receiver is 122.88 MHz; how-
ever, the date rate of input data to the matched filter is 1.92 MHz.
Thus, 9600 samples at the output of the matched filter need
to be buffered during the 5 ms period, which is not area and
cost efficient. To come up with a low cost solution, a method of
down-sampling by 8 is used at the output of matched filter.
A. Method Without Down-Sampling by 8 for 10-Bit ADC
From the last section, the matched filter as expressed in (16)
can be reformulated when using a 10-bit, 122.88 MHz pipelined
ADC
(17)
where is the received signal sampled by a 10-bit, 122.88
MHz pipelined ADC, and is obtained in (14) and (15).
Every output of the matched filter is buffered since
there is no down-sampling module, and it needs a large area
buffer which is very costly.
1164 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 7, JULY 2012
TABLE VIII
SIMULATION ASSUMPTIONS
B. Method With Down-Sampling by 8 for 1-Bit ADC
Equation (16) can be reformulated when using a 1-bit, 122.88
MHz ADC
(18)
where is the received signal sampled by a 1-bit, 122.88
MHz ADC, and is obtained in (14) and (15).
Every output of the matched filter is down-sampled by
8
(19)
where is the output of the down-sampling module.
Now, only 1200 outputs need to be buffered during 5 ms with
an additional comparator of 1 out of 8 implementing the down-
sampling module. This results in less area which translates to
lower cost in a practical system.
With the practical method introduced above, its implementa-
tion architecture is discussed in Section VI after the simulation
performance is discussed in Section V.
V. SIMULATION RESULTS
Primary synchronous signal is designed for cell search and
handover in 3GPP LTE systems, which is transmitted every 5
ms. Search time of PSS detection is an important criterion when
measuring its performance.
To compare the performance using a 10-bit 122.88 MHz ADC
without down-sampling and that using a 1-bit 122.88 MHz ADC
with down-sampling by 8, the parameters listed in Table VIII are
used in the simulation.
We assume that there are four receive antennas and four
transmit antennas in the simulated LTE MIMO system.
Replica-based method is very useful for symbol timing de-
tection since a diversity gain of 3 dB can be obtained when
two PSSs are received in different time slot. Higher diversity
gain can be achieved when more than two PSSs are used in the
detection. At most 16 PSSs are transmitted in the simulation,
that is, the detection gives up after 16 PSS correlations are
calculated at the receiver. From Section II, we know that there
are different combinations of delay profiles, Doppler spectra
and channel correlation matrices defined in E-UTRA channel
model. To demonstrate different simulation assumptions in the
channel model, we simulate both the original method and the
Fig. 1. Performance of both methods using low correlation channel matrix and
EPA 5 Hz channel model.
proposed method under three typical channel combinations,
which is EPA 5 Hz model with low correlation channel matrix,
EVA 70 Hz model with medium correlation channel matrix and
ETU 300 Hz model with high correlation channel matrix.
Fig. 1 shows the search time of both methods under EPA 5
Hz model with low correlation channel matrix, which indicates
that their performance is very close to each other. The results
for EVA 70 Hz and ETU 300 Hz are shown in Figs. 2 and 3,
respectively. From Figs. 2 and 3, we can see that the method
using a 1-bit 122.88 MHz ADC with down-sampling by 8 does
not degrade the performance much even if the signal-to-noise
ratio (SNR) is very low. When SNR is larger than 10 dB, their
performance are almost identical. As a result, the method of
1-bit 122.88 MHz ADC with down-sampling by 8 is proposed
as the low power and low cost design for PSS detection with
good search performance.
VI. HARDWARE IMPLEMENTATION
As discussed in the previous section, the performance of the
proposed method for PSS detection is acceptable in a practical
LTE system; thus, its implementation detail is described in this
section where the matched filter is considered first followed by
the architecture of our proposed PSS detector.
A. Architecture of Matched Filter
The matched filter is an important component in the PSS
detection, as denoted in Section III. We use 64-tap time do-
main matched filter; hence 64 complex multiplication units per
matched filter are used in the calculation in (16).
Since 84 matched filters are required in the system, a total
of 5376 units of complex multiplication is needed, which is not
reasonable for a practical implementation due to the high cost
of multiplication unit in the receiver. In practice, the sampling
rate of input data to the matched filter is 1.92 MHz while the
system clock is 122.88 MHz, which implies that we can use
MA et al.: A LOW-POWER LOW-COST DESIGN OF PRIMARY SYNCHRONIZATION SIGNAL DETECTION
Fig. 2. Performance of both methods using medium correlation channel matrix
and EVA 70 Hz channel model.
Fig. 3. Performance of both methods using high correlation channel matrix and
ETU 300 Hz channel model.
only one complex multiplication unit during 64 cycles instead of
using 64 units of complex multiplication. Thus we propose the
structure of matched filter shown in Fig. 4. As a result, 84 units
of complex multiplication are enough for the whole system.
B. Architecture of PSS Detection
A mismatch of up to 14 part per million (ppm) can exist be-
tween the oscillators at the base station (eNodeB) and at the UE,
so seven groups of matched filters are used to cover the range
of [ 14 ppm, 14 ppm] with each group responsible for 4 ppm
corresponding to 2/3 subcarrier spacing. Each group contains
three matched filters to detect three different physical-layer IDs
of value 0, 1, or 2. Therefore, there are 21 hardware units as
shown in Fig. 6 for each receiver antenna. Since the system is
MIMO 4-by-4 and there are 4 receiver antennas at the UE end,
1165
Fig. 4. Matched filter architecture with one complex multiply unit.
Fig. 5. Original architecture of the whole PSS detection.
Fig. 6. Area-efficient architecture of the whole PSS detection.
84 such hardware units are involved in the architecture of the
PSS detection.
As the sampling rate of the input data to PSS detection is 1.92
MHz and the PSS signal is repetitively transmitted every 5 ms,
there are 9600 samples during 5 ms and thus a single port RAM
with 9600 addresses is needed.
As described above, there are 84 such RAMs in the system,
and the area is too large for the UE chip; therefore an area-
efficient architecture is proposed as shown in Fig. 6. Compared
to the architecture in Fig. 5, a small RAM with 8 addresses is
added whose function is to find the maximum value of every
eight correlations. As a result, only 1200 correlation values need
to be stored in RAM with 1200 addresses, which reduce the
RAM size of the whole system by a factor of almost 8.
As the implementation is targeted for application-specific in-
tegrated circuit (ASIC) chip, the two different architectures are
synthesized using SMIC 65-nm technology at 1.2 V voltage.
The area and power reports are listed in Table IX. We can ob-
serve that the area of the area-efficient architecture is much
smaller than that of the original architecture, which reduces the
1166 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 20, NO. 7, JULY 2012
TABLE IX
COMPARISONS OF TWO ARCHITECTURES
cost of the chip significantly. From the power perspective, not
only the 1-bit ADC reduces the power consumption, but the
hardware of digital logic also does.
VII. CONCLUSION
In this paper, we address the problem of detecting primary
synchronization signal in 3GPP LTE system. Down-sampling
block, 10-bit 122.88 MHz ADC and 1-bit 122.88 MHz ADC are
basic components of PSS detection methods. Theoretically, de-
tection with 1-bit ADC and with down-sampling would degrade
the performance and prolong the detection time. However, due
to the inherent advantage of the ZC sequence, our simulation re-
sults show that the performance of the proposed method using
a 1-bit ADC with down-sampling by 8 does not degrade much
compared with that using a 10-bit ADC without down-sampling
in the presence of frequency offset under several typical LTE
propagation channels. Subsequently, two different implementa-
tion architectures of the PSS detection are presented. As the area
and the power consumption of the original implementation ar-
chitecture are too large to be acceptable, based on simulation
results and ASIC synthesis results, a more practical implemen-
tation architecture is proposed where the PSS can be detected
efficiently and accurately at a much lower power and lower cost
which renders it feasible in the implementation of a UE chip.
REFERENCES
[1] 3rd Generation Partnership Project (3GPP), Sophia-Antipolis Cedex,
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and Modulation (Release 8), 3rd Generation Partnership Project, Dec.
2009, 3GPP.
[2] K. Manolakis, D. M. Gutierrez Estevez, V. Jungnickel, X. Wen, and
C. Drewes, “A closed concept for synchronization and cell search in
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[3] B. M. Popovic and F. Berggren, “Primary synchronization signal in
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mission and Reception (Release 8), 3rd Generation Partnership Project,
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MA: Kluwer, 2001.
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Chixiang Ma (S’10) received the B.S. degree in
electrical engineering from Zhejiang University,
Hangzhou, China, in 2005. He is currently pursuing
the Ph.D. degree from Beijing Embedded System
Key Lab of Beijing University of Technology,
Beijing, China.
His research interests include MIMO and OFDM
of wireless communication systems and VLSI
design.
Hao Cao received the B.S. degree in electrical and
information from Huazhong University of Science
and Technology, Wuhan, China, in 2008. He is
currently pursuing the M.S. degree from Beijing
Embedded System Key Lab, Beijing University of
Technology, Beijing, China.
His research interests include synchronization and
VLSI design.
Ping Lin (M’10) received the M.S. degree in elec-
trical engineering from University of Rhode Island,
Kingston.
She is the Director of Beijing Embedded System
Key Lab, Beijing University of Technology, Beijing,
China. Her research interests include DSP algo-
rithms, VLSI design, wireless communications, and
embedded SOC.