IEIE Transactions on Smart Processing and Computing, vol. 8, no.

6, December 2019
https://doi.org/10.5573/IEIESPC.2019.8.6.506 506

IEIE Transactions on Smart Processing and Computing

A Novel Approximate Adder with Enhanced Low-cost

Carry Prediction for Error Tolerant Computing
Yongtae Kim

School of Computer Science and Engineering, Kyungpook National University, Daegu, Korea yongtae@knu.ac.kr

Received August 26, 2019; Accepted September 16, 2019; Published December 30, 2019

* Short Paper

Abstract: This paper proposes an approximate adder that employs a novel carry speculation scheme
to enhance the computation precision of the existing error tolerant adder (ETA) designs with
extremely little hardware overhead. The proposed carry prediction technique leverages two input
bits to increase the prediction accuracy while the conventional ones do only one bit. This leads to a
reduction of the carry prediction error rate from 25% to 18.75%. Compared to the existing ETA
design, the proposed adder reduces normalized mean error distance (NMED) and mean relative
error distance (MRED) by up to 10% and 28%, respectively, at the cost of only a two-input OR
gate. Moreover, the proposed design outperforms the conventional ETAs when jointly evaluating
hardware cost and computation accuracy. Specifically, the new design allows 11% and 17%
reductions of area-power-NMED and power-NMED products, respectively, compared to the
traditional ETA.

Keywords: Approximate adder, Error tolerant computing, Error tolerant adder (ETA), Carry predicting error
tolerant adder (CPETA)

1. Introduction approximate addition for lower order bits. Dalloo et al.

Power consumption has become a key design
constraint in modern digital systems, and researchers have
made aggressive efforts to reduce power dissipation in
designing the systems, especially mobile and portable
devices. Approximate computing has emerged in response
to increasing power demand. This new computing
technique exploits the inherent error tolerance in many
applications, such as image and video processing, and
neuromorphic computing, to reduce hardware cost (e.g.,
power and area) while sacrificing computation precision
with acceptable processing quality [1-4]. It becomes
possible in that they do not require 100% full precision in
computations and humans can still recognize and interpret
the outcomes even with intermittent errors in these
applications. Since they excessively use the addition
operation, designing power-efficient approximate adders is
one of the critical success factors for taking advantage of
approximate computing, and a lot of adder designs have
been presented [4-10]. For example, Mahdiani et al.
proposed the lower-part OR adder (LOA) that utilizes a
smaller sub-adder and a few standard digital logic gates
(e.g., the OR gate) [5]. The sub-adder performs precise
addition for higher order input bits while the OR gates do
analyzed and optimized the LOA architecture and
introduced a systematic design approach called the
optimized lower-part OR constant adder (OLOCA) [6].
The error tolerant adder I (ETAI) presented in [7] has a
similar adder architecture to the LOA in that it also uses a
sub-adder together with modified XOR gates to achieve
overall approximate addition. Kim proposed the carry
predicting error tolerant adder (CPETA) to improve the
computation accuracy of the ETAI and LOA by exploiting
a new carry prediction method with a sum generator [8].
This article focuses on a new approximate adder design
based on the existing ETAs [7, 8], and enhances accuracy
by proposing a novel carry prediction method. The carry
speculation utilizes two input bits and offers an 18.75%
carry prediction error rate, whereas the conventional one
reaches 25% using only one input bit. When implemented
in a 65-nm CMOS technology, the proposed adder
improves computation precision notably. Specifically, the
proposed design reduces mean relative error distance
(MRED) by up to 28% and 43%, compared to the CPETA
and ETAI, respectively.
IEIE Transactions on Smart Processing and Computing, vol. 8, no. 6, December 2019
An-1:n-k Bn-1:n-k An-k-1 Bn-k-1 An-k-2 Bn-k-2 An-k-3 Bn-k-3
k-bit
Precise Cin
Adder
Sn-1:n-k
Fig. 1. Block diagram of the proposed enhanced carry predicting error tolerant adder (ECPETA).
2. Proposed Approximate Adder
This section describes the proposed approximate adder,
which is called the enhanced carry predicting error tolerant
adder (ECPETA). Let n and k denote the length of the
entire adder and the size of the precise adder, respectively.
Fig. 1 exhibits a block diagram of the proposed adder
architecture, which consists of a k-bit precise adder for k
most significant bit (MSB) inputs and a digital logic circuit
to approximately add the remaining n-k least significant bit
(LSB) inputs. It is worth noting that any traditional
accurate adder, such as the ripple carry adder (RCA), can
be adopted to implement this precise adder. A carry-in
signal (Cin) is speculated from n-k-1 and n-k-2 LSB input
bits and is fed into the precise adder. The carry is predicted
by OR’ing the two intermediate outputs of the AND gates
for the adder inputs (see the gray logic gates in Fig. 1). In
fact, in terms of circuit implementation, the difference
between the proposed adder and the existing CPETA is the
OR gate. In other words, the two AND gates are necessary
to design the CPETA, and the proposed adder requires the
cost of merely one OR gate. This may cause a longer delay
than the CPETA, and the critical path delay tECPETA is given
by
tECPETA = max(t pa + tOR + t AND ,
t AND + (n − k − 3) ⋅ tOR )
where tpa, tOR, and tAND are the delays of the precise adder,
the two-input OR gate, and the AND gate, respectively.
Fig. 2 illustrates the operation of the proposed
ECPETA. Basically, the overall approximate addition
requires two different steps that are performed
concurrently. The precise adder is used to correctly
compute the higher order k input bits. The carry-in (Cin) is
predicted through the OR operation of the two AND
outputs from n-k-1 and n-k-2 LSB input bits to enhance the
carry speculation accuracy while the CPETA leverages n-
k-1 LSB input bits only. Simultaneously, the approximate
addition for the remaining lower order input bits is
conducted according to the conventional ETA algorithm.
In brief, if both input bits are 1 when checking from the n-
k-2 input position to the LSB, all the remaining LSB
507
A0 B0
Sn-k-1 Sn-k-2 Sn-k-3 S0
MSB LSB
10110111 10000110
+ 00101001 10010100
AND AND
k-bit Precise Adder Approximation
Cin
11100001 00010111
All bits set to "1"
Fig. 2. Operation of the proposed adder.
outputs are set to 1. Otherwise, it performs the regular bit-
wise OR operation between the inputs.
The proposed ECPETA utilizes one more input bit to
generate the carry, compared to the CPETA and LOA, and
its carry prediction error rate (CPER) is better than theirs,
in which speculation is achieved by AND’ing the n-k-1
LSB input. For these adders, the carry prediction is always
correct when the two inputs of the n-k-1 bit position are
identical (i.e., An-k-1 = Bn-k-1). If they are exclusive of each
other, however, then more preceding inputs beyond the n-
(1) k-1 LSB position (i.e., the n-k-2 bit position to the LSB)
are needed to correctly determine the carry. Therefore, the
probability of the carry prediction error of the LOA and
CPETA is 1/4 = 0.25, and their CPER would be 25% under
random input patterns. On the other hand, the proposed
carry speculation is always precise, except in the following
two cases:
1) An-k-1 = Bn-k-1 = 0 and An-k-2 = Bn-k-2 = 1
2) An-k-1 ≠ Bn-k-1 and An-k-2 ≠ Bn-k-2
In 1), the correct carry would be 0, but our scheme
produces 1 as a carry, since both inputs of the n-k-2 LSB
position are 1. Case 2) requires lower LSB inputs (i.e., the
n-k-3 bit position to the LSB) to correctly calculate the
carry. Therefore, considering these two cases, the CPER of
the proposed adder is 3/16×100 = 18.75% under random
input.
In addition to the CPER, the overall error rate (ER) of
the proposed adder is identical to the CPETA, since an
508 Kim: A Novel Approximate Adder with Enhanced Low-cost Carry Prediction for Error Tolerant Computing

error occurs when both input bits of the n-k-2 LSB position Table 1. Comparison of the proposed adder with two
are 1. It is written as other approximate adders when n=16 and k=8.

n − k −1
⎛3⎞
ERECPETA (n, k ) = 1 − ⎜ ⎟
⎝4⎠
3. Experimental Results
The proposed approximate adder, together with the
ETAI and CPETA, were designed in the Verilog HDL and
synthesized with a 65-nm CMOS standard cell library in
order to evaluate and compare circuit performance. The
parameters of n=16 and k=8 were considered and the
precise adder was implemented with an RCA for all these
approximate adders. Also, software simulations were
conducted to analyze the computation accuracy of the
adders, and ER, CPER, MRED, mean error distance
(MED), and normalized MED (NMED) were extracted
under 10 million (i.e., 107) uniformly generated random
input patterns.
Table 1 summarizes the circuit performance of the
proposed adder and the other two approximate adders. The
lack of a carry prediction method makes the ETAI the
fastest adder among them. Also, it is the most efficient
design with respect to area, power, and power delay
product (PDP), although it exhibits the worst accuracy,
which will be investigated later in this section. Since the
proposed ECPETA necessitates an OR gate to more
accurately speculate the carry, it causes a longer critical
path delay than the others. Unfortunately, this also makes
the proposed design the most energy-consuming (i.e. PDP)
adder. It is very important to note that the critical path
delay of these adders depends on either parameter k or the
delay of the precise adder (i.e., tpa), as seen in (1). It means
that the overall critical path delay could be the same for all
three adders when k is small enough. From the area and
power perspectives, the proposed design is comparable to
the CPETA.
Table 2 provides a computation accuracy comparison
of the 16-bit approximate adders for different sizes of k. It
shows that the accuracy of the approximate adders clearly
improves as the size of the precise adder k increases. The
ER of the CPETA and ECPETA is identical, as explained
in Section 2, and is slightly lower than the ETAI. The
MED and NMED decrease by nearly half as k increases by
Area Power PDP
Adder Delay (ns)
(µm2) (µW) (fJ)
(2)
ETAI 108 1.09 26.3 28.7
CPETA 114 1.14 28.0 31.9
ECPETA 116 1.26 29.7 37.4
1 for all the adders. Those of the proposed adder are
enhanced by up to 8% to 10% and 54% to 56%,
respectively, compared to the CPETA and ETAI. In
addition, the MRED of all adders is reduced by between
0.5 and 1 when k increases by 1. The proposed design
allows the MRED to decrease by 9% to 28% and 17% to
43% compared to the CPETA and ETAI, respectively.
Thanks to the proposed carry speculation method, in short,
this design outperforms the other two ETA designs from
all computation accuracy perspectives.
To validate the CPER calculated in Section 2, the
CPER of the proposed design and the CPETA at the
different sizes of k were also simulated. Fig. 3 shows the
CPER of the two 16-bit adders under different sizes of k.
Please note that the ETAI has no carry prediction scheme,
and hence, it was not included in this simulation. As
discussed in Section 2, the CPER of the CPETA reaches
around 25% (24.97% to 24.22%), whereas the proposed
design maintains a CPER of about 18.75% (18.75% to
17.99%), regardless of k. As an example, the CPER of the
CPETA and the ECPETA are 24.81% and 18.56%,
respectively, for k=8, resulting in a CPER reduction of
25.19%. In fact, this improvement in the carry prediction
accuracy enables the existing ETA designs to enhance
their overall computation accuracy.
To jointly evaluate the power and accuracy of the
approximate adders, the power-NMED product was
presented in [11]. This represents the overall efficiency of
approximate adders, considering both hardware cost and
precision. Furthermore, the area-power-NMED product
can be defined to take are into account, as well. Fig. 4
exhibits the products for the three approximate adders with
n=16 and k=8. To effectively compare these metrics
among the adders, they were normalized by the ETAI, and
the values outside of the bars were inserted. The results
clearly show that the proposed design is superior to the
ETAI and CPETA in terms of both the power-NMED

Table 2. Accuracy comparison of the 16-bit approximate adders for different sizes of k.

ETAI CPETA ECPETA

k ER (%) MED MRED NMED ER (%) MED MRED NMED ER (%) MED MRED NMED
4 96.83 2780.82 7.83 4.24e-02 95.78 1409.72 7.14 2.15e-02 95.78 1275.61 6.47 1.95e-02
5 95.77 1413.20 7.32 2.16e-02 94.36 711.90 6.62 1.09e-02 94.36 646.52 5.93 9.87e-03
6 94.37 709.72 6.47 1.08e-02 92.48 355.13 5.76 5.42e-03 92.48 322.79 5.06 4.93e-03
7 92.50 357.80 5.81 5.46e-03 90.01 179.06 5.12 2.73e-03 90.01 163.03 4.42 2.49e-03
8 89.98 177.14 5.08 2.70e-03 86.65 88.58 4.38 1.35e-03 86.65 81.46 3.70 1.24e-03
9 86.65 89.77 4.53 1.37e-03 82.20 44.99 3.81 6.86e-04 82.20 40.68 3.05 6.21e-04
10 82.21 43.97 3.62 6.71e-04 76.26 21.73 2.89 3.32e-04 76.26 19.68 2.06 3.00e-04
IEIE Transactions on Smart Processing and Computing, vol. 8, no. 6, December 2019
Fig. 3. CPER of the 16-bit approximate adders for
different sizes of k.
Fig. 4. Normalized Power- and Area-Power-NMED
products for the 16-bit approximate adders with k = 8.
product and area-power-NMED product. While the
ECPETA shows slightly better performance than the
CPETA, it reduces the area-power-NMED product and
power-NMED product by 11% and 17%, respectively,
compared to the ETAI. The proposed carry prediction
approach certainly makes the proposed design the most
efficient adder, and it also offers a good design tradeoff
among area, power, and precision.
4. Conclusion
This paper presented a new approximate adder design
that leverages a novel carry speculation technique to
reduce approximation errors. The proposed carry
prediction requires only a few digital logic gates and
improves precision significantly. When implemented in a
65-nm CMOS technology, the proposed approximate adder
allows reductions in MED and MRED of 17% to 43% and
54% to 57%, respectively, of the ETAI and the proposed
carry prediction method reduces the CPER by 25.19%,
compared to the CPETA. Furthermore, this design offers a
good tradeoff among area, power and computation
509
accuracy, and demonstrated up to an 11% reduction in the
area-power-NMED product when compared to the other
approximate adders. While the proposed carry prediction
method was applied to only ETA designs in this work,
importantly, it can be appropriately employed in the design
of similar adder architectures, such as the LOA, to enhance
accuracy at an extremely low cost. Therefore, the proposed
design approach is applicable quite well to designing error
tolerant computing systems, such as neuromorphic
computing [12], to achieve overall power efficiency with
reasonable computation precision.
Acknowledgement
This research was supported by Kyungpook National
University Research Fund, 2018.
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Yongtae Kim received the B.S. and

M.S. degrees in electrical engineering
from the Korea University, Seoul,
Republic of Korea, in 2007 and 2009,
respectively and the Ph.D. degree from
the Department of Electrical and
Computer Engineering from the Texas
A&M University, College Station, TX,
in 2013. From 2013 to 2018, he was a software engineer
with Intel Corporation, Santa Clara, CA. Since 2018, he
has been with the School of Computer Science and
Engineering at Kyungpook National University, Daegu,
Republic of Korea, where he is currently an assistant
professor. His research interests are in energy-efficient
integrated circuits and systems, particularly, neuromorphic
computing and approximate computing, and new memory
devices and architectures.

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