MICROPROCESSORTECHNOLOGY

BENC2423
ADDRESSING MODES

Syafeeza Ahmad Radzi1, Wong YanChiew2

1syafeeza@utem.edu.my, 2ycwong@utem.edu.my,
 Learning Outcomes

At the end of this lecture, you should be able to:

• Differentiate between the three categories of base
displacement addressing mode.
• Relate LDRand STRinstructions with the three
categories of base displacement addressing mode.
 Table of Contents

Operand addressing (Base

displacement addressing mode)
• Offset
• Pre-indexed
• Post-indexed

Comparison of addressing modes

Exercises
 Operand addressing
• There are many ways in ARM to specify the address; these are called addressing
modes.
• Two basic classification
1. Base register Addressing (1 type)
– Known as register indirect addressing mode
– Register holds the 32 bit memoryaddress
– Also called the baseaddress
– E.g: LDRr0, [r1]

2. Base Displacement Addressing mode (9 types)

– Offset (i) immediate, (ii) register, (iii)scaled register
– Pre-indexed (i) immediate, (ii) register, (iii) scaledregister
– Post-indexed (i) immediate, (ii) register, (iii)scaled register
– E.g: LDRr0, [r1, #12], LDRr0, [r1, r2]
– An effective address is calculated:
Effective address = < Base address + base displacement>

In total, there are 10 different addressingmodes

 Offset: Immediate

i. Immediate offset
Syntax (32 bit): op{type}{cond} Rt, [Rn {, #offset}] ; immediate offset (value range: -255 to +4095)
Syntax (64 bit): opD{type}{cond} Rt, [Rn {, #offset}] ; immediate offset, two words (value range: -1020 to +1020)

[Rn, #±imm]
• Address accessed is imm more/less than the address found in Rn.
• Rn does not change.
• Example:
LDR r2, [r1, #12] ; r2:= mem32[r1+12]

1210 =C16

Before load
Address Memory
r1 0×00006000
Base address 0×00006000 0×000000BE
r2 0×12345678 0×00006004 0×000000BA
0×00006008 0×000000ED
After load
Effective address 0×0000600C 0×000000FE
r1 0×00006000

r2 0×000000FE r1 value will not be changed by immediate offset

 Offset: Immediate (cont.)

• Example: Immediate offset for STR

STRr0, [r1, #-8] ; Store word from r0 to location pointed to by contents of [r1, #-8]

Before store Before store After store

r1 0×00006000
Address Memory Address Memory
r0 0×12345678 0×00005FF8 0×000000BE Effective address 0×00005FF8 0×12345678
0×00005FFC 0×000000BA -8 0×00005FFC 0×000000BA
After store
0×00006000 0×000000ED Base address 0×00006000 0×000000ED
r1 0×00006000
0×00006004 0×000000FE 0×00006004 0×000000FE
r0 0×12345678

r1 value will not be changed by

immediate offset
 Offset: Register
ii. Register offset
Syntax: op{type}{cond} Rt, [Rn, ± Rm}]
[Rn, ±Rm]
• Address accessed is the value in Rn ± the value in Rm. Rn and Rm do not change
values.
• This is just shorthand for [Rn, ±Rm, LSL#0].

Before load
Address Memory
r0 0×00006000
Base address 0×00006000 0×000000BE
r1 0×0000000C 0×00006004 0×000000BA
0×00006008 0×000000ED
r2 0×12345678
Effective address 0×0000600C 0×000000FE
After load
r0 0×00006000
r0 and r1 do not change
r1 0×0000000C values

r2 0×000000FE r2 is updated with the value

contained in the effective address
 Offset: Register (cont.)

• Example
STRr2, [r0, r1] ; Store word from r2 to location pointed to by contents of [r0, r1]

Before store Before store After store

r0 0×00006000 Address Memory Address Memory

0×00006000 0×000000BE Base address 0×00006000 0×000000BE
r1 0×0000000C
0×00006004 0×000000BA 0×00006004 0×000000BA
r2 0×12345678 0×00006008 0×000000ED 0×00006008 0×000000ED
0×0000600C 0×000000FE Effective address 0×0000600C 0×12345678
After store
r0 0×00006000

r1 0×0000000C r0, r1 and r2 do not

change values
r2 0×12345678
 Offset: Scaled-register

iii. Scaled registeroffset

Syntax: op{type}{cond} Rt, [Rn, ± Rm, shift]

[Rn, ±Rm, shift]

• Address accessed is the value in Rn ± the value in Rm shifted asspecified.
• Rn and Rm do not change values.
• Example: LDR r0, [r1, r2, LSL #5] ; r0  *(r1 + r2 * 32)
• LSL: Logical Shift Left
– Shifts left by the specified amount (multiplies by powers of two) e.g.
– r2, LSL#5 = r2 multiply by32

r2 0×0000000C C16 = 11002

1 After LSL #5, 11002 becomes 2 C16×2016 (Remember, 25 = 3210 = 2016)

1100000002 that is equivalent to 18016

• LSR: Logical Shift Right

– Shifts right by the specified amount (divides by powers of two) e.g.
– r2, LSR#5 = R2 divide by32
 Offset: Scaled-Register (cont.)

Shifted/rotated secondoperand
• LSL #n Logical shift left n (0  n  31)
• LSR #n Logical shift right n (1  n  32)
• ASR #n Arithmetic shift right n (1  n  32)
• ROR #n Rotate right n (1  n  31)
• RRX Rotate right one bit, with extend
• Bit [0] is written toshifter_carry_out,
• Bits [31:1] shifted right onebit
• Carry flag is shifted into bit [31]
 Offset: Scaled-Register (cont.)

• Example:
LDRr0, [r1, r2, LSL#2]
Before load
r0 0×12345678 Address Memory
Base address 0×00006000 0×000000BE r2×22 = C16×4 = 3016
r1 0×00006000 .
.
. r1 + 3016 = 0×00006030
r2 0×0000000C
Effective address 0×00006030 0×000000FE
After load
r0 0×000000FE Copy the value hold by effective
adress
r1 0×00006000
The value of r1 does not change

r2 0×0000000C
 Offset: Scaled-Register (cont.)

• Example:
STRr0, [r1, r2, LSL#2] ; Store word from r0 to location pointed to by contents of [r1, r2, LSL#2]

Before store Before store After store

r0 0×12345678 Address Memory Address Memory

0×00006000 0×000000BE Base address 0×00006000 0×000000BE

r1 0×00006000 . .
. .
. .
r2 0×0000000C
0×00006030 0×000000FE Effective address0×00006030 0×12345678
After store
r0 0×12345678 r0 remain the same r2×22 = C16×4 = 3016

r1 0×00006000 The value of r1 does not change r1 + 3016 = 0×00006030

r2 0×0000000C
 Pre-indexed: Immediate

i. Immediate pre-indexed
Syntax (32 bit): op{type}{cond} Rt, [Rn , #offset]! ; pre-indexed (value range: -255 to
+255)
Syntax (64 bit): opD{type}{cond} Rt, [Rn , #offset]! ; pre-indexed, two words (value range:
-1020 to +1020)

[Rn, #±imm]!
• Address accessed is as with immediate offset mode, but Rn's value updates to become
the address accessed.

LDRr0, [r1,#6]! ; r0 : = mem32 [r1 +6]

; r1 : = r1 +6

The exclamation “!” mark indicates that the base register needs to be
updated with the effective address after executing theinstruction.
 Pre-indexed: Immediate (cont.)

• Example

LDRr0, [r1, #4]!

before load
r0 0×00000000
Address Memory
r1 0×00009000 Base address 0×00009000 0×01010101
Effective address 0×00009004 0×02020202

after load
r0 0×02020202

r1 0×00009004 The base register is updated

with the immediate offset
 Pre-indexed: Immediate (cont.)

• Example:
STRr0, [r5, # -4]! ; Store word from r0 to location pointed to by contents of [r5, #-4]!

Before store Before store After store

r5 0×00006000
Address Memory Address Memory
r0 0×12345678 0×00005FF8 0×000000BE 0×00005FF8 0×000000BE
0×00005FFC 0×000000BA Effective address 0×00005FFC 0×12345678
After store -4
0×00006000 0×000000ED Base address 0×00006000 0×000000ED
r5 0×00005FFC
0×00006004 0×000000FE 0×00006004 0×000000FE
r0 0×12345678

The base register is updated

with the immediate offset
 Pre-indexed: Immediate
(cont.)
Example:

LDRD R8, R9, [R3, #0x20]

– Load R8 from the location pointed by (R3 + 32)
– Load R9 from the location pointed by (R3 + 36)
 Pre-indexed: Register

ii. Register pre-indexed

Syntax: op{type}{cond} Rt, [Rn, ± Rm]!

[Rn, ±Rm]!
• Address accessed is as with register offset mode, but Rn's
value updates to become the addressaccessed.

The optional “!” specifies writing the effective address back into Rn at the end of the
instruction. Without it, Rn contains its original value after the instruction executes.
• This type of incrementing is useful in stepping through tables or lists, since the
base address is automatically updated for you.
 Pre-indexed: Register (cont.)

• Example:
LDRr2,[r0, r1]!
Before load
Address Memory
r0 0×00006000
Base address 0×00006000 0×000000BE
r1 0×0000000C 0×00006004 0×000000BA
0×00006008 0×000000ED
r2 0×12345678
Effective address 0×0000600C 0×000000FE
After load
r0 0×0000600C The base register is updated
with the register value

r1 0×0000000C

r2 0×000000FE r2 is updated with the value

contained in the effective address
 Pre-indexed: Register (cont.)

• Example:
STRr2,[r0, r1]! ; Store word from r0 to location pointed to by contents of [r0, r1]!

Before store Before store After store

r0 0×00006000 Address Memory Address Memory

0×00006000 0×000000BE Base address 0×00006000 0×000000BE
r1 0×0000000C
0×00006004 0×000000BA 0×00006004 0×000000BA
r2 0×12345678 0×00006008 0×000000ED 0×00006008 0×000000ED
0×0000600C 0×000000FE Effective address 0×0000600C 0×12345678
After store
The content of base register r0 is
r0 0×0000600C
updated to become effective address

r1 0×0000000C
r1 and r2 do not
r2 0×12345678 change values
 Pre-indexed: Scaled-register

iii. Scaled register pre-indexed

Syntax: op{type}{cond} Rt, [Rn, ± Rm, shift]!

[Rn, ±Rm, shift]!

• Address accessed is as with scaled register offset mode, but Rn'svalue
updates to become the addressaccessed.
 Pre-indexed: Scaled-register (cont.)

• Example
LDRr0, [r1, r2, LSL#2]!
Before load
r0 0×12345678 Address Memory
Base address 0×00006000 0×000000BE r2×22 = C16×4 = 3016
r1 0×00006000 .
.
. r1 + 3016 = 0×00006030
r2 0×0000000C
Effective address 0×00006030 0×000000FE
After load
r0 0×000000FE Copy the value hold by effective
adress
r1 0×00006030 The value of r1 is updated with the
effective address
r2 0×0000000C
 Pre-indexed: Scaled-register (cont.)

• Example
STRr0, [r1, r2, LSL#2]!; Store word from r0 to location pointed to by contents of [r1, r2, LSL#2]!

Before store Before store After store

r0 0×12345678 Address Memory Address Memory

0×00006000 0×000000BE Base address 0×00006000 0×000000BE

r1 0×00006000 . .
. .
. .
r2 0×0000000C
0×00006030 0×000000FE Effective address 0×00006030 0×12345678
After store
r0 0×12345678 r0 remain the same r2×22 = C16×4 = 3016
The value of r1 is updated with the
r1 0×00006030 r1 + 3016 = 0×00006030
effective address

r2 0×0000000C
 Post-indexed: Immediate

i. Immediate post-indexed
Syntax (32 bit): op{type}{cond} Rt, [Rn] , #offset ; post-indexed (value range: -255 to
+255)
Syntax (64 bit): opD{type}{cond} Rt, [Rn] , #offset ; post-indexed, two words (value
range: -1020 to +1020)

[Rn], #±imm
• The address accessed is the value found in Rn, and then Rn's value is
increased/decreased by imm.

LDRr0, [r1],#6 ; r0 : = mem32 [r1]

; r1 : = r1 +6

This is called: post-indexed addressing - the base address is used

without an offset as the transfer address, after which it is auto-
indexed:(r1=r1+6)
 Post-indexed: Immediate (cont.)

Example:
LDRr2, [r1],#4 ; loads r2 with the contents of the address pointed to by r1 and then increments r1 by 4
Before load
Address Memory
r2 0×FEEDBABE
Base address 0×8000 0×AB

r1 0×00008000 0×8001 0×CD

0×8002 0×EF
0×8003 0×GH
After load
Content of r2 is updated with the
r2 0×GHEFCDAB
word contained in the base register

r1 0×00008004

After loading the value of r1(base

register) into r2, only then you can
update the base register according
to the immediate value
 Post-indexed: Immediate (cont.)

• Example:
STR r3, [r8], #4; store word from location r3 to the address pointed by r8 and then increment r8 by 4
What is the size of each memory
location? 1 byte or 1 word?

before store after store

before store Address Memory Memory
Address
r3 0×FEEDBABE
Base address 0×8000 0×AB Base address 0×8000 0×BE

r8 0×00008000 0×8001 0×CD 0×8001 0×BA

0×8002 0×EF 0×8002 0×ED
0×8003 0×GH 0×8003 0×FE
after store
r3 0×FEEDBABE
After storing the value of r3 into r8
(base register), only then you can
r8 0×00008004 update the base register according
to the immediate value
 Post-indexed: Immediate (cont.)

Example:

STRD R0, R1, [R8], #-16

– Store R0to the location pointed by R8
– Store R1 to the address pointed by (R8 + 4)
– Decrement R8 by 16
 Post-indexed: Register

ii. Register post-indexed

Syntax: op{type}{cond} Rt, [Rn], ± Rm

[Rn], ±Rm
• Address accessed is value found in Rn, and then Rn's value is
increased/decreased by Rm.
 Post-indexed: Register (cont.)

• Example
LDRr0, [r1], r2
Before load
r0 0×12345678 Address Memory
Base address 0×00006000 0×000000BE
r1 0×00006000
0×00006004 0×000000BA

r2 0×0000000C 0×00006008 0×000000ED

0×0000600C 0×000000FE
After load
r0 0×000000BE Load the word hold by the base
address
r1 0×0000600C
The value of r1 is increased by r2

r2 0×0000000C
 Post-indexed: Register (cont.)

• Example
STRr0, [r1], r2; store word from location r0 to the address pointed by r1 and then increment r1 by r2

Before store Before store After store

r0 0×12345678 Address Memory Address Memory

0×00006000 0×000000BE Base address 0×00006000 0×12345678

r1 0×00006000
0×00006004 0×000000BA 0×00006004 0×000000BA
r2 0×0000000C 0×00006008 0×000000ED 0×00006008 0×000000ED
0×0000600C 0×000000FE 0×0000600C 0×000000FE
After store
r0 0×12345678 r0 remain the same

r1 0×0000600C The value of r1 is increased by r2

r2 0×0000000C
 Post-indexed: Scaled-register

iii. Scaled register post-indexed

Syntax: op{type}{cond} Rt, [Rn], ± Rm, shift]

[Rn], ±Rm, shift

• Address accessed is the value found in Rn, and then Rn's value is
increased/decreased by Rm shifted according toshift.
• This is just shorthand for [Rn], ±Rm, LSL#0.
 Post-indexed: Scaled-register (cont.)

• Example
LDRr0, [r1], r2, LSL#2
Before load
r0 0×12345678 Address Memory
Base address 0×00006000 0×000000BE r2×22 = C16×4 = 3016
r1 0×00006000 .
.
. r1 + 3016 = 0×00006030
r2 0×0000000C
Effective address 0×00006030 0×000000FE
After load
r0 0×000000BE Copy the value hold by base
adress r1
r1 0×00006030 The value of r1 is updated with the
effective address
r2 0×0000000C
 Post-indexed: Scaled-register (cont.)

• Example
STRr0, [r1], r2, LSL#2
Before store Before store After store

r0 0×12345678 Address Memory Address Memory

0×00006000 0×000000BE Base address 0×00006000 0×12345678

r1 0×00006000 . .
. .
. .
r2 0×0000000C
0×00006030 0×000000FE Effective address 0×00006030 0×000000FE
After store
r0 0×12345678 r0 remain the same r2×22 = C16×4 = 3016
The value of r1 is updated with the
r1 0×00006030 r1 + 3016 = 0×00006030
effective address

r2 0×0000000C
 Comparison of addressing modes

ARM indexing modes

Mode ARM Assembly Effective Address Base Register
Offset LDR r0, [r1, r2] r1 + r2 Unchanged
Pre-index LDR r0, [r1, r2]! r1 + r2 r1 = r1 + r2
Post-index LDR r0, [r1], r2 r1 r1 = r1 + r2
 Exercise 1

Describe the contents of register r9 after the following

instructions, assuming that memory contains the values
shown below. Register r0 contains 0x30, and the memory
system is little-endian.
Address Memory
0×30 0×06
0×31 0×FC
0×32 0×03
0×33 0×FF

a. LDRSB r9, [r0]

b. LDR r9, [r0]
c. LDRSH r9, [r0]
d. LDRB r9, [r0]
 Exercise 2

Assume register r4 contains 0×6000. What would

be the content of register r4 after executing the
following instructions?
a. STR r6, [r4, #12]
b. STRB r7, [r4], #4
c. LDRH r5, [r4],#8
d. LDR r12, [r4, #12]!
 Exercise 3

Assuming you have a little-endian memory system, what would

register r9 contain after executing the following instructions?
Register r6 holds the value 0×ABCDEFFF and register r3 holds
0×6000.
STR r6, [r3]
LDRB r9, [r3]
 Exercise 4

1. Copy LDR r1, =TABLE1 ; TABLE1=0x0002 0000

2. LDR r2, =TABLE2 ; TABLE2=0x0004 0000
3. LDR r0, [r1] ; load first value ….
4. STR r0, [r2] ; and store it inTABLE2
5. LDR r0, [r1, #4] ; load second value
6. STR r0, [r2, #4] ; and store it
(all in hex)
After r0 r1 r2 0002 0000- 0002 0004- 0004 0000- 0004 0004-
Line
0002 0003 0002 0007 0000 4003 0004 0007
1 0000 0000 0002 0000 0000 0000 1357 2468 A123 B246 0 0
2
3
4
5
6

37
 Exercise 5

1. Copy LDR r1, =TABLE1 ; TABLE1=0x0002 0000

2. LDR r2, =TABLE2 ; TABLE2=0x0004 0000
3. LDR r0, [r1] ; load first value ….
4. STR r0, [r2] ; and store it inTABLE2
5. LDR r0, [r1, #4]! ; load second value, r1 will change
6. STR r0, [r2, #4]! ; and store it, r2 will change too

(all in hex)
After
r0 r1 r2 0002 0000- 0002 0004- 0004 0000- 0004 0004-
line
0002 0003 0002 0007 0004 0003 0004 0007
1 0000 0000 0002 0000 0000 0000 1357 2468 A123 B246 0 0
2
3
4
5
6

38
 Exercise 6

State ONE (1) assembly instruction to perform action as shown in the followingdiagram.

Before load
r0 0×12345678 Address Memory
0×00006000 0×000000BE
r1 0×00006000 .
.
r2 0×0000000C .
0×00006060 0×0000008F
After load
r0 0×0000008F

r1 0×00006000

r2 0×0000000C

Answer:
 Answer Exercise 1

Describe the contents of register r9 after the following

instructions complete, assuming that memory contains
the values shown below. Register r0 contains
0x00000030, and the memory system islittle-endian.
Address Memory
0×30 0×06
0×31 0×FC
0×32 0×03
0×33 0×FF

a. LDRSB r9, [r0]  r9 = 0x00000006

b.LDR r9, [r0]  r9 = 0xFF03FC06
c.LDRSHr9, [r0]  r9 = 0xFFFFFC06 d.
LDRB r9, [r0]  r9 = 0x00000006
 Answer Exercise 2

Assume register r4 contains 0×00006000. What would the

register r4 contain after executing the following
instructions?
a.STR r6, [r4, #12]  r4 = 0x00006000 (offset, base register unchanged)
b.STRB r7, [r4], #4  r4 = 0x00006004 (post-indexed, base register changed)
c. LDRH r5, [r4], #8  r4 = 0x00006008 (post-indexed, base register changed)
d. LDR r12, [r4, #12]!  r4 = 0x0000600C (pre-indexed, base registerchanged)

3. Assuming you have a little-endian memory system,what

would register r9 contain after executing the following
instructions? Register r6 holds the value 0×ABCDEFGH and
register r3 holds 0×00006000.
STR r6, [r3]  r3 0x00006000 0X00006000 0xABCDEFGH
LDRB r9, [r3]  r9 = 0x000000GH
 Answer Exercise 3

3. Assuming you have a little-endian memory system,what

would register r9 contain after executing the following
instructions? Register r6 holds the value 0×ABCDEFFF and
register r3 holds 0×00006000.
STR r6, [r3]  r3 0x00006000 0X00006000 0xABCDEFGH
LDRB r9, [r3]  r9 = 0x000000FF
 Answer Exercise 4
1. Copy LDR r1, =TABLE1 ; TABLE1=0002 0000
2. LDR r2, =TABLE2 ; TABLE2=0004 0000
• 3. LDR r0, [r1] ; load first value ….
4. STR r0, [r2] ; and store it inTABLE2
5. LDR r0, [r1, #4] ; load second value
6. STR r0, [r2, #4] ; and store it
(all in hex)
After r0 r1 r2 0002 0000- 0002 0004- 0004 0000- 0004 0004-
Line
0002 0003 0002 0007 0000 4003 0004 0007
1 0000 0000 0002 0000 0000 0000 1357 2468 A123 B246 0 0
2 0000 0000 0002 0000 0004 0000 1357 2468 A123 B246 0 0
3 1357 2468 0002 0000 0004 0000 1357 2468 A123 B246 0 0
4 1357 2468 0002 0000 0004 0000 1357 2468 A123 B246 1357 2468 0
5 A123 B246 0002 0000 0004 0000 1357 2468 A123 B246 1357 2468 0
6 A123 B246 0002 0000 0004 0000 1357 2468 A123 B246 1357 2468 A123 B246

43
 Answer Exercise 5

1. Copy LDR r1, =TABLE1 ; TABLE1=0x0002 0000

2. LDR r2, =TABLE2 ; TABLE2=0x0004 0000
3. LDR r0, [r1] ; load first value ….
4. STR r0, [r2] ; and store it inTABLE2
5. LDR r0, [r1, #4]! ; load second value, r1 will change
6. STR r0, [r2, #4]! ; and store it, r2 will change too
(all in hex)
After
r0 r1 r2 0002 0000- 0002 0004- 0004 0000- 0004 0004-
line
0002 0003 0002 0007 0004 0003 0004 0007
1 0000 0000 0002 0000 0000 0000 1357 2468 A123 B246 0 0
2 0000 0000 0002 0000 0004 0000 1357 2468 A123 B246 0 0
3 1357 2468 0002 0000 0004 0000 1357 2468 A123 B246 0 0
4 1357 2468 0002 0000 0004 0000 1357 2468 A123 B246 1357 2468 0
5 A123 B246 0002 0004 0004 0000 1357 2468 A123 B246 1357 2468 0
6 A123 B246 0002 0004 0004 0004 1357 2468 A123 B246 1357 2468 A123 B246

44
 Answer Exercise 6

• LDRr0, [r1, #96] or LDRr0, [r1, #0x60]

• LDRr0, [r1, r2, LSL#3]