1) If r0=0x00000000, r1=0x80000004

Find the content of the registers r0 and r1 after the following instructions are executed in
isolation. Mention if the CPSR register is updated or not.
(i) MOV r0,r1 (ii) MOV r0,r1,LSL #1 (iii) MOVS r0,r1,LSL #1 (iv) MVN r0,r1 (v) MOV r0,r1,LSR #1
(i) (ii)
Pre : r0=0x80000004 Pre: r0=0x00000000
r1=0x80000004 r1=0x80000004 =1000 0000 0000 0000 0000 0000 0000 0100 in binary.
MOV r0,r1 MOV r0,r1,LSL #1 ;After 1 bit logical shift left(LSL), the value is 0000 0000
Post : r0=0x80000004 0000 0000 0000 0000 0000 1000 which is copied to r0.
r1=0x80000004. Post: r0=0x00000008
CPSR is not updated. r1=0x80000004.
CPSR is not updated.

(iv) Pre: r0=0x00000000, (iii)

r1=0x80000004 Pre: r0=0x00000000
MVN r0,r1 r1=0x80000004=1000 0000 0000 0000 0000 0000 0000 0100 in binary.
;NOT of r1 is 0111 1111 1111 1111 MOVS r0,r1,LSL #1 ;After 1 bit logical left shift (LSL), the value is 0000 0000
1111 1111 1111 1011=0x7ffffffb is 0000 0000 0000 0000 0000 1000 which is copied to r0.Most significant bit (MSB) is
copied to ro. copied to the carry flag and carry flag is set.
Post: r0=0x7ffffffb Post: r0= 0x00000008
r1=0x80000004. r1=0x80000004.
CPSR is not updated. CPSR is updated. ; cpsr = nzCvqift_USER
(v)
Pre: r1=0x80000004 ; =1000 0000 0000 0000 0000 0000 0000 0100 in binary.
MOV r0,r1,LSR #1 ;After 1 bit logical shift right (LSR), the value is 0100 0000 0000
0000 0000 0000 0000 0010 which is copied to r0.
Post:
r0=0x40000002
r1=0x80000004.
CPSR is not updated.
2) If r0=0x00000000, r1=0x00000002 and r2=0x00000001
Find the content of the register r0, r1 and r2 after the following instructions are executed in isolation. Mention if the
CPSR register is updated or not.
(i) ADD r0,r1,r2,LSL #1 (ii) SUB r0,r1,r2 (iii) RSB r0,r1,#0 (iv) SUBS r1,r1,#2
(i) Pre: r2=0x00000001 ;=0000 0000 0000 0000 (ii) Pre: r0=0x00000000
0000 0000 0000 0001. r1=0x00000002
ADD r0,r1,r2,LSL #1 ; After logic shift left(LSL) it is r2=0x00000001
0000 0000 0000 0000 0000 0000 0000 0010=0x00000002 SUB r0,r1,r2
which is added to r1 and the result is at r0. Post: r0=0x00000001
Post: r0=0x00000004 r1=0x00000002
r1=0x00000002 r2=0x00000001
r2=0x00000001 CPSR is not updated.
CPSR is not updated.

(iii) r0=0x0-r1=-r1 which is copied to r0 as 2’s complement of (iv) ) Pre: r0=0x00000000

r1. r1=0x00000002
r1=0x00000002=0000 0000 0000 0000 0000 0000 0000 0010 r2=0x00000001
1’s complment=1111 1111 1111 1111 1111 1111 1111 1101 SUBS r1,r1,#2
2’s complment=1111 1111 1111 1111 1111 1111 1111 Post: r0=0x00000000
1110=0xfffffffe r1=0x00000000
Hence, r0=0xfffffffe, r1=0x00000002 and r2=0x00000001. r2=0x00000001
CPSR is not updated. CPSR is updated (Zero flag is set).
3) If r0=0x00000000, r1=0x02040608 and r2=0x10305070
Find the content of the register r0 after the following instructions are executed in isolation and also mention if the
CPSR register updated or no
(i) AND r0,r1,r2 (ii) ORR r0,r1,r2 (iii) BIC r0,r1,r2

(i) r1=0x02040608=0000 0010 0000 0100 0000 0110 0000
1000
r2=0x10305070=0001 0000 0011 0000 0101 0000 0111
0000
Hence, r0=0000 0000 0000 0000 0000 0000 0000
0000=0x00000000
After execution of AND r0,r1,r2 , r0=0x00000000,
r1=0x02040608 and r2=0x10305070
(ii) r1=0x02040608=0000 0010 0000 0100 0000 0110 0000
1000
r2=0x10305070=0001 0000 0011 0000 0101 0000 0111
0000
Hence, r0=0001 0010 0011 0100 0101 0110 0111
1000=0x12345678
After execution of ORR r0,r1,r2 , r0=0x12345678,
r1=0x02040608 and r2=0x10305070

(iii) r2=0x10305070=0001 0000 0011 0000 0101 0000 0111 0000

NOT r2=1110 1111 1100 1111 1010 1111 1000 1111
r1=0x02040608=0000 0010 0000 0100 0000 0110 0000 1000
r0=r1 AND (NOT r2)=0000 0010 0000 0100 0000 0110 0000 1000=0x02040608
After execution of BIC r0,r1,r2 , r0=0x02040608, r1=0x02040608 and r2=0x10305070. CPSR is not updated
4) If r1=0x00000002 and r2=0x00000002
Find the content of the register r1 and r2 after the following instructions are executed in isolation and also mention
if the CPSR register is updated or not.
(i) CMP r1,r2 (ii) CMN r1,r2 (iii) TST r1,r2 (iv) TEQ r1,r2
(i) After execution, r1=0x00000002 and r2=0x00000002. CPSR (ii) After execution, r1=0x00000002 and r2=0x00000002.
is updated (Zero flag is set if r1-r2=0). CPSR is not updated (Zero flag is set if r1+r2=0).

(iii) After execution, r1=0x00000002 and (iv) After execution, r1=0x00000002 and
r2=0x00000002.CPSR is updated (Zero flag is set if Exclusive r2=0x00000002.CPSR is not updated (Zero flag is set if AND of
OR of r1and r2=0). r1and r2=0).
5) If r0=0x00000000, r1=0x00000001, r2=0x00000002 and r3=0x00000003
Find the content of the register r0, r1, r2 and r3 after the following instructions are executed in isolation. Mention if
the CPSR register is updated or not.
(i) MUL r0,r1,r2 (ii) MLA r0,r1,r2,r3 (iii) UMULL r0,r1,r2,r3
(i) (ii)
Pre: r0=0x00000000 Pre: r0=0x00000000
r1=0x00000001 r1=0x00000001
r2=0x00000002 r2=0x00000002
r3=0x00000003 r3=0x00000003
MUL r0,r1,r2 ; r0=r1*r2 MLA r0,r1,r2,r3 ; , r0=r1*r2+r3
Post: r0=0x00000002 Post: r0=0x00000005
r1=0x00000001 r1=0x00000001
r2=0x00000002 r2=0x00000002
r3=0x00000003 r3=0x00000003

(iii)
Pre: r0=0x00000000
r1=0x00000001
r2=0x00000002
r3=0x00000003
UMULL r0,r1,r2,r3 ; [r0,r1]=r2*r3
Post: r0=0x00000006, r1=0x00000000, r2=0x00000002 and r3=0x00000003
6) If r0=0x00000000, r1=0x00090000
mem32[0x00090000]=0x01010101 and mem32[00090004]=0x02020202
Find the content of the register r0, r1 after the following instructions are executed in isolation.
(i) LDR r0,[r1,#4] (ii) LDR r0,[r1,#4]! (iii) LDR r0,[r1],#4
(i) (ii) After the execution, r0=0x02020202 and r1=0x00090004
Pre: r0=0x00000000
r1=0x00090000
mem32[0x00090000]=0x01010101
mem32[00090004]=0x02020202
LDR r0,[r1,#4]
Post: r0=0x02020202
r1=0x00090000

(iii) After the execution, r0=0x01010101 and r1=0x00090004

7) If r0=0x00000010, r1=0x00000000, r2=0x00000000, r3=0x00000000
mem32[0x00000010]=0x00000001 and mem32[00000014]=0x00000002
mem32[0x00000018]=0x00000003 and mem32[0000001c]=0x00000004
Find the content of the register r0, r1,r2 and r3 after the following instructions are executed in isolation.
(i) LDMIA r0!, {r1-r3} (ii) LDMIB r0!, {r1,r2,r3}

(i) (ii) After the execution, r0=0x0000001c, r1=0x00000002,

Pre: r0=0x00000010 r0=0x00000003 and r0=0x00000004
r1=0x00000000
r2=0x00000000
r3=0x00000000
mem32[0x00000010]=0x00000001
mem32[00000014]=0x00000002
mem32[0x00000018]=0x00000003
mem32[0000001c]=0x00000004
LDMIA r0!, {r1-r3}
Post: r0=0x0000001c
r1=0x00000001
r0=0x00000002
r0=0x00000003