CHAPTER 3_2: ARM

ASSEMBLY LANGUAGE
PROGRAMMING
BENM 2123: MICROPROCESSOR
TECHNOLOGY

DATA TRANSFER INSTRUCTIONS: LOADS,

STORES
Outline
• Introduction
• Loads and Stores
• LDR, LDRB, LDRH, LDRSB, LDRSH
• STR, STRB, STRH
• ADR
Introduction
The ARM is a Load/Store Architecture:
– Only load and store instructions can access memory
– Does not support memory to memory data processing
operations.
– Must move data values into registers before using them.

Data transfer instructions transfer data between registers

and memory:
• Memory to register (LDR)
• Register to memory (STR)
How we can operate the data inside
memory?
• In ARM architecture, data must place in register before performing basic
operations

• You can’t perform operation directly to memory

Data Register
Data

Register
Data
Data

Memory Memory
Memory to memory data processing is not allowed because it can slow
down the memory access. Therefore, all data operation needs to be
done in register before transfer it back to memory.
Loads and Stores – The instructions
• The ARM has three sets of instructions which interact with main
memory. These are:
• Single register data transfer (LDR/STR)
• Block data transfer (LDM/STM)
• Single Data Swap (SWP)

• Load – take a single value from memory and write it to general

purpose register. (MEMORY  REGISTER)
• Store – read a value from a general purpose register and store it to
memory. (REGISTER  MEMORY)
• Memory system must support all access sizes
• Syntax:
LDR{<cond>}{<size>} Rd, <address>
STR{<cond>}{<size>} Rd, <address>

Signed or not? Byte? Destination Addressing

halfword? register mode
Word?
• Example: LDR r0, [r1, #12]
Loads and Stores (cont.)
Most often used Load/Store instructions
Components of any computer
Data Transfer: Memory to Register (LDR)
• To transfer a word of data, we need to specify two things:
• Register: r0-r12
• r13 – stack pointer, r14: link register, r15: PC
• How to access the memory?
• Think of memory as a single one-dimensional array, so we can address it
simply by supplying a pointer to a memory address.
• Besides pointer, we also need to identify the base register. Base register
will point to the beginning of the memory array.

Base register
A register which contains a pointer to memory
Example: [r0]
• specifies the memory address pointed to by the value in r0
• This is called register indirect addressing
Data Transfer: Memory to Register (LDR)
Load Instruction Syntax:
Data flow
LDR r1, [r0] ; Load r1 with contents of memory location pointed to by
contents of r0.
where
1) operation name (LDR)
2) register that will receive value (r1)
3) register containing pointer to memory/base register [r0]

• ARM Instruction Name:

• LDR(meaning Load Register, so 32 bits or one word are loaded at a time)

1 r0 contains the memory

address that it points in 2 3
the memory

0x00000200 0x00000200
0x12345678
r1 0x12345678
r0
Base register 0x00000204 The value contained in memory
location 0x00000200 is loaded in r1
0x00000208

0x0000020C
Data Transfer: Register to Memory (STR)
Store Instruction Syntax:

Data flow
STR r0,[r1] ; Store contents of r0 to location pointed to by contents
where of r1

1) operation name (STR)

2) register that will transfer value (r0)
3) register containing pointer to memory/base register [r1]
1
3
Base register
0x5
r1 0x00000200 0x00000200

0x00000204

0x00000208
2 0x0000020C
r0 contains value 0x5 Write the value 0x5
contained in r0 to
r0 0x5 memory location
pointed to by r1
Loads and Stores (cont.)
Loads
LDR

Example:
Consider the instruction
LDR r9, [r0] ; load a word into r9

Assuming the address in register r0 is 0x6000, before and after the

instruction is executed, the data appear as follows:
Before load
r0 0×00006000 Address
0×6000 0×EE
r9 0×12345678
0×6001 0×FF
After load 0×6002 0×80
r0 0×00006000 0×6003 0×A7

r9 0×A780FFEE
Loads (cont.)
LDRB

Example:
Consider the instruction
LDRB r9, [r0] ; load a byte into r9

Assuming the address in register r0 is 0x6000, before and after the

instruction is executed, the data appear as follows:
Before load
r0 0×00006000 Address Memory
0×6000 0×EE
r9 0×12345678
0×6001 0×FF
After load 0×6002 0×80
r0 0×00006000 0×6003 0×A7

r9 0×000000EE
Loads (cont.)
LDRH

Example:
Consider the instruction
LDRH r9, [r0] ; load a halfword into r9

Assuming the address in register r0 is 0x6000, before and after the

instruction is executed, the data appear as follows:

Before load
r0 0×00006000 Address Memory
0×6000 0×EE
r9 0×12345678
0×6001 0×FF
After load 0×6002 0×80
r0 0×00006000 0×6003 0×A7

r9 0×0000FFEE
Loads (cont.)
LDRSB

Example:
Consider the instruction
LDRSB r9, [r0] ; load signed byte into r9

Assuming the address in register r0 is 0x6000, before and after the instruction is
executed, the data appear as follows:

Before load
r0 0×00006000 Address Memory
0×6000 0×EE
r9 0×12345678
0×6001 0×8C
After load 0×6002 0×80
r0 0×00006000 0×6003 0×A7

r9 0×FFFFFFEE
Loads (cont.)
LDRSH

Example:
Consider the instruction
LDRSH r9, [r0] ; load signed half into r9

Assuming the address in register r0 is 0x6000, before and after the instruction is
executed, the data appear as follows:

Before load
r0 0×00006000 Address Memory
0×6000 0×EE
r9 0×12345678
0×6001 0×8C
After load 0×6002 0×80
r0 0×00006000 0×6003 0×A7

r9 0×FFFF8CEE
Stores
STR

Example:
Consider the instruction
• STR r9, [r0] ; Store word from r9 to location pointed to by contents of r0

Assuming the address in register r0 is 0x6000, before and after the instruction is
executed, the data appear as follows:

Before store Before store After store

r0 0×00006000
Address Memory Address Memory
r9 0×12345678 0×6000 0×BE 0×6000 0×78
0×6001 0×BA 0×6001 0×56
After store
0×6002 0×ED 0×6002 0×34
r0 0×00006000
0×6003 0×FE 0×6003 0×12
r9 0×12345678
Stores
STRB

Example:
Consider the instruction
• STRB r9, [r0] ; Store byte from r9 to location pointed to by
contents of r0

Assuming the address in register r0 is 0x6000, before and after the

instruction is executed, the data appear as follows:

Before store Before store After store

r0 0×00006000
Address Memory Address Memory
r9 0×12345678 0×6000 0×BE 0×6000 0×78
0×6001 0×BA 0×6001 0×BA
After store
0×6002 0×ED 0×6002 0×ED
r0 0×00006000
0×6003 0×FE 0×6003 0×FE
r9 0×12345678
Stores
STRH

Example:
Consider the instruction
• STRH r9, [r0] ; Store halfword from r9 to location pointed to by
contents of r0

Assuming the address in register r0 is 0x6000, before and after the instruction is
executed, the data appear as follows:

Before store Before store After store

r0 0×00006000
Address Memory Address Memory
r9 0×12345678 0×6000 0×BE 0×6000 0×78
0×6001 0×BA 0×6001 0×56
After store
0×6002 0×ED 0×6002 0×ED
r0 0×00006000
0×6003 0×FE 0×6003 0×FE
r9 0×12345678
Load an address into register
• Note that all addressing modes are register offseted. Can
we issue LDR r0, Table?
• The pseudo instruction ADR loads a register with an
address

table: .word 10
…..
ADR r0, table
Load an address into register (cont.)
Application of ADR
ADR loads the register with the address of
the operand
ADR
• Retrieve the address of ROM constants

• label
• Location of stored variable of which its address is to be loaded into
Rd
• Label must be within -4095 and +4095 of the current program
counter value
• In other words, ADR makes Rd the pointer to the constant
label
ADR example
ADR R0, lit ; returns the address of lit
LDR R2, [R0], #4 ; load 0x12345678 into R2
; increment R0 by 4
; to point to next value
LDR R3, [R0] ; load 0x88888888 into R3

lit DCD 0x12345678, 0x88888888 ; stored in ROM

• ADR is best for

• Pointing to strings stored in ROM
• Pointing to constants stored in ROM
• Filter coefficients, encryption keys, etc.