Computer Architecture

Lecture 2

Abhinav Agarwal
Veeramani V.
Quick Recap

 Various metrics in design of processor

 The interface & internal structure
 Instruction Set Architecture
 Assembly instructions
 Instruction encoding

add r1, r2, r3

000111 00001 00010 00011

Outline

 RISC
 Multi-cycle execution
 Pipelining
Reduced Instruction Set Computer
(RISC)
 Limited no. of instructions
 Fixed Length
 Simple to decode
 Easier to implement in hardware
 Prevalent in all commercial processors at the core
level
 Counterpart – C(omplex)ISC
 Intel processors
 Multi-operation instructions
 Still Intel processors have switched to RISC at second level
Execution Cycle of a RISC
Instruction
Five main phases of Instruction Lifecycle

1. IF: Instruction Fetch

 Read Instruction Memory at PC
 Bring the instruction into the CPU
2. ID/RF: Instruction Decode/Register Fetch
 Translate the opcode of the instruction to appropriate control
signals
 No. of operands
 Registers clearly specified in instruction code
 Fetch operand values from the registers
Execution Cycle of a RISC
Instruction
3. EX: ALU computation
 Activate appropriate functional unit – Adder, Multiplier, Divider,
Logical Unit
 Why no Subtracter?

4. MEM: Memory Operation

 Load/Store data from/to Data Memory

5. WR: Register Write

 Write the final result value into register
A Picture speaks a thousand words
Multi Cycle Execution

 Cycle Per Instruction (CPI)

 Kinds of Implementation:
1. One cycle for each stage
 Cycle time determined by longest stage
 CPI = ?
2. Combine all stages into a single cycle
 Cycle time determined by worst case instruction
 CPI = 1
Execution Snapshot: Cycle 1 IF

PC
00010
000111 00001 00010 00011

Address Instr
00000 Mov r2, 2A
00001 Mov r3, 12
00010 Add r1,r2,r3
00011 Store r1,0(r4)
00100 XXXX
00101 XXXX
Execution Snapshot: Cycle 2 ID/RF

PC Reg Data
00011 r1 12 H
000111 00001 00010 00011
Add
r2 2A H
r3 12 H
Address Instr
r4 00 H
00000 Mov
r5 01 H
r1,

00001 Mov
00010 add
00011 Store
r2,

00100 XXXX
00101 XXXX
r3
Execution Snapshot: Cycle 3 EX

PC Reg Data
00011 r1 12 H
000111 00001 00010 00011
Add
r2 2A H
r3 12 H
Address Instr
r4 00 H 12 2A
00000 Mov
r5 01 H
r1,

00001 Mov
00010 add Adder
00011 Store
r2,

00100 XXXX
00101 XXXX
r3
Execution Snapshot: Cycle 4 MEM

PC Reg Data
00011 r1 12 H
000111 00001 00010 00011
Add
r2 2A H
r3 12 H
Address Instr
r4 00 H 12 2A
00000 Mov
r5 01 H
r1,

00001 Mov
00010 add Adder
00011 Store
r2,

00100 XXXX ??
00101 XXXX
r3
Execution Snapshot: Cycle 5 WB

PC Reg Data
00011 r1 3C H
000111 00001 00010 00011
Add
r2 2A H
r3 12 H
Address Instr
r4 00 H
00000 Mov
r5 01 H
r1,

00001 Mov
00010 add Adder
00011 Store
r2,

00100 XXXX
00101 XXXX
r3
Execution Snapshot: Cycle 1 IF

PC
00011
111001 00001 00100 00000
store
Address Instr
00000 Mov
r1,

00001 Mov
00010 add
00011 Store
0(r4)

00100 XXXX
00101 XXXX
Instruction Execution Timeline

 Sequential Execution
 Low utilization of functional units
 Alternative ?

add r1, r2, r3 store r1, 0(r4)

IF ID/ EX ME WB IF ID/ EX ME IF ID/ EX ME WB
RF M RF M RF M

Instruction Execution Timeline

Pipelining: Concept and Example

 Washing machine, Dryer, Iron

source: http://cse.stanford.edu/class/sophomore-college/projects-00/risc/pipelining/
Pipelining Concept

 Remarkable Insight or Common Sense

Time Savings:
Per person 0%
Overall 42%

source: http://cse.stanford.edu/class/sophomore-college/projects-00/risc/pipelining/
 Implementation of Pipelining in
RISC
 Parallelism in all 5 stages
 New instruction every cycle
 Best case scenario
Inst
IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
IF ID/RF EX MEM WB
Time
Hardware Requirements

source: http://cse.stanford.edu/class/sophomore-college/projects-00/risc/pipelining/
Problems
 Data hazards
 Dependent Instructions
 add r1, r2, r3
IF ID/RF EX MEM WB
 store r1, 0(r4)
IF ID/RF EX MEM WB

 Control Hazards
 Branches resolution
IF ID/RF EX MEM WB
 bnz r1, label
IF ID/RF EX MEM WB
 add r1, r2, r3
IF ID/RF EX MEM WB
 label: sub r1, r2, r3

 Structural Hazards
References

 Wikipedia: CPU Parallelism

http://en.wikipedia.org/wiki/Central_processing_unit#Parallelism

 http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/pipe_title.html