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VLSI DESIGN
UNIT-1

LECTURE-1

• Till 1950s the electronic technology was vacuum tube based.

• 1947,transistor invention by William B Shockley et al revolutionised the
field of electronics.
• Integrated circuit era has began in 1960s.
• Quest to integrated more devices per chip has resulted transition from
SSI(Small Scale Integration) to LSI (Large Scale Integration)to VLSI(Very
Large Scale Integration) with 10 to 100 million devices per chip.
• Measure of Progress- determined by number of transistors per chip,
size of the chip, process technology used within.
To produce smaller, faster, more reliable and less expensive systems
which consume less power.
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Moore’s Law
• Intel co-founder Gordon Moore is a visionary
published his paper “Cramming more
components onto integrated circuits” in
Electronics, Volume 38, Number 8, April 19, 1965

• His bold prediction, popularly known as Moore's Law, states that the
number of transistors on a chip will double approximately every two years.
• Intel, which has maintained this pace for decades, uses this golden rule as
both a guiding principle and a springboard for technological
advancement, driving the expansion of functions on a chip at a lower cost
per function and lower power per transistor, by shrinking feature sizes while
introducing new materials and transistor structures.

Technology Road Map

• Transistor size and structure are at the very centre of delivering the
benefits of Moore's Law to the end user.
• The smaller and more power efficient the transistor, the better.
• Intel continues to predictably shrink its manufacturing technology in a
series of "world firsts": 45nm with high-k/metal gate in 2007; 32nm in 2009;
and now 22nm with the world's first 3-D transistor in a high volume logic
process beginning in 2011.
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• With a smaller, 3-D transistor, Intel can design even more powerful
processors with incredible power efficiency. The new technology enables
innovative microarchitectures, System on Chip (SoC) designs, and new
products–from servers and PCs to smart phones, and innovative consumer
products.
• Next generation is 14nm is expected to rule the product market by 2015.

System Integration Complexity Roadmap

• Lowering the supply voltages
and channel lengths together
with increasing transistor per
chip ratios result in system with
more efficient, smaller in size
and can be packed at
significantly higher density.

• Challenges are posed by smart

appliances (eg Soc),complex
imaging systems to silicon CMOS
technologies demanding low
power high performance .

• Major challenges due to constraints on power density(W/cm 2),high dynamic

ands static power dissipation.
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Successful designs are dependent on system design

cycle and workable transistor models.
System design cycle flow chart of arithmetic processor
(fundamental problem at hand to physical layout with low power and min
areas as important design criteria)

Transistor models are characterized by figure of merit that depends on

• Performance,
• level of integration and cost.
• Cost.
• Minimum Feature size.
• Number of gates
• Power of dissipation
• Gate delay.
• Die Size.
Within the bound of MOS technology the
• Testing possible circuit realizations are based on
• Reliability. pMOS,nMOS,CMOS and BiCMOS devices.
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Comparison between CMOS and Bipolar Transistors

Speed Power Performance of available technologies