‘About College RAGHU Isat of Technology is estab in 207 by 2 ‘roup of eminent personalities inte eld ot enenerng ‘pportnite for doing meaning recere: The compu of ‘og Intute of Technlory leat on» spawing 10 cer ofan st Datamar Vilage imamate Ma ‘tii Sc (Ah a Sant aorbe ‘hatege tothe ocaere stations to provide cualed eight Theor, Rag nse of Technlagy ses fo ‘up the sets wth reqaed conceptual teil end {ain quaitedprotestinalin the held of ence cater {he tcisteey ents of the suety end soci te ‘verchaning business esponsbles tational andi. [About Department {our yor dere prosam n leaves a communeaton Engncring with on ota take of 80 suse ond ‘Miech Po program in Embedded sytem & Vis (ESE) ‘nan sont ae ot 8 ude sir ef cco an eto ray dere a ‘Sas numbers intreaneced computer duane Sn Sipe, cet ean, Ste nd ‘The Department conducts Clog, an annua ational ieee mpi at res run te inom som the county pra, rest ope ‘Address for Correspondence alt smecredaiee ort Faculty Development Program AICTE Spontored Two Week FOP on Cee Re Ly ‘ohne eno bapa AP S162 Sponsor cerifeate SEER ET cea ee cae rice Att Faculty Development Program AICTE Sponsored Two Week FOP on. Design Challenges in Deep Sub Micron Technology Sth to 19th Aug, 2019 Convener Prof.P'SR Chowdary, Ph.D Coordinator Dr.VVSSS Chakravarthy Co-Coordinators Mr. BS SV Ramesh Babu ‘Mr. Anil Kumar Patnaik DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING RAGHU INSTITUTE OF TECHNOLOGY ‘omrve iy Mere eh ered by Pemaniegur 3) aan ene ‘apna them Rana ata 16.Chief Patrons Sri Kalidind! Raghs, Chairman, Raghu Educato ‘Smt. K:Rama Devi, ‘Secretary Raghu Educational Institutions Patrons Sri Rah Vo Director, Raghu Educational Institutions ProfS.Satyannarayana, Principal, Raghu Institute OF Technology Convener Dr. Satish Rama Chowsary, Raghs Institute of Technology Organizing committee Dr Sonal Dash Avant Pte Mr PUK Durga rata nen Me Suresh nora Mr Chandra Salar, Asta tee Me Santosh Kamar Asner tt Me P Py Rey rus one MeKPhaneendn Attn Mes rigor it re MeV Reeth Kran sent Mrs Kasuma Van ron Me Akash Kamar Gupta, ost Pee MSM Divy tnt Ptr Mrs Lash stn ter MeN Srinivas Gupta, ns tr ‘Mr Arun Kumar AP yaks eee ‘About the Program ‘tonal ination The uses oe ee severe then te {ton {UObMS wecheiogy espe analog eat on deep Sbtmcon proces tchneloges (2.2216, 10,7, 5m) hat etc etiege tole is oles taba aera lesiage carer ar demanded by low power deg for ‘modern anamebie ospts the Nesaoom renin out na procesnghos toes ecologic catenges Tas po Objectives content repose cae me ptt pac sete ace ons erent eta eeeaes ie aces teesareecnaee exits caesar tears Exp nearer ieee ee eee eee Foe al eeenitentte a eden topiin system Ts rng wt oo be mieuotan veneer yuuiaan eee alee Prerequisites for the Course + Knowledge on asc ect es, 1 Yow on VSI design concent. 1 bisc noulagge on CAD tole Important Dates + tat eae for epsation ‘ination tothe pertinent 2st ty 2019 25th uy 2018 ‘Course Outline Course consist of series of lectures onthe following ‘topics along with hands on ‘Tends Chatlenges ae Opportunies in less Implementation of Signal processing Algorithm on FPGA destin 1 System on Chip Design wing FPGA * Mleresectrone Devices and Cres net of Vt Resource Persons +b aya Sankara Roo Pasupureda, University of Hyderabad Prot Samat saat, Univers of iderabad * Dr Balj Profesr HOD & Vie rnp INTUK UCEN, +b vert Narayan ao, BM/GLOBALFOUNORIES +b Subrahmanya Soaps tl Bangalore ‘course Program ‘The Course program has thee sections: + course end fam (MCabased questions) Registration epson ees atestpsenicipn ae pero, Tarren Taped [ROT Tague ne aa Ee The few refndable Aegon hep et pot cop ay ‘Aoi ened marge ke ‘minor TH MUL pte te stim Melanesia imam a ned ‘renee ney = screed + iene ptt pe mms