Title : Power Aware Efficient Techniques for side Channel Attacks

Mainly we are concentrating on Differential Power Analysis Attacks and Leakage Power
Analysis Attcaks

Objective:

• Defining the leakage currents in the design and applying LPA and defining the Alioto’s
attack.

• Applying the Leakage reduction techniques to counter act against LPA attack and
making the circuit LPA resistant.

• Finally applying the Monte Carlo Simulations and verifying the results with process
variations. (Optional)

Till date the two papers published and one paper is communicated (These papers were
presented in review meeting but rejected by panel by saying not upto the mark)

 “CALPAN: Counter measure against Leakage Power Analysis attack by

Normalized DDPL”, IEEE ICCPCT 2016.
Abstract— This paper proposes novel techniques against Leakage Power Analysis (LPA)
attack on Dual-Rail Precharge Logic (DDPL) which is a Differential Power Analysis (DPA)
resistant logic style. DDPL is first applied with sleep transistors technique and second with
Normalization technique by which the Cryptosystem is made LPA resistant. Security metrics
used for assessing the proposed logic styles are the leakage power and Coefficient of Deviation
(CoD). By analyzing the leakage power traces secret key can be extracted, as the leakage power
is data dependent. The leakage power dissipated by the Cryptosystem cannot be avoided
completely but it can be reduced by which LPA attack can be avoided. To avoid LPA attack,
leakage power should be made independent of data that is getting processed in the
Cryptosystem. This paper concentrates on leakage power analysis of DDPL NAND applied
with novel techniques and defines the leakage power and CoD. The logic styles are
implemented and analyzed using Cadence© GPDK 45nm technology node. In the proposed
method sleep transistor technique is applied to DDPL by which the power consumption is
double the normal DDPL but the data dependency CoD has been reduced by 20% and with the
novel Normalized DDPL technique, power consumption is reduced by 30% and the CoD has
been reduced by 89.4% which implies that the power traces are made equal for all the input
combinations by which LPA attack can be avoided. The power traces are measured at various
temperatures by which dependency of Logic style on temperature i.e., thermal Stability is also
studied
 “PEARL: Performance Analysis of Ultra Low Power Adiabatic Logic style against
DPA Attack”, at IEEE ICEEOT’ 2016, Chennai, India.
Abstract—Reversible logic is one of the most vital issues at present time and it has major
role in cryptographic applications. Security of cryptographic devices like smart cards has
come under threat from powerful side channel attacks like Differential Power Analysis
 (DPA) attacks. DPA uses power dissipation information leaked from the secure IC to
retrieve the secret key stored in it. To address this problem, we have proposed a novel
gate which introduces the reversible two-input logical operations with minimum power
dissipation for each logical operation. Therefore, the proposed gate mitigates the DPA
attacks since the proposed logic dissipates very low power compared to DPA ressistant
logic styles such as Sense Amplifier Based Logic (SABL), Wave Dynamic Differential Logic
(WDDL), Masked Dual-rail Precharge logic style (MDPL) and Delay based Dualrail
Precharge Logic (DDPL) which is thereby useful in the design of secure integrated
circuits. The experimental results have been carried out using Cadence c
design tools in 180nm technology. The obtained simulation results of the proposed gate
are appreciably better in terms of power dissipation as well as security when compared
to the designs in literature.
 “A DPA Resistant Low Power Adiabatic Logic With a Discharge and Clock Signal” -
Communicated to ISOCC 2019
Abstract—As the technology is shirking the major treat to the VLSI chips fabricated
is Side Channel Attacks(SCA) and the popular SCA attacks are Differential Power
Analysis(DPA). In cryptographic systems such are Smart cards, RFID tags, military
applications and E-commerce applications cryptography plays a vital role. The DPA
attacks are mainly caused due to the processing power in the chip. Cryptography
plays a vital role in acquiring the software security of data and the latest
cryptographic algorithm is Advance encryption Standard(AES). In this paper a Low
power Adiabatic logic gates such as Buffer, AND and XOR are proposed and a Galois
Field multiplier GF(16) is implemented which reduces the energy consumption by
64% AND 75% compae to SPGAL and PFSAL respectivitely. The proposal is
implemented and results are verified in Cadence Virtuoso 45nm technology and the
power and current traces are observed to be constant.
Main Base Papers:
[1] Massimo Alioto, Simone Bongiovanni, et al., “Effectiveness of leakage power analysis
attacks under process variations”, IEEE Trans. Circuits and Systems,2014.
[2] Bhuvana B P, Kanchana Bhaaskaran V S “Positive Feedback Symmetric Adiabatic Logic
against Differential Power Attack” 2018 31th International Conference on VLSI Design and
2018 17th International Conference on Embedded Systems

I want the extension of these two papers and finally implementing a 128bit AES algorithm
with the improved gates.

If cadence tool is not available atleast circuits executed in tanner tool preferably 45nm
technology node.

Main Text Book:

[1] Power Analysis Attacks Revealing the Secrets of Smart Card