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Semiconductor Memories: Digital Integrated Circuits © Prentice Hall 1995 Memory
Semiconductor Memories: Digital Integrated Circuits © Prentice Hall 1995 Memory
MEMORIES
• Memory Classification
• Memory Architectures
• Periphery
• Reliability
DRAM LIFO
Shift Register
CAM
S0 S0
Word 0 Word 0
S1
Word 1 A0 Word 1
S2 Storage Storage
Word 2 Word 2
N Words
Cell A1 Cell
Decoder
A K-1
SN-2
Word N-2 Word N-2
SN_1
Word N-1 Word N-1
Input-Output Input-Output
(M bits) (M bits)
AK
Row Decoder
AL-1
K
M.2
A0
Column Decoder Selects appropriate
A K-1 word
Input-Output
(M bits)
Row
Address
Column
Address
Block
Address
I/O
Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
Read Cycle
READ
WRITE
Write Access
Data Valid
DATA
Data Written
Address
Row Address Colum n Address
Bus
RAS Address
Address
Bus
Address transition
CAS initiates memory operation
RAS-CAS timing
WL[0]
GND
WL[1]
WL[2]
GND
WL[3]
WL[0]
GND (diffusion)
WL[1]
Polysilicon
Basic cell
10 λ x 7 λ Metal1
WL[2] 2λ
WL[3]
WL[0]
GND (diffusion)
Basic Cell
8.5 λ x 7 λ
Metal1 over diffusion
WL[1]
Polysilicon
WL[2]
WL[3]
Pull-up devices
WL[0]
WL[1]
WL[2]
WL[3]
Polysilicon
Basic cell
5 λx 6 λ
Threshold
lowering
implant
VDD
BL
rword
Model for NOR ROM WL
Cbit
cword
BL
CL
rbit
Model for NAND ROM
rword cbit
WL
cword
Metal bypass
WL[0]
GND
WL[1]
WL[2]
GND
WL[3]
tox G
tox
S
+ p +
n n
Substrate
20 V 0V 5V
20 V 0V 5V
10 V→ 5 V − 5V − 2.5 V
S D S D S D
20-30 nm − 10 V VGD
10 V
n+ Substrate n+
p
10 nm
WL
VDD
Control gate
Floating gate
n+ source n+ drain
programming
p-substrate
Flash EPROM
Courtesy Intel
Digital Integrated Circuits Memory © Prentice Hall 1995
Characteristics of State-of-the-art
NVM
• STATIC (SRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
• DYNAMIC (DRAM)
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended
Digital Integrated Circuits Memory © Prentice Hall 1995
6-transistor CMOS SRAM Cell
WL
VDD
M2 M4
Q
Q M6
M5
M1 M3
BL BL
VDD
M4
Q=0 M6
M5 Q=1
M1
VDD
BL = 1 BL = 0
k n M5 V VDD 2 V DD V 2
, -----------
-------------- DD
– VTn ----------- = k n ,M1 ( VDD – VTn )----------- – -----------
DD
2 2 2 2 8 (W/L)n,M5 ≥ 10 (W/L)n,M1
VDD
BL M4
BL
Q=0 M6
M5 Q=1
M1 V DD
VDD VDD
Cbit C bit
VDD
M2 M4
Q Q
M1 M3
GND
M5 M6 WL
BL BL
VDD
RL RL
Q Q
M3 M4
BL M1 M2 BL
WWL WWL
RWL
RWL
X VDD -VT
X M3
M2
M1 VDD
BL1
CS
RWL
M3
M2
WWL
M1
M1 X
CS GND VDD − VT
VDD
BL
VDD /2 VDD /2
CBL sensing
(b) Layout
Cell Plate Si
Si Substrate
2nd Field Oxide
•Decoders
•Sense Amplifiers
•Input/Output Buffers
•Control / Timing Circuitry
Digital Integrated Circuits Memory © Prentice Hall 1995
Row Decoders
Collection of 2M complex logic gates
Organized in regular and dense fashion
(N)AND Decoder
NOR Decoder
WL3
WL3 VDD
WL2
WL2 VDD
WL1 WL1
VDD
WL0 WL0
V DD φ A0 A0 A1 A1 A0 A0 A1 A1 φ
WL 1
WL 0
A1 A 0 A0 A1 A3 A2 A2 A3
BL 0 BL1 BL 2 BL3
S0
A0 2 input NOR decoder
S1
S2
A1
S3
D
Advantage: speed (t pd does not add to overall memory access time)
only 1 extra transistor in signal path
Disadvantage: large transistor count
Digital Integrated Circuits Memory © Prentice Hall 1995
4-to-1 tree based column decoder
BL0 BL 1 BL2 BL 3
A0
A0
A1
A1
D
Number of devices drastically reduced
Delay increases quadratically with # of sections; prohibitive for large decoders
Solutions: buffers
progressive sizing
combination of tree and pass transistor approaches
WL0 WL 1 WL 2
φ φ φ φ φ φ
...
R φ φ R φ φ R φ φ
VDD
large small
small
transition s.a.
input output
x M1 M2 x x x
BL BL
EQ
SE M5 SE
WLi
(b) Doubled-ended Current Mirror Amplifier
VDD
SRAM cell i
y y
Diff.
x Sense x x x
Amp
y y
D D SE
EQ
BL BL
VDD
SE
SE
WL
BL
x Diff. x
+
S.A. _ Vref
cell
y y
EQ
R L1 L0 R0 R1 L
VDD
SE
BLL BLR
... ...
CS CS CS SE CS CS CS
dummy dummy
cell cell
4.0
V (Volt)
BL
2.0 BL
5.0
0.00 4.0 WL
1 2 3 4 5
V (Volt)
t (nsec) 3.0 SE
(a) reading a zero
2.0 EQ
6.0 1.0
0.00 1 2 3 4 5
4.0
V (Volt)
2.0 BL
0.00 1 2 3 4 5
t (nsec)
(b) reading a one
Vcasc
WLC
WL
DELAY
A0 td
ATD ATD
DELAY
A1 td
...
DELAY
AN-1 td
EQ
BL CBL x y
... Sense
C C C C C
C EQ Amplifier
BL CBL x y
CWBL
BL’
Ccross
BL
SA
BL
BL"
BL’
Ccross
BL
SA
BL
BL"
α-particle
WL
VDD
BL
SiO2
n+
Row
Address
Redundant
rows
Fuse
:
Bank
Redundant
columns
Row Decoder
Memory
Array
Product Terms
x0x1
AND x2 OR
PLANE PLANE
f0 f1
x0 x1 x2
VDD
GND GND GND GND
GND
GND
GND
VDD f0 f1
x0 x0 x1 x1 x2 x2
AND-PLANE OR-PLANE
GND VDD
φOR
φOR
φAND
V DD f0 f1 GND
x0 x0 x1 x1 x2 x2
AND-PLANE OR-PLANE
φ φ φAND
φAND
φAND φOR
Dummy AND Row
φOR
x0 x0 x1 x1 x2 x2 f0 f1
Pull-up devices Pull-up devices
Digital Integrated Circuits Memory © Prentice Hall 1995
PLA versus ROM
IDENTICAL TO ROM!
Main difference
ROM: fully populated
PLA: one element per minterm