Design with FinFETs:

Design Rules, Patterns, and Variability

(Special Session)

Rasit O. Topaloglu
IBM
Semiconductor R&D Center, Hopewell Junction, NY
e-mail: rasit@us.ibm.com

Abstract—FinFETs have proven to be the device of choice G

for the next few technology generations. Consequently, design

C
rules and limitations related to FinFETs need to be carefully
understood. We present restricted and gridded design rules
related to FinFETs. We also present results which indicate that
a complete front-end-of-line (FEOL) and middle-of-line (MOL)
of a memory with controllers can be designed from a fixed set
of patterns. We also indicate sources of variations in FinFETs. (a) (b) (c)

Fig. 1. (a) Simplified layout of a traditional device (b) Layout of a FinFET

I. I NTRODUCTION
Technological demand and industry roadmaps push semi-
conductor engineers towards a rapid progress in device sizes.
With device sizes reaching 10nm, two aspects have shown to
be of research need to further the device performance increase:
a) materials and b) structure.
Innovation through material engineering is quite valuable.
However, it has significant challenges. When a new material is
introduced into a foundry, optimization of processing methods
and knobs may take several years. Frequently, exotic individual
devices or very small circuits as presented in leading-edge
device conferences such as IEDM are not directly suitable
for large-scale manufacturing where billions of such devices
need to be placed on a die and that thousands of wafers each
of which contains tens to hundreds of such dies need to be
manufactured with high yield. This is one reason why silicon-
based devices with improvements of germanium, carbon, and
other materials have stayed as the process of record. However,
approaching 10nm requires the industry to come up with
a radical change. This is essentially a structural change in
devices while still staying with silicon and materials that
provide additional boost to silicon’s mobility.
Obviously, processing and patterning changes are not the
only differences we need to pay attention to. Design tools are
essential to develop chips in short amounts of time. Hence,
a new change should avoid bringing a drastic alteration to
design tools. While this task becomes arduous and certain
changes need to be implemented, we try to keep such changes
minimal. With the structural change to FinFET-based design,
many of the traditional design tool features are kept. However,
new features may be needed in tools such as RC extractors as
well as place and route tools.
In this paper, we outline key differences of FinFET tech-
nologies over previous generations. We go over key design rule
changes. We also discuss what types of patterns these rules
device (c) How the fins could look like on wafer.
enable. We present results from hardware that indicate that a
fixed set of small layout patterns may indeed be sufficient to
design and manufacture circuits; similar to a fixed set of rules
being “almost” sufficient for the same purpose. We furthermore
outline sources of variations for FinFETs.
Fig. 1(a) shows how a device would be drawn in a previous
technology. A diffusion layer would be overlapped by a gate
(G). The diffusion layer would have contacts (C) that make
connections to metal layers. Fig. 1(b) shows how the device
would be drawn in a FinFET technology. Fig. 1(c) shows how
the device and in particular the fins could actually look like on
wafer. This shows that although FinFETs are structurally quite
different, they are drawn almost like the traditional devices so
that the design tools are not affected.
II. D ESIGN RULES
Uniform Pitch. Designs with varying pitches are difficult
to manufacture due to lithographic limitations. Hence there
have been lithographic requirements to limit the pitch since
the last few technology nodes. Given that we have to utilize
methodologies such as double patterning, it should not come
as a surprise that pitch values are restricted to fixed discrete
values. While large jumps in the pitch such as providing a 2x
pitch with respect to the nominal may be considered, even
such large jumps may be problematic in terms of defects.
In summary with the current state of lithography, fixed and
uniform pitch is almost a must.
Uniform Width. Width distribution is to a certain extent not
affected by lithography if it is kept uniform. While pitch is
defined mainly by lithographic constraints at the current state
of the technology, width is controlled by etch, electrical, and
reliability constraints. However, this is only true for uniform

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width. If width is not uniform, then lithographic effects start
to dominate. Hence whenever it is possible, the width should
be kept uniform.
Unidirectional Orientation. Orientation of layers have be-
come unidirectional for certain layers already. Bi-directional
layers have started to require double patterning to pattern the
two orthogonal sets of features separately. Such orthogonal
double patterning also is the solution against corner rounding
issues.
No Staggering. Staggering, similar to the pitch variations,
can results in both lithographic issues as well as sub-optimal
corner rounding. One reason for this is that the stagger would
result in two different pitch values around the stagger point.
Unlike bidirectional layers, if utilized, staggering would not
use double patterning so that mask costs are kept low.
Figure 2 illustrates a new concern. In the past technologies,
we have been mainly worried about staggers within a polygon.
However, staggering in large arrays are also potential issues
in current state of the technology and should be avoided if
possible.
Fig. 2. Not only staggering within an individual polygon is not permitted,
but staggering within an array of fixed width polygons may also be restricted.
About MOL. Middle-of-line usage has entered the semicon-
ductor technology domain before the FinFETs. However, it is
useful to understand about them to appreciate some of the rules
we mention.
G are bounded by constraints from another layer, features on the
C
MOL V M
M
(a) (b)
Fig. 3. Middle-of-line (MOL) is a collection of one or more interconnecting
layers that connect the devices to back-end-of-line (BEOL) interconnects (M).
Unlike contacts in previous technologies (a), they enable routing to nearby
devices directly (b).
Middle-of-line has been introduced essentially because of
electrical resistance concerns between various connected de-
vices resulting in significant performance loss. Hence, instead
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of connecting the diffusion layer to interconnect layer using
contacts, routing for the cells and devices can be mostly
handled at the MOL layer directly. Obviously, this requires
several process and material changes. However, it is possible
with MOL-enabled devices to route devices with each other
at much lower resistances. Figure 3 illustrates how MOL is
utilized. Via layer (V) may be utilized to make connection
between the MOL and BEOL layers.
Cut Layers. Another major change in the semiconductor
manufacturing is the utilization of cut masks. They are used
also with certain lithographic processes such as self-aligned-
double-patterning (SADP) as shown in [1]. Cut masks usually
have larger features and are less costly to manufacture. The
main benefit of them is to help structure the final printed
features by removing unwanted features that are printed by
a prior mask. So unlike the past technologies where only final
structures are to be printed, currently a wide area of uniform
structures are printed first and from these structures what needs
to be kept is defined through a cut mask. This is illustrated in
Figure 4.
Fig. 4. Cutmasks are used to remove portions of an otherwise regular arrays
of polygons. A cutmask is shown with dashed lines.
Such Boolean operations with masks are usually hidden
from the designers though and the requirements are embedded
into the design rules. The purpose is to ensure that the designer
is provided with a simple interface to the printed features.
Gridded Design. Once certain layers have been confined to
fixed pitches and widths, as several layers that define a device
new layers can be restricted to align with certain grids. These
restrictions may either be based on alignment to edges or center
lines. Hence unlike prior technologies, designers would find
several grid-based restrictions as to where they can place a
polygon. Restrictions to MOL is shown in Figure 5.
Such restrictions indeed can be a benefit to EDA tools
as instead of covering a continuous design range, discrete
placements need to be sufficient. This lends itself to faster
EDA algorithms as these placements can be defined in terms
of efficient data structures.
Double Coloring. Needless to say, double coloring in the pitch
splitting sense is required for FinFETs given the current state
of lithography. Any layer that can avoid double patterning
should avoid it. However for layers such as MOL, this does
not theoretically seem possible. Readers may refer to [2] for
further discussion on double patterning impact on design.

Fig. 5. Grids restrict the placement of polygons. A vertical grid on MOL
shows how placements in horizontal direction can be confined.
Lithographic Checks. Lithographic checks and litho-friendly
design has been crucial to manufacturability since 90nm tech-
nology. One may think that with such restrictions on pitch,
width, staggers, and grids, lithographic checks would be a
historical practice. In practice, lithographic checks are still
very important. Certainly corner rounding may not be an issue
anymore if all these restrictions are implemented, however,
where there are staggers in the convex hull of an array of
patterns, there may be problems around such staggered regions.
Furthermore, co-optimization of OPC and SRAFs may not be
easy and may require lithographic checks to ensure that line
ends satisfy process assumptions and none of the SRAFs ends
up printed on wafer.
Several of the aforementioned rules have been developed
using a design-technology co-optimization (DTCO) process
where designers are involved actively in making design rule
decisions. Readers may refer to [3] for further details on the
DTCO process.
III. D ESIGN PATTERNS
As technology advances, being able to impose design rules
are also getting more difficult due to several dependences
across multiple layers that are required to form a device.
Hence one way to cope with the rule difficulty has been to
introduce pattern-based design methods. Such methods can
either be restrictive or design-friendly. In the latter, certain
patterns are provided to the designers for them to freely use
in their designs. These patterns would otherwise be ruled out
by the design rules. [4] summarizes such ideas and [5] has
investigated the applications to routing.
A design pattern, perhaps also called a snippet, is a small
window of layout. It may contain one or more layers. The
size is not restricted usually however a window size of 0.1um
to 0.1um to 2um to 2um could be reasonable dimensions in
technologies close to 10nm. In the past, describing a design
with patterns alone would not be feasible as the design rule
space would cover almost an infinite number of possibilities.
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With the aforementioned restrictions, we have been able to
confine these patterns into a fixed size library.
We have found that to manufacture a completely working
memory of 5.995 by 1.244mm size in 14nm technology
with controllers can be achieved with 6725 FEOL and MOL
combined unique patterns, or 1991 FEOL-only patterns of 120
by 120nm patterns. These patterns are allowed to overlap with
each other, hence this number is not the minimum that is
possible.
IV. S OURCES OF VARIABILITY
While we are still characterizing the various variability
sources, it may be useful to summarize the sources of vari-
ability we expect from FinFETs:
i- Epitaxy
ii- Overlay
iii- Fin height variations
iv- Width variations across double-patterned layers
v- Fin to fin variations
vi- Pitch-dependent width variation
vii- MOL resistance variations
due to overlap differences or etch micro-loading effects
Certain variations to devices is evident from layout and
may be estimated by the EDA tool. For example, if an MOL
layer is drawn longer, its effect can be extracted by an RC
extractor. However for other effects such as width variations
across double-patterned layers, the assumption would be that
the two widths should print equal and hence such variations
would not by default be accounted for.
V. C ONCLUSIONS
We have summarized key design changes in FinFETs. Most
of these changes do have EDA tool implications. We have
presented results that indicate that a fixed set of design patterns
are sufficient to design circuits with FinFETs. We have also
outlined sources of variations we expect from FinFETs.
ACKNOWLEDGMENT
The author thanks Phil Strenski and Jim Culp on discus-
sions related to the design patterns.
R EFERENCES
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Design, 2011, pp. 1-4.
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