EXPERIMENT 6

ANALYSIS OF THE DESIGN PROCEDURE

The first part of this experiment was to design an adder-subtractor combination. Recycling the
combinatorial circuit from the full-adder, it was incorporated into the design by creating a schematic
symbol for the full-adder and calling it to the current project. From the illustration of the adder-
subtractor combination, an asynchronous input together with a select variable passes through an XOR
gate into four adder FSMs, with an independent sum port per adder, and a carry that passes overflow
into the next FSM until the carry may be considered as the result’s sign convention. The second part
illustrates a schematic to design an ALU. We used the design of the adder FSM from the previous part.
The three extenders, namely: logic, arithmetic, and carry extenders had their Boolean equation derived
from the given truth tables. These extenders serve as the first stage of the ALU, being connected by a
single input that would eventually be processed by the four adder FSMs.

DATA AND TESTING OF RESULTS

This two-part experiment had its circuit diagram related to each other, along with concepts from
previous experiments like the construction of an adder finite-state machine. The four adder FSMs that
were used for the construction of the adder-subtractor combination was incorporated on to the second
part’s design for an ALU schematic. We noticed that before the second stage was in play, the
information was first processed by three extenders on the first stage, which was the logic, arithmetic,
and carry extender. Since each of these extenders had a truth table that represents its function, we used
the knowledge on karnaugh mapping to simplify and obtain its corresponding Boolean equation. To run
the simulation properly, the Boolean equation for each extender were integrated into its subsequent
schematic symbol, using logic gates necessary for the equation. A sample test bench was made to verify
whether the derived Boolean equations from the extenders were correct, and that they were properly
processed by the four adder FSM respectively.

CONCLUSION

The arithmetic-logic unit, or ALU, is a complex digital circuit integrated into a computer’s central
processing unit. Its primary function is to perform both bitwise and mathematical operations on binary
numbers. Some of the operations demonstrated in this experiment include addition, subtraction, and
the logical AND and OR. However, the other two fundamental operations, multiplication and division,
were excluded. In this experiment, the integration of the adder FSM’s from previous experiments were
necessary, along with the concept on the creation of a schematic symbol using the constructed
combinatorial circuit. For the adder-subtractor in part 1, the switch between the addition and
subtraction was fairly simple; an input of either logic high or low would set the combination to either
subtraction or addition, respectively. Notice that the sign convention was considered. For the second
part, the 4-bit ALU was constructed using adders and three extenders: the logical, arithmetic, and carry
extenders, with each extender manipulating its defined operations.