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use ieee.std_logic_1164.all;
use arithmetic.std_logic_arith.all;
entity div_seq is
port(divid: in std_logic_vector(28 downto 0);divis: in std_logic_vector(20 downto
0);
q: buffer std_logic_vector(7 downto 0);reset1,reset2,reset,clk:in std_logic;
fin_div:out std_logic);
end div_seq;
is
variable ddp:std_logic_vector(22 downto 0);
begin
ddp(0):=divd(6-j);
--test du carry
if sp(23)='0' then
label4: for i in 22 downto 1 loop
ddp(i):=dp(i-1);
end loop label4;
else
label5: for i in 1 to 22 loop
ddp(i):=sp(i-1);
end loop label5;
end if;
return ddp;
end ddp_val;
--programme principal
signal ddp,dsp: std_logic_vector(22 downto 0);
signal sp: std_logic_vector(23 downto 0);
signal divd: std_logic_vector(6 downto 0);
signal l,k: std_logic;
signal j: integer;
begin
process(clk)
begin
if (clk'event and (clk = '1')) then
--etape d'initialisation
if reset='1' then
l<='0';
k<='0';
j<=0;
fin_div<='0';
q<="00000000";
else
if ((reset1='1') and (k='0')) then
label3: for i in 20 downto 0 loop
dsp(i)<=not(divis(i));
end loop label3;
dsp(21)<='1';
dsp(22)<='1';
k<='1';
j<=0;
fin_div<='0';
end if;
if ((reset2 = '1') and (l='0')) then
label1: for i in 20 downto 0 loop
ddp(i)<=divid(i+7);
end loop label1;
ddp(21)<=divid(28);
ddp(22)<='0';
q <= "00000000";
fin_div<='0';
j<=0;
l<='1';
label2: for i in 0 to 6 loop
divd(i)<=divid(i);
end loop label2;
end if;
if ((l='1') and (k='1')) then
if j<=6 then
ddp<=ddp_val(divd, dsp, ddp, sp,j);
q <= q_val(q,sp(23));
j<=j+1;
fin_div<='0';
else
if j=7 then
q <= q_val(q,sp(23));
j<=j+1;
--valeur finale du quotient coincide avec fin_div
else
fin_div<='1';
k<='0';
l<='0';
end if;
end if;
end if;
end if;
end if;
end process;
sp<=soustraction(ddp,dsp);
end div_seq_arch;