#exec rm -rf db/dtmf_mw

#exec mkdir -p rpts/sanity_checks

create_mw_lib -technology
/tools/libraries/28nm/SAED32_EDK/tech/milkyway/saed32nm_1p9m_mw.tf \
-bus_naming_style {[%d]} \
-mw_reference_library { \
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_rvt/milkyway/saed32nm_rvt_1p9m \
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_lvt/milkyway/saed32nm_lvt_1p9m \
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_hvt/milkyway/saed32nm_hvt_1p9m \
/tools/libraries/28nm/SAED32_EDK/lib/sram_lp/milkyway/saed32sram_lp \
/tools/libraries/28nm/SAED32_EDK/lib/pll/milkyway/SAED32_PLL_FR/ \
/tools/libraries/28nm/SAED32_EDK/lib/sram/milkyway/SRAM32NM} -open
mwdb/dtmf_mw_lib1

## Attaching the TLU+ Files ##

set_tlu_plus_files -max_tluplus
/tools/libraries/28nm/SAED32_EDK/tech/star_rcxt/saed32nm_1p9m_Cmax.tluplus \
-min_tluplus
/tools/libraries/28nm/SAED32_EDK/tech/star_rcxt/saed32nm_1p9m_Cmin.tluplus \
-tech2itf_map
/tools/libraries/28nm/SAED32_EDK/tech/star_rcxt/saed32nm_tf_itf_tluplus.map

## Importing the Verilog Netlist ##

import_designs -format verilog -cel dtmf_recvr_core -top dtmf_recvr_core
inputs/dtmf_recvr_core.vg
## Setting the Current Design ##
set current_design dtmf_recvr_core
_
## Linking the Physical Libraries ##
link_physical_library1

## Linking the Timing Libraries ##1

link

## Reading the SDC ##

read_sdc inputs/dtmf_recvr_core.sdc

#create path groups in your design

source scripts/create_path_groups.tcl

## PG - Global Net Connection ## need to read once floorplan is done

#source scripts/derive_pg_connection.tcl

## Saving the Design ##

save_mw_cel -as dtmf_recvr_core_import_design
save_mw_cel