Loading 28nm SAED32 Design Libraries

Loading db file '/pd_libs/saed32hvt_ss0p95v125c.
db'
Loading db file '/pd_libs/saed32hvt_ff1p16v25c.db'
Loading db file '/pd_libs/saed32rvt_ss0p95v125c.db'
Loading db file '/pd_libs/saed32rvt_ff1p16v25c.db'
Loading db file '/pd_libs/saed32lvt_ss0p95v125c.db'
Loading db file '/pd_libs/saed32lvt_ff1p16v25c.db'
Loading db file
'/tools/libraries/28nm/SAED32_EDK/lib/sram/db_nldm/saed32sram_ss0p95v125c.db'
Loading db file
'/tools/libraries/28nm/SAED32_EDK/lib/sram/db_nldm/saed32sram_ff1p16v25c.db'
Loading db file
'/tools/libraries/28nm/SAED32_EDK/lib/pll/db_nldm/saed32pll_ss0p95v125c_2p25v.db'
Loading db file
'/tools/libraries/28nm/SAED32_EDK/lib/pll/db_nldm/saed32pll_ff1p16v25c_2p75v.db'
icc_shell> create_mw_lib -technology
/tools/libraries/28nm/SAED32_EDK/tech/milkyway/saed32nm_1p9m_mw.tf -bus_naming_style
{[%d]} -mw_reference_library {
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_rvt/milkyway/saed32nm_rvt_1p9m
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_lvt/milkyway/saed32nm_lvt_1p9m
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_hvt/milkyway/saed32nm_hvt_1p9m
/tools/libraries/28nm/SAED32_EDK/lib/sram_lp/milkyway/saed32sram_lp
/tools/libraries/28nm/SAED32_EDK/lib/pll/milkyway/SAED32_PLL_FR/
/tools/libraries/28nm/SAED32_EDK/lib/sram/milkyway/SRAM32NM} -open mwdb/dtmf_mw_lib
Error: Library 'mwdb/dtmf_mw_lib' already exists. (MWUI-004)
0
icc_shell> create_mw_lib -technology
/tools/libraries/28nm/SAED32_EDK/tech/milkyway/saed32nm_1p9m_mw.tf -bus_naming_style
{[%d]} -mw_reference_library {
/tools/libraries/28nm/SAED32_EDK/lib/pll/milkyway/SAED32_PLL_FR/
/tools/libraries/28nm/SAED32_EDK/lib/sram/milkyway/SRAM32NM} -open
mwdb/dtmf_mw_lib1
Start to load technology file
/tools/libraries/28nm/SAED32_EDK/tech/milkyway/saed32nm_1p9m_mw.tf.
Warning: Layer 'M1' has a pitch 0.152 that does not match the recommended wire-to-via pitch 0.13
or 0.105. (TFCHK-049)
Warning: Layer 'M2' has a pitch 0.152 that does not match the recommended wire-to-via pitch
0.139. (TFCHK-049)
0.139. (TFCHK-049)
0.139. (TFCHK-049)
0.139. (TFCHK-049)
0.139. (TFCHK-049)
0.139. (TFCHK-049)
0.179 or 0.164. (TFCHK-049)
Warning: Layer 'M9' has a pitch 2.432 that does not match the recommended wire-to-via pitch 1.74.
(TFCHK-049)
Warning: Layer 'MRDL' has a pitch 4.864 that does not match the recommended wire-to-via pitch
4.5. (TFCHK-049)
Warning: Layer 'MRDL' has a pitch 4.864 that does not match the doubled pitch 2.432 or tripled
pitch 3.648. (TFCHK-050)
Warning: CapModel sections are missing. Capacitance models should be loaded with a TLU+ file
later. (TFCHK-084)
Technology file /tools/libraries/28nm/SAED32_EDK/tech/milkyway/saed32nm_1p9m_mw.tf has
been loaded successfully.
{dtmf_mw_lib1}
icc_shell> set_tlu_plus_files -max_tluplus
/tools/libraries/28nm/SAED32_EDK/tech/star_rcxt/saed32nm_1p9m_Cmax.tluplus -min_tluplus
/tools/libraries/28nm/SAED32_EDK/tech/star_rcxt/saed32nm_1p9m_Cmin.tluplus
-tech2itf_map /tools/libraries/28nm/SAED32_EDK/tech/star_rcxt/saed32nm_tf_itf_tluplus.map
1
icc_shell>
icc_shell> import_designs -format verilog -cel dtmf_recvr_core -top dtmf_recvr_core
inputs/dtmf_recvr_core.vg
Warning: Unit conflict found: Milkyway technology file resistance unit is kOhm; main library
resistance unit is MOhm. (IFS-007)
Warning: Unit conflict found: Milkyway technology file power unit is pW; main library power unit
is uW. (IFS-007)
Type of creating bus for undefined cells : 0
Warning: /tools/libraries/28nm/SAED32_EDK/lib/stdcell_rvt/milkyway/saed32nm_rvt_1p9m: bus
naming style _<%d> is not consistent with main lib. (MWNL-111)
***** Verilog HDL translation! *****
***** Start Pass 1 *****

Warning: Lineno 9442, change net type from TRI to Wire. (MWNL-117)
***** Pass 1 Complete *****

Elapsed = 0:00:00, CPU = 0:00:00
***** Verilog HDL translation! *****
***** Start Pass 2 *****

***** Pass 2 Complete *****
***** Verilog HDL translation completed! *****

Elapsed = 0:00:00, CPU = 0:00:00
Hierarchy Preservation is turned ON
The quick-attach skip-search mode has been turned on.
Start axu naming escaping style change ...
INFO: net in module m16x16_DW01_add_0 renamed from \A[0] to A[0]1 because of name conflict
INFO: net in module m16x16_DW01_add_0 renamed from \A[10] to A[10]1 because of name
conflict
conflict
conflict
conflict
conflict
INFO: net in module tdsp_core_glue renamed from \port_addrs_in[0] to port_addrs_in[0]1 because
of name conflict
INFO: net in module tdsp_core_glue renamed from \data_out[15] to data_out[15]1 because of name
conflict
INFO: net in module tdsp_core_glue renamed from \ir[10] to ir[10]1 because of name conflict
conflict
conflict
conflict
conflict
conflict
conflict
conflict
conflict
conflict
conflict
conflict
conflict
conflict
conflict
conflict
INFO: net in module tdsp_ds_cs renamed from \address[0] to address[0]1 because of name conflict
End axu naming escaping style change, status is 1
Checking single pin net for cell 'dtmf_recvr_core.CEL' now...
Total number of cell instances: 5658
Total number of nets: 6323
Total number of ports: 67 (include 3 PG ports)
Total number of hierarchical cell instances: 75
The quick-attach skip-search mode has been turned off.

INFO: total find 0 pg nets connected with tie net.
Elapsed = 0:00:01, CPU = 0:00:00
Information: Read verilog completed successfully.
1
icc_shell> set current_design dtmf_recvr_core
Loading db file '/tools/synopsys/installers/icc/libraries/syn/gtech.db'
Loading db file '/tools/synopsys/installers/icc/libraries/syn/standard.sldb'
Information: linking reference library :
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_rvt/milkyway/saed32nm_rvt_1p9m. (PSYN-878)
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_lvt/milkyway/saed32nm_lvt_1p9m. (PSYN-878)
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_hvt/milkyway/saed32nm_hvt_1p9m. (PSYN-878)
/tools/libraries/28nm/SAED32_EDK/lib/sram_lp/milkyway/saed32sram_lp. (PSYN-878)
/tools/libraries/28nm/SAED32_EDK/lib/pll/milkyway/SAED32_PLL_FR. (PSYN-878)
/tools/libraries/28nm/SAED32_EDK/lib/sram/milkyway/SRAM32NM. (PSYN-878)
Linking design 'dtmf_recvr_core'

Using the following designs and libraries:
--------------------------------------------------------------------------
* (75 designs) dtmf_recvr_core.CEL, etc
saed32lvt_ss0p95v125c (library) /pd_libs/saed32lvt_ss0p95v125c.db
saed32rvt_ss0p95v125c (library) /pd_libs/saed32rvt_ss0p95v125c.db
saed32pll_ss0p95v125c_2p25v (library)
/tools/libraries/28nm/SAED32_EDK/lib/pll/db_nldm/saed32pll_ss0p95v125c_2p25v.db
saed32sram_ss0p95v125c (library)
/tools/libraries/28nm/SAED32_EDK/lib/sram/db_nldm/saed32sram_ss0p95v125c.db
saed32hvt_ss0p95v125c (library) /pd_libs/saed32hvt_ss0p95v125c.db
Warning: Reference PLL contains internal pins with clock attribute. (TIM-103)
dtmf_recvr_core
icc_shell> link_physical_library1
Error: unknown command 'link_physical_library1' (CMD-005)
icc_shell> link_physical_library
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_rvt/milkyway/saed32nm_rvt_1p9m. (PSYN-878)
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_lvt/milkyway/saed32nm_lvt_1p9m. (PSYN-878)
/tools/libraries/28nm/SAED32_EDK/lib/stdcell_hvt/milkyway/saed32nm_hvt_1p9m. (PSYN-878)
/tools/libraries/28nm/SAED32_EDK/lib/sram_lp/milkyway/saed32sram_lp. (PSYN-878)
/tools/libraries/28nm/SAED32_EDK/lib/pll/milkyway/SAED32_PLL_FR. (PSYN-878)
/tools/libraries/28nm/SAED32_EDK/lib/sram/milkyway/SRAM32NM. (PSYN-878)
1
icc_shell> link
Linking design 'dtmf_recvr_core'
Using the following designs and libraries:
--------------------------------------------------------------------------
* (75 designs) dtmf_recvr_core.CEL, etc
saed32lvt_ss0p95v125c (library) /pd_libs/saed32lvt_ss0p95v125c.db
saed32rvt_ss0p95v125c (library) /pd_libs/saed32rvt_ss0p95v125c.db
saed32pll_ss0p95v125c_2p25v (library)
saed32sram_ss0p95v125c (library)
saed32hvt_ss0p95v125c (library) /pd_libs/saed32hvt_ss0p95v125c.db
1
icc_shell> read_sdc inputs/dtmf_recvr_core.sdc
Info: hierarchy_separator was changed to /
Reading SDC version 2.0...

Current design is 'dtmf_recvr_core'.
Current design is 'dtmf_recvr_core'.
Info: hierarchy_separator was changed to /
1
icc_shell> sh scripts/create_path_groups.tcl
Error: scripts/create_path_groups.tcl: line 2: group_path: command not found
scripts/create_path_groups.tcl: line 3: group_path: command not found
Use error_info for more info. (CMD-013)
icc_shell> source scripts/create_path_groups.tcl
Floorplan loading succeeded.
Information: Updating graph... (UID-83)
Warning: No controlling value could be found for the clock gating cell 'TDSP_DS_CS_INST/U10'
for the clock pin 'A2'. (TIM-128)
Warning: Gated clock latch is not created for cell 'TEST_CONTROL_INST/U6'on pin 'A2' in
design 'dtmf_recvr_core'. (TIM-141)
Warning: No controlling value could be found for the clock gating cell
'TEST_CONTROL_INST/U6' for the clock pin 'A1'. (TIM-128)
Warning: Gated clock latch is not created for cell 'SPI_INST/present_state_reg[1]'on pin 'D' in
Warning: Clock port 'p_clk' is assigned input delay relative to clock 'refclk'. (TIM-111)
Warning: Clock port 'p_clk' is assigned input delay relative to clock 'refclk'. (TIM-111)
Warning: Clock port 'scan_clk' is assigned input delay relative to clock 'refclk'. (TIM-111)
Warning: Clock port 'scan_clk' is assigned input delay relative to clock 'refclk'. (TIM-111)
1
icc_shell> sh xterm &
966
icc_shell> sh gvim scripts/create_path_groups.tcl &
1817
icc_shell> save_mw_lib
Error: unknown command 'save_mw_lib' (CMD-005)
icc_shell> save_mw_cel
Information: Performing CEL netlist consistency check. (MWDC-118)
Information: CEL consistency check PASSED. (MWDC-119)
Information: Saved design named dtmf_recvr_core. (UIG-5)
1
icc_shell> save_mw_lib
Error: unknown command 'save_mw_lib' (CMD-005)
icc_shell> check_library
#BEGIN_XCHECK_LIBRARY
Logic Library #1:

Library name saed32hvt_ss0p95v125c
File name /pd_libs/saed32hvt_ss0p95v125c.db
Library type pg_pin based db
Library Version 1.0000000
Tool Created F-2011.09-SP1
Data Created [2010 APRIL 28]
Time unit 1ns
Capacitance unit 1ff
Leakage power unit 1pW
Current unit 1uA
check_library options
Version M-2017.06-SP1
Check date and time Thu Aug 9 16:10:09 2018
#BEGIN_LIBSCREEN_UPF
Library#1 (saed32hvt_ss0p95v125c):
Power management cell checking passed.
#END_LIBSCREEN_UPF
#BEGIN_XCHECK_LOGICCELLS
#END_XCHECK_LOGICCELLS
#BEGIN_XCHECK_LOGICPINS
#END_XCHECK_LOGICPINS
#BEGIN_XCHECK_LOGICPGPINS
Number of cells missing pg_pins in library 1: 0 (out of 294)
#END_XCHECK_LOGICPGPINS
#BEGIN_XCHECK_ARCS
#END_XCHECK_ARCS
#END_XCHECK_LIBRARY
Logic Library #1:

Library name saed32hvt_ff1p16v25c
File name /pd_libs/saed32hvt_ff1p16v25c.db
Time unit 1ns
Current unit 1uA
Library#1 (saed32hvt_ff1p16v25c):
#END_LIBSCREEN_UPF
#BEGIN_XCHECK_ARCS
#END_XCHECK_ARCS
#END_XCHECK_LIBRARY
Logic Library #1:

Library name saed32rvt_ss0p95v125c
File name /pd_libs/saed32rvt_ss0p95v125c.db
Time unit 1ns
Current unit 1uA
Library#1 (saed32rvt_ss0p95v125c):
#END_LIBSCREEN_UPF
#BEGIN_XCHECK_ARCS
#END_XCHECK_ARCS
#END_XCHECK_LIBRARY
Logic Library #1:

Library name saed32rvt_ff1p16v25c
File name /pd_libs/saed32rvt_ff1p16v25c.db
Time unit 1ns
Current unit 1uA
Library#1 (saed32rvt_ff1p16v25c):
#END_LIBSCREEN_UPF
#BEGIN_XCHECK_ARCS
#END_XCHECK_ARCS
#END_XCHECK_LIBRARY
Logic Library #1:

Library name saed32lvt_ss0p95v125c
File name /pd_libs/saed32lvt_ss0p95v125c.db
Time unit 1ns
Current unit 1uA
Library#1 (saed32lvt_ss0p95v125c):
#END_LIBSCREEN_UPF
#BEGIN_XCHECK_ARCS
#END_XCHECK_ARCS
#END_XCHECK_LIBRARY
Logic Library #1:

Library name saed32lvt_ff1p16v25c
File name /pd_libs/saed32lvt_ff1p16v25c.db
Time unit 1ns
Current unit 1uA
Library#1 (saed32lvt_ff1p16v25c):
#END_LIBSCREEN_UPF
#BEGIN_XCHECK_ARCS
#END_XCHECK_ARCS
#END_XCHECK_LIBRARY
Logic Library #1:

Library name saed32sram_ss0p95v125c
File name
Time unit 1ns
Current unit 1uA
Library#1 (saed32sram_ss0p95v125c):
PG checking passed.
No power management cells in library#1.
#END_LIBSCREEN_UPF
Information: List of cell classification (LIBCHK-312)

------------------------------------------------------------------------------
Library name saed32sram_ss0p95v125c(lib#1)
------------------------------------------------------------------------------
Total number 35
Inverter 0
Buffer 0
Level shifter 0
Differential level shifter 0
Isolation cell 0
Clock Isolation cell 0
Retention cell 0
Switch cell 0
Always on cell 0
------------------------------------------------------------------------------
#BEGIN_XCHECK_ARCS
#END_XCHECK_ARCS
#END_XCHECK_LIBRARY
Logic Library #1:

Library name saed32sram_ff1p16v25c
File name
/tools/libraries/28nm/SAED32_EDK/lib/sram/db_nldm/saed32sram_ff1p16v25c.db
Time unit 1ns
Current unit 1uA
Library#1 (saed32sram_ff1p16v25c):
PG checking passed.
#END_LIBSCREEN_UPF

------------------------------------------------------------------------------
Library name saed32sram_ff1p16v25c(lib#1)
------------------------------------------------------------------------------
Total number 35
Inverter 0
Buffer 0
Level shifter 0
Isolation cell 0
Retention cell 0
Switch cell 0
Always on cell 0
------------------------------------------------------------------------------
#BEGIN_XCHECK_ARCS
#END_XCHECK_ARCS
#END_XCHECK_LIBRARY
Checking library or object saed32pll_ss0p95v125c_2p25v ...
Logic Library #1:

Library name saed32pll_ss0p95v125c_2p25v
File name
Library Version Not Specified
Data Created Not Specified
Time unit 1ns
Leakage power unit 1uW
Current unit 1uA
Library#1 (saed32pll_ss0p95v125c_2p25v):
PG checking passed.
#END_LIBSCREEN_UPF

------------------------------------------------------------------------------
Library name saed32pll_ss0p95v125c_2p25v(lib#1)
------------------------------------------------------------------------------
Total number 1
Inverter 0
Buffer 0
Level shifter 0
Isolation cell 0
Retention cell 0
Switch cell 0
Always on cell 0
------------------------------------------------------------------------------
#BEGIN_XCHECK_ARCS
#END_XCHECK_ARCS
#END_XCHECK_LIBRARY
Checking library or object saed32pll_ff1p16v25c_2p75v ...
Logic Library #1:

Library name saed32pll_ff1p16v25c_2p75v
File name
/tools/libraries/28nm/SAED32_EDK/lib/pll/db_nldm/saed32pll_ff1p16v25c_2p75v.db
Library Version Not Specified
Data Created Not Specified
Time unit 1ns
Leakage power unit 1uW
Current unit 1uA
Library#1 (saed32pll_ff1p16v25c_2p75v):
PG checking passed.
#END_LIBSCREEN_UPF

------------------------------------------------------------------------------
Library name saed32pll_ff1p16v25c_2p75v(lib#1)
------------------------------------------------------------------------------
Total number 1
Inverter 0
Buffer 0
Level shifter 0
Isolation cell 0
Retention cell 0
Switch cell 0
Always on cell 0
------------------------------------------------------------------------------
#BEGIN_XCHECK_ARCS
#END_XCHECK_ARCS
#END_XCHECK_LIBRARY
Memory usage for this session 63 Mbytes.

CPU usage for this session 4 seconds ( 0.00 hours ).
Thank you...
Logic Library: saed32lvt_ss0p95v125c

saed32rvt_ss0p95v125c
saed32pll_ss0p95v125c_2p25v
saed32sram_ss0p95v125c
saed32hvt_ss0p95v125c
Physical Library:
/tools/libraries/28nm/SAED32_EDK/lib/pll/milkyway/SAED32_PLL_FR
/tools/libraries/28nm/SAED32_EDK/lib/sram/milkyway/SRAM32NM
check_library options:
Version: M-2016.12-SP5-4
Check date and time: Thu Aug 9 16:10:13 2018
List of logic library and file names

------------------------------------------------------------------------------
Logic library name Logic library file name
------------------------------------------------------------------------------
saed32lvt_ss0p95v125c /pd_libs/saed32lvt_ss0p95v125c.db
saed32rvt_ss0p95v125c /pd_libs/saed32rvt_ss0p95v125c.db
saed32pll_ss0p95v125c_2p25v
saed32sram_ss0p95v125c
saed32hvt_ss0p95v125c /pd_libs/saed32hvt_ss0p95v125c.db
------------------------------------------------------------------------------
Number of cells missing in logic library: 204 (out of 918)
Information: List of cells missing in logic library (LIBCHK-210)

-------------------------------------------------------------------------
Cell name Cell type Physical library
-------------------------------------------------------------------------
LSUPX1_RVT Core saed32nm_rvt_1p9m
LSDNSSX8_RVT Core saed32nm_rvt_1p9m
LSDNX1_RVT Core saed32nm_rvt_1p9m
LSUPENCLX1_RVT Core saed32nm_rvt_1p9m
LSUPENX1_RVT Core saed32nm_rvt_1p9m
LSDNENCLX4_RVT Core saed32nm_rvt_1p9m
LSDNENSSX1_RVT Core saed32nm_rvt_1p9m
LSDNENX1_RVT Core saed32nm_rvt_1p9m
LSDNENCLSSX1_RVT Core saed32nm_rvt_1p9m
HEADX2_RVT Core saed32nm_rvt_1p9m
FOOTX16_RVT Core saed32nm_rvt_1p9m
HEAD2X16_RVT Core saed32nm_rvt_1p9m
FOOT2X16_RVT Core saed32nm_rvt_1p9m
LSUPX1_LVT Core saed32nm_lvt_1p9m
LSDNSSX8_LVT Core saed32nm_lvt_1p9m
LSDNX1_LVT Core saed32nm_lvt_1p9m
LSUPENCLX1_LVT Core saed32nm_lvt_1p9m
LSUPENX1_LVT Core saed32nm_lvt_1p9m
LSDNENCLX4_LVT Core saed32nm_lvt_1p9m
LSDNENSSX1_LVT Core saed32nm_lvt_1p9m
LSDNENX1_LVT Core saed32nm_lvt_1p9m
LSDNENCLSSX1_LVT Core saed32nm_lvt_1p9m
HEADX2_LVT Core saed32nm_lvt_1p9m
FOOTX16_LVT Core saed32nm_lvt_1p9m
HEAD2X16_LVT Core saed32nm_lvt_1p9m
FOOT2X16_LVT Core saed32nm_lvt_1p9m
LSUPX1_HVT Core saed32nm_hvt_1p9m
LSDNSSX8_HVT Core saed32nm_hvt_1p9m
LSDNX1_HVT Core saed32nm_hvt_1p9m
LSUPENCLX1_HVT Core saed32nm_hvt_1p9m
LSUPENX1_HVT Core saed32nm_hvt_1p9m
LSDNENCLX4_HVT Core saed32nm_hvt_1p9m
LSDNENSSX1_HVT Core saed32nm_hvt_1p9m
LSDNENX1_HVT Core saed32nm_hvt_1p9m
LSDNENCLSSX1_HVT Core saed32nm_hvt_1p9m
HEADX2_HVT Core saed32nm_hvt_1p9m
FOOTX16_HVT Core saed32nm_hvt_1p9m
HEAD2X16_HVT Core saed32nm_hvt_1p9m
FOOT2X16_HVT Core saed32nm_hvt_1p9m
SRAMLP1RW128x48 Unknown saed32sram_lp
unitTile Unknown saed32sram_lp
-------------------------------------------------------------------------
#BEGIN_XCHECK_PHYSICALCELLS
Number of cells missing in physical library: 0 (out of 1122)
#END_XCHECK_PHYSICALCELLS
#BEGIN_XCHECK_PINS
Number of cells with missing or mismatched pins in libraries: 0
#END_XCHECK_PINS
#BEGIN_XCHECK_CELLANTENNADIODETYPE
Number of cells with inconsistent antenna_diode_type: 0
#END_XCHECK_CELLANTENNADIODETYPE
Logic vs. physical library check summary:

Number of cells missing in logic library: 204
Information: Logic library is INCONSISTENT with physical library (LIBCHK-220)
#END_XCHECK_LIBRARY
0
icc_shell> check_design
****************************************
check_design summary:
Version: M-2016.12-SP5-4
Date: Thu Aug 9 16:11:20 2018
****************************************
Name Total
--------------------------------------------------------------------------------
Inputs/Outputs 917
Undriven outputs (LINT-5) 505
Unloaded inputs (LINT-8) 162
Feedthrough (LINT-29) 174
Shorted outputs (LINT-31) 52
Constant outputs (LINT-52) 24
Cells 152
Cells do not drive (LINT-1) 1
Connected to power or ground (LINT-32) 118
Nets connected to multiple pins on same cell (LINT-33) 33
Nets 1226
Unloaded nets (LINT-2) 721
Undriven nets (LINT-3) 505
--------------------------------------------------------------------------------
Warning: In design 'dtmf_recvr_core', cell 'PM_INST' does not drive any nets. (LINT-1)
Warning: In design 'dtmf_recvr_core', net 'scan_in[0]' driven by pin 'scan_in[0]' has no loads.
(LINT-2)
(LINT-2)
(LINT-2)
Warning: In design 'dtmf_recvr_core', net 'scan_en' driven by pin 'scan_en' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'ibias' driven by pin 'ibias' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_DS_CS_INST/port_read' driven by pin
'TDSP_DS_CS_INST/port_read' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_DS_CS_INST/port_write' driven by pin
'TDSP_DS_CS_INST/port_write' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/t_sdi[2]' driven by pin
'TDSP_CORE_INST/t_sdi[2]' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_MUX/t_read' driven by pin 'TDSP_MUX/t_read'
has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'unused_clk' driven by pin 'PLLCLK_INST/CLK_4X' has
no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'SYNOPSYS_UNCONNECTED__71' driven by pin
'RAM_256x16_TEST_INST_2/O[34]' has no loads. (LINT-2)
'RAM_128x16_TEST_INST/O[16]' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'PM_INST/SYNOPSYS_UNCONNECTED__0' driven
by pin 'PM_INST/state_inst/power_control[3]' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/MPY_32_INST/ovm' driven by pin
'TDSP_CORE_INST/MPY_32_INST/ovm' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/ACCUM_STAT_INST/accum[32]'
driven by pin 'TDSP_CORE_INST/ACCUM_STAT_INST/accum[32]' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net
'TDSP_CORE_INST/TDSP_CORE_GLUE_INST/acc[32]' driven by pin
'TDSP_CORE_INST/TDSP_CORE_GLUE_INST/acc[32]' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/ACCUM_STAT_INST/ov' driven
by pin 'TDSP_CORE_INST/ACCUM_STAT_INST/ov' has no loads. (LINT-2)
'TDSP_CORE_INST/TDSP_CORE_GLUE_INST/alu_cmd[3]' driven by pin
'TDSP_CORE_INST/TDSP_CORE_GLUE_INST/alu_cmd[3]' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/PROG_BUS_MACH_INST/sync'
driven by pin 'TDSP_CORE_INST/PROG_BUS_MACH_INST/sync' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/DATA_BUS_MACH_INST/sync'
driven by pin 'TDSP_CORE_INST/DATA_BUS_MACH_INST/sync' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/PORT_BUS_MACH_INST/sync'
driven by pin 'TDSP_CORE_INST/PORT_BUS_MACH_INST/sync' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/EXECUTE_INST/pdr[15]' driven
by pin 'TDSP_CORE_INST/EXECUTE_INST/pdr[15]' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/EXECUTE_INST/pdr[9]' driven by
pin 'TDSP_CORE_INST/EXECUTE_INST/pdr[9]' has no loads. (LINT-2)
'TDSP_CORE_INST/TDSP_CORE_GLUE_INST/pc[15]' driven by pin
'TDSP_CORE_INST/TDSP_CORE_GLUE_INST/pc[15]' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/TDSP_CORE_GLUE_INST/pc[9]'
driven by pin 'TDSP_CORE_INST/TDSP_CORE_GLUE_INST/pc[9]' has no loads. (LINT-2)
'TDSP_CORE_INST/EXECUTE_INST/decode_skip_one' driven by pin
'TDSP_CORE_INST/EXECUTE_INST/decode_skip_one' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/DECODE_INST/phi_5' driven by
pin 'TDSP_CORE_INST/DECODE_INST/phi_5' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/EXECUTE_INST/phi_2' driven by
pin 'TDSP_CORE_INST/EXECUTE_INST/phi_2' has no loads. (LINT-2)
'TDSP_CORE_INST/SYNOPSYS_UNCONNECTED__0' driven by pin
'TDSP_CORE_INST/EXECUTE_INST/alu_cmd[3]' has no loads. (LINT-2)
'RESULTS_CONV_INST/SYNOPSYS_UNCONNECTED__443' driven by pin
'RESULTS_CONV_INST/sub_358_C165/DIFF[4]' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'RESULTS_CONV_INST/sub_358_C193/A[16]' driven
by pin 'RESULTS_CONV_INST/sub_358_C193/A[16]' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'RESULTS_CONV_INST/sub_358_C193/B[16]' driven
by pin 'RESULTS_CONV_INST/sub_358_C193/B[16]' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'RESULTS_CONV_INST/sub_358_C193/CI' driven by
pin 'RESULTS_CONV_INST/sub_358_C193/CI' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/ALU_32_INST/sub_84/CI' driven
by pin 'TDSP_CORE_INST/ALU_32_INST/sub_84/CI' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/ALU_32_INST/add_81/CI' driven
by pin 'TDSP_CORE_INST/ALU_32_INST/add_81/CI' has no loads. (LINT-2)
'TDSP_CORE_INST/MPY_32_INST/M16X16_INST/mult_8/TC' driven by pin
'TDSP_CORE_INST/MPY_32_INST/M16X16_INST/mult_8/TC' has no loads. (LINT-2)
'TDSP_CORE_INST/MPY_32_INST/M16X16_INST/mult_8/FS_1/B[1]' driven by pin
'TDSP_CORE_INST/MPY_32_INST/M16X16_INST/mult_8/FS_1/B[1]' has no loads. (LINT-2)
'TDSP_CORE_INST/MPY_32_INST/M16X16_INST/mult_8/FS_1/A[29]' driven by pin
'TDSP_CORE_INST/MPY_32_INST/M16X16_INST/mult_8/FS_1/A[29]' has no loads. (LINT-2)
'TDSP_CORE_INST/MPY_32_INST/M16X16_INST/mult_8/FS_1/CI' driven by pin
'TDSP_CORE_INST/MPY_32_INST/M16X16_INST/mult_8/FS_1/CI' has no loads. (LINT-2)
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/t_sdo[1]' has no drivers. Logic 0
assumed. (LINT-3)
assumed. (LINT-3)
assumed. (LINT-3)
Warning: In design 'dtmf_recvr_core', net 'scan_out[0]' has no drivers. Logic 0 assumed. (LINT-3)
Warning: In design 'dtmf_recvr_core', net 'vcop' has no drivers. Logic 0 assumed. (LINT-3)
Warning: In design 'dtmf_recvr_core', net 'vcom' has no drivers. Logic 0 assumed. (LINT-3)
Warning: In design 'dtmf_recvr_core', net 'switch_en_out' has no drivers. Logic 0 assumed. (LINT-
3)
Warning: In design 'dtmf_recvr_core', net 'RESULTS_CONV_INST/sub_380_C253/CO' has no
drivers. Logic 0 assumed. (LINT-3)
Warning: In design 'dtmf_recvr_core', net 'RESULTS_CONV_INST/sub_358_C165/DIFF[4]' has
no drivers. Logic 0 assumed. (LINT-3)
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/ALU_32_INST/add_81/CO' has no
Warning: In design 'dtmf_recvr_core', net 'TDSP_CORE_INST/ALU_32_INST/sub_84/CO' has no
'TDSP_CORE_INST/MPY_32_INST/M16X16_INST/mult_8/FS_1/CO' has no drivers. Logic 0
assumed. (LINT-3)
Warning: In design 'dtmf_recvr_core', output port 'scan_out[2]' is not driven. (LINT-5)
Warning: In design 'dtmf_recvr_core', output port 'switch_en_out' is not driven. (LINT-5)
Warning: In design 'dtmf_recvr_core', output port 'vcom' is not driven. (LINT-5)
Warning: In design 'dtmf_recvr_core', output port 'vcop' is not driven. (LINT-5)
Warning: In design 'tdsp_core', output port 't_sdo[1]' is not driven. (LINT-5)
Warning: In design 'results_conv_DW01_sub_4', output port 'DIFF[14]' is not driven. (LINT-5)
Warning: In design 'results_conv_DW01_sub_4', output port 'CO' is not driven. (LINT-5)
Warning: In design 'alu_32_DW01_add_0', output port 'CO' is not driven. (LINT-5)
Warning: In design 'alu_32_DW01_sub_0', output port 'CO' is not driven. (LINT-5)
Warning: In design 'm16x16_DW01_add_0', output port 'CO' is not driven. (LINT-5)
Warning: In design 'dtmf_recvr_core', input port 'scan_in[2]' is unloaded. (LINT-8)
Warning: In design 'dtmf_recvr_core', input port 'ibias' is unloaded. (LINT-8)
Warning: In design 'dtmf_recvr_core', input port 'scan_en' is unloaded. (LINT-8)
Warning: In design 'tdsp_ds_cs', input port 'port_write' is unloaded. (LINT-8)
Warning: In design 'tdsp_ds_cs', input port 'port_read' is unloaded. (LINT-8)
Warning: In design 'tdsp_core', input port 't_sdi[0]' is unloaded. (LINT-8)
Warning: In design 'tdsp_data_mux', input port 't_read' is unloaded. (LINT-8)
Warning: In design 'tdsp_core_glue', input port 'alu_cmd[3]' is unloaded. (LINT-8)
Warning: In design 'tdsp_core_glue', input port 'pc[11]' is unloaded. (LINT-8)
Warning: In design 'tdsp_core_glue', input port 'acc[32]' is unloaded. (LINT-8)
Warning: In design 'mult_32', input port 'ovm' is unloaded. (LINT-8)
Warning: In design 'accum_stat', input port 'ov' is unloaded. (LINT-8)
Warning: In design 'accum_stat', input port 'accum[32]' is unloaded. (LINT-8)
Warning: In design 'port_bus_mach', input port 'sync' is unloaded. (LINT-8)
Warning: In design 'data_bus_mach', input port 'sync' is unloaded. (LINT-8)
Warning: In design 'prog_bus_mach', input port 'sync' is unloaded. (LINT-8)
Warning: In design 'execute_i', input port 'decode_skip_one' is unloaded. (LINT-8)
Warning: In design 'execute_i', input port 'phi_2' is unloaded. (LINT-8)
Warning: In design 'execute_i', input port 'pdr[15]' is unloaded. (LINT-8)
Warning: In design 'decode_i', input port 'phi_1' is unloaded. (LINT-8)
Warning: In design 'results_conv_DW01_sub_4', input port 'CI' is unloaded. (LINT-8)
Warning: In design 'results_conv_DW01_sub_4', input port 'B[16]' is unloaded. (LINT-8)
Warning: In design 'results_conv_DW01_sub_4', input port 'A[16]' is unloaded. (LINT-8)
Warning: In design 'alu_32_DW01_add_0', input port 'CI' is unloaded. (LINT-8)
Warning: In design 'alu_32_DW01_sub_0', input port 'CI' is unloaded. (LINT-8)
Warning: In design 'm16x16_DW02_mult_0', input port 'TC' is unloaded. (LINT-8)
Warning: In design 'm16x16_DW01_add_0', input port 'CI' is unloaded. (LINT-8)
Warning: In design 'm16x16_DW01_add_0', input port 'B[10]' is unloaded. (LINT-8)
Warning: In design 'm16x16_DW01_add_0', input port 'A[29]' is unloaded. (LINT-8)
Warning: In design 'tdsp_ds_cs', input port 'address[0]' is connected directly to output port
't_address_ds[0]'. (LINT-29)
Warning: In design 'tdsp_core_glue', input port 'port_data_out[11]' is connected directly to output
port 'pdr[11]'. (LINT-29)
Warning: In design 'tdsp_core_glue', input port 'data_out[11]' is connected directly to output port
'p_data_in[11]'. (LINT-29)
'port_data_in[11]'. (LINT-29)
'ze_mdr[11]'. (LINT-29)
'mdr[11]'. (LINT-29)
'ze_mdr[12]'. (LINT-29)
'mdr[12]'. (LINT-29)
'ze_mdr[13]'. (LINT-29)
'mdr[13]'. (LINT-29)
'ze_mdr[14]'. (LINT-29)
'mdr[14]'. (LINT-29)
'se_shift_mdr[30]'. (LINT-29)
'ze_mdr[15]'. (LINT-29)
'mdr[15]'. (LINT-29)
'ze_mdr[3]'. (LINT-29)
'mdr[3]'. (LINT-29)
'mdr[4]'. (LINT-29)
'mdr[5]'. (LINT-29)
'mdr[6]'. (LINT-29)
'mdr[7]'. (LINT-29)
'mdr[8]'. (LINT-29)
'mdr[9]'. (LINT-29)
'ze_mdr[10]'. (LINT-29)
'mdr[10]'. (LINT-29)
'mdr[0]'. (LINT-29)
'mdr[1]'. (LINT-29)
'mdr[2]'. (LINT-29)
Warning: In design 'tdsp_core_glue', input port 'ir[10]' is connected directly to output port
'port_addrs_in[2]'. (LINT-29)
Warning: In design 'accum_stat', input port 'accum[31]' is connected directly to output port 'lz'.
(LINT-29)
Warning: In design 'port_bus_mach', input port 'addrs_in[0]' is connected directly to output port
'address[0]'. (LINT-29)
Warning: In design 'port_bus_mach', input port 'data_in[13]' is connected directly to output port
'pad_data_out[13]'. (LINT-29)
Warning: In design 'data_bus_mach', input port 'addrs_in[0]' is connected directly to output port
Warning: In design 'data_bus_mach', input port 'data_in[8]' is connected directly to output port
Warning: In design 'prog_bus_mach', input port 'addrs_in[7]' is connected directly to output port
Warning: In design 'prog_bus_mach', input port 'data_in[15]' is connected directly to output port
Warning: In design 'm16x16_DW01_add_0', input port 'A[8]' is connected directly to output port
'SUM[8]'. (LINT-29)
'SUM[9]'. (LINT-29)
'SUM[10]'. (LINT-29)
'SUM[11]'. (LINT-29)
'SUM[12]'. (LINT-29)
'SUM[13]'. (LINT-29)
'SUM[14]'. (LINT-29)
'SUM[0]'. (LINT-29)
'SUM[1]'. (LINT-29)
'SUM[2]'. (LINT-29)
'SUM[3]'. (LINT-29)
'SUM[4]'. (LINT-29)
'SUM[5]'. (LINT-29)
'SUM[6]'. (LINT-29)
'SUM[7]'. (LINT-29)
Warning: In design 'ulaw_lin_conv', output port 'lpcm[14]' is connected directly to output port
'lpcm[15]'. (LINT-31)
Warning: In design 'tdsp_core_glue', output port 'mdr[12]' is connected directly to output port
'ze_mdr[12]'. (LINT-31)
'ze_mdr[13]'. (LINT-31)
'ze_mdr[14]'. (LINT-31)
'ze_mdr[15]'. (LINT-31)
'ze_mdr[10]'. (LINT-31)
'ze_mdr[11]'. (LINT-31)
Warning: In design 'tdsp_core_glue', output port 'res_port_adr[0]' is connected directly to output
port 'port_addrs_in[0]'. (LINT-31)
Warning: In design 'dtmf_recvr_core', a pin on submodule 'TDSP_CORE_INST' is connected to
logic 1 or logic 0. (LINT-32)
Pin 't_sdi[0]' is connected to logic 0.
Warning: In design 'tdsp_core', a pin on submodule 'TDSP_CORE_GLUE_INST' is connected to
Pin 'enc_read_data' is connected to logic 0.
Pin 'enc_read_port' is connected to logic 0.
Pin 'alu_cmd[3]' is connected to logic 0.
Warning: In design 'tdsp_core', a pin on submodule 'ALU_32_INST' is connected to logic 1 or logic
0. (LINT-32)
Pin 'cmd[3]' is connected to logic 0.
Warning: In design 'results_conv', a pin on submodule 'sub_380_C253' is connected to logic 1 or
logic 0. (LINT-32)
Pin 'CI' is connected to logic 0.
logic 0. (LINT-32)
Pin 'B[16]' is connected to logic 0.
logic 0. (LINT-32)
Pin 'A[16]' is connected to logic 0.
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
Warning: In design 'alu_32', a pin on submodule 'add_81' is connected to logic 1 or logic 0. (LINT-
32)
Warning: In design 'alu_32', a pin on submodule 'sub_84' is connected to logic 1 or logic 0. (LINT-
32)
Warning: In design 'm16x16', a pin on submodule 'mult_8' is connected to logic 1 or logic 0. (LINT-
32)
Pin 'TC' is connected to logic 0.
Warning: In design 'm16x16_DW02_mult_0', a pin on submodule 'FS_1' is connected to logic 1 or
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
logic 0. (LINT-32)
Warning: In design 'dtmf_recvr_core', the same net is connected to more than one pin on submodule
'TDSP_DS_CS_INST'. (LINT-33)
Net 'port_write' is connected to pins 'port_write', 'port_read''.
Warning: In design 'dtmf_recvr_core', the same net is connected to more than one pin on submodule
'TDSP_CORE_INST'. (LINT-33)
Net 'SNPS_LOGIC0' is connected to pins 't_sdi[0]', 't_sdi[1]'', 't_sdi[2]'.
Warning: In design 'tdsp_core', the same net is connected to more than one pin on submodule
'TDSP_CORE_GLUE_INST'. (LINT-33)
Net 'SNPS_LOGIC0' is connected to pins 'enc_read_data', 'enc_read_port'', 'alu_cmd[3]'.
Warning: In design 'results_conv', the same net is connected to more than one pin on submodule
'sub_380_C253'. (LINT-33)
Net 'SNPS_LOGIC0' is connected to pins 'CI', 'B[16]'', 'A[16]'.
'sub_383_C253'. (LINT-33)
Net 'SNPS_LOGIC0' is connected to pins 'CI', 'B[15]'', 'B[16]', 'B[14]', 'A[16]'.
'sub_384_C253'. (LINT-33)
'sub_388_C253'. (LINT-33)
Net 'SNPS_LOGIC0' is connected to pins 'CI', 'B[15]'', 'B[16]', 'B[14]', 'A[16]'.
'sub_389_C253'. (LINT-33)
'sub_358_C220'. (LINT-33)
'sub_359_C220'. (LINT-33)
'sub_357_C229'. (LINT-33)
'sub_358_C229'. (LINT-33)
'sub_359_C229'. (LINT-33)
'sub_357_C238'. (LINT-33)
'sub_358_C238'. (LINT-33)
'sub_359_C238'. (LINT-33)
'sub_359_C193'. (LINT-33)
'sub_357_C202'. (LINT-33)
'sub_358_C202'. (LINT-33)
'sub_359_C202'. (LINT-33)
'sub_357_C211'. (LINT-33)
'sub_358_C211'. (LINT-33)
'sub_359_C211'. (LINT-33)
'sub_357_C220'. (LINT-33)
'sub_357_C165'. (LINT-33)
'sub_358_C165'. (LINT-33)
'sub_359_C165'. (LINT-33)
'sub_357_C184'. (LINT-33)
'sub_358_C184'. (LINT-33)
'sub_359_C184'. (LINT-33)
'sub_357_C193'. (LINT-33)
'sub_358_C193'. (LINT-33)
Warning: In design 'm16x16_DW02_mult_0', the same net is connected to more than one pin on
submodule 'FS_1'. (LINT-33)
Net 'SNPS_LOGIC0' is connected to pins 'CI', 'B[10]'', 'B[11]', 'B[12]', 'B[13]', 'B[14]', 'B[2]',
'B[3]', 'B[4]', 'B[5]', 'B[6]', 'B[7]', 'B[8]', 'B[9]', 'A[29]', 'B[0]', 'B[1]'.
Warning: In design 'tdsp_core_glue', output port 'ze_mdr[28]' is connected directly to 'logic 0'.
(LINT-52)
(LINT-52)
(LINT-52)
(LINT-52)
(LINT-52)
(LINT-52)
(LINT-52)
(LINT-52)
(LINT-52)
(LINT-52)
(LINT-52)
(LINT-52)
(LINT-52)
(LINT-52)
(LINT-52)
(LINT-52)
Warning: In design 'tdsp_core_glue', output port 'res_port_adr[4]' is connected directly to 'logic 0'.
(LINT-52)
(LINT-52)
(LINT-52)
(LINT-52)
(LINT-52)
Warning: In design 'execute_i', output port 'read_port' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'execute_i', output port 'read_data' is connected directly to 'logic 0'. (LINT-52)
Warning: In design 'execute_i', output port 'alu_cmd[3]' is connected directly to 'logic 0'. (LINT-52)
1
icc_shell> check_design > reports/dtmf_check_design_import.rpt
icc_shell> sh gvim reports/dtmf_check_design_import.rpt
icc_shell> check_timing > reports/dtmf_check_timing_import.rpt
icc_shell> sh gvim reports/dtmf_check_timing_import.rpt
icc_shell> check_design > reports/dtmf_check_design_import.rpt
icc_shell> sh gvim reports/dtmf_check_design_import.rpt
icc_shell> check_timing > reports/dtmf_check_timing_import.rpt
icc_shell> exit
Thank you...

Loading 28nm SAED32 Design Libraries

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Loading 28nm SAED32 Design Libraries

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Loading db file '/pd_libs/saed32hvt_ss0p95v125c.

***** Verilog HDL translation! *****

***** Start Pass 1 *****

***** Pass 1 Complete *****

***** Verilog HDL translation! *****

***** Start Pass 2 *****

***** Pass 2 Complete *****

***** Verilog HDL translation completed! *****

The quick-attach skip-search mode has been turned off.

Linking design 'dtmf_recvr_core'

Reading SDC version 2.0...

Logic Library #1:

Number of cells missing pg_pins in library 1: 0 (out of 294)

Logic Library #1:

Number of cells missing pg_pins in library 1: 0 (out of 294)

Logic Library #1:

Number of cells missing pg_pins in library 1: 0 (out of 294)

Logic Library #1:

Number of cells missing pg_pins in library 1: 0 (out of 294)

Logic Library #1:

Number of cells missing pg_pins in library 1: 0 (out of 294)

Logic Library #1:

Number of cells missing pg_pins in library 1: 0 (out of 294)

Logic Library #1:

Information: List of cell classification (LIBCHK-312)

Number of cells missing pg_pins in library 1: 0 (out of 35)

Logic Library #1:

Information: List of cell classification (LIBCHK-312)

Number of cells missing pg_pins in library 1: 0 (out of 35)

Logic Library #1:

Information: List of cell classification (LIBCHK-312)

Number of cells missing pg_pins in library 1: 0 (out of 1)

Checking library or object saed32pll_ff1p16v25c_2p75v ...

Logic Library #1:

Information: List of cell classification (LIBCHK-312)

Number of cells missing pg_pins in library 1: 0 (out of 1)

Memory usage for this session 63 Mbytes.

Logic Library: saed32lvt_ss0p95v125c

List of logic library and file names

Number of cells missing in logic library: 204 (out of 918)

Information: List of cells missing in logic library (LIBCHK-210)

Number of cells missing in physical library: 0 (out of 1122)

Number of cells with missing or mismatched pins in libraries: 0

Number of cells with inconsistent antenna_diode_type: 0

Logic vs. physical library check summary:

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* Verilog HDL translation! *

* Start Pass 1 *

* Pass 1 Complete *

* Verilog HDL translation! *

* Start Pass 2 *

* Pass 2 Complete *

* Verilog HDL translation completed! *