hphone_l_reg[0]

C 0
0 Q
D

RTL_REG

hphone_l_reg[1]

C 1
1 Q
D

RTL_REG

hphone_l_reg[2]

C 2
2 Q
D

RTL_REG

hphone_l_reg[3]

C 3
3 Q
D

RTL_REG

hphone_l_reg[4]

C 4
4 Q
D

RTL_REG

hphone_l_reg[5]

C 5
5 Q
D

RTL_REG

hphone_l_reg[6]

C 6
6 Q
D

RTL_REG

hphone_l_reg[7]

C 7
7 Q
D

RTL_REG

hphone_l_reg[8]

C 8
8 Q
D

RTL_REG

hphone_l_reg[9]

C 9
9 Q
D

RTL_REG

hphone_l_reg[10]

C 10
10 Q
D

RTL_REG

hphone_l_reg[11]

C 11
11 Q
D

RTL_REG

hphone_l_reg[12]

C 12
12 Q
D

RTL_REG

hphone_l_reg[13]

C 13
13 Q
D

RTL_REG

hphone_l_reg[14]

C 14
14 Q
D

RTL_REG

hphone_l_reg[15]

C 15
15 Q
D

RTL_REG

hphone_l_reg[16]

C 16
16 Q
D

RTL_REG

hphone_l_reg[17]

C 17
17 Q
D

RTL_REG

hphone_l_reg[18]

C 18
18 Q
D

RTL_REG

hphone_l_reg[19]

C 19
19 Q
D

RTL_REG

hphone_l_reg[20]

C 20
20 Q
D

RTL_REG

hphone_l_reg[21]

C 21
21 Q
D
AC_ADR0_OBUF_inst
RTL_REG I O
AC_ADR0
AC_GPIO1 OBUF
AC_GPIO2 AC_ADR1_OBUF_inst
I O
hphone_l_reg[22] AC_ADR1
i_audio OBUF
C 22
22 Q AC_GPIO0_OBUF_inst
D AC_GPIO1 AC_ADR0 I O
AC_GPIO0
RTL_REG AC_GPIO2 AC_ADR1
OBUF
AC_GPIO3 AC_GPIO0
AC_GPIO3 AC_MCLK_OBUF_inst
AC_SDA AC_MCLK I O
hphone_l_reg[23] AC_MCLK
clk_100 AC_SCK
OBUF
C 23 hphone_l[23:0] line_in_l[23:0]
23 Q AC_SCK_OBUF_inst
D hphone_l_valid line_in_r[23:0] I O
AC_SCK
RTL_REG hphone_r[23:0] new_sample
OBUF
clk_100_IBUF_inst BUFG_inst hphone_l_i hphone_r_valid_dummy sample_clk_48k
I O I O
clk_100 S=1'b1 I0[23:0]
hphone_valid_reg audio_top
O[23:0]
IBUF BUFG S=default I1[23:0]
AC_SDA
C
S RTL_MUX Q
D

RTL_REG

hphone_r_i
g_audi
S=1'b1 I0[23:0]
O[23:0]
CLK S=default I1[23:0]
blockamp hphone_r_reg[0]
DIR[23:0]
S RTL_MUX
ga0[7:0] fout[23:0] fout[23:0] C 0
ga0[7:0] ma 0 Q
ga1[7:0] D
ga1[7:0]
DIR[23:0] DIR[23:0] RTL_REG
ga2[7:0] blockFFT blockmaxbin
ga0[7:0] x[7:0]
ga3[7:0] hphone_r_reg[1]
s3di0[23:0] s3di0[23:0] mult8
s3di1[23:0] s3di1[23:0] C 1
mb 1 Q
s3di2[23:0] s3di2[23:0] D

CLK s3di3[23:0] s3di3[23:0] max_bin[2:0] DIR[23:0] RTL_REG

DIR[23:0] s3dr0[23:0] s3dr0[23:0] ga1[7:0] x[7:0]
hphone_r_reg[2]
s3dr1[23:0] s3dr1[23:0] mult8_HD1
s3dr2[23:0] s3dr2[23:0] C 2
mc 2 Q
s3dr3[23:0] s3dr3[23:0] D

fft maxbin DIR[23:0] RTL_REG

ga2[7:0] ga2[7:0] x[7:0]
hphone_r_reg[3]
mult8_HD2
C 3
md 3 Q
D

DIR[23:0] RTL_REG
ga3[7:0] ga3[7:0] x[7:0]
hphone_r_reg[4]
sel[2:0] mult8_HD3
C 4
4 Q
amplifier1 D

top RTL_REG

hphone_r_reg[5]

C 5
5 Q
D

RTL_REG

hphone_r_reg[6]

C 6
6 Q
D

RTL_REG

hphone_r_reg[7]

C 7
7 Q
D

RTL_REG

hphone_r_reg[8]

C 8
8 Q
D

RTL_REG

hphone_r_reg[9]

C 9
9 Q
D

RTL_REG

hphone_r_reg[10]

C 10
10 Q
D

RTL_REG

hphone_r_reg[11]

C 11
11 Q
D

RTL_REG

hphone_r_reg[12]

C 12
12 Q
D

RTL_REG

hphone_r_reg[13]

C 13
13 Q
D

RTL_REG

hphone_r_reg[14]

C 14
14 Q
D

RTL_REG

hphone_r_reg[15]

C 15
15 Q
D

RTL_REG

hphone_r_reg[16]

C 16
16 Q
D

RTL_REG

hphone_r_reg[17]

C 17
17 Q
D

RTL_REG

hphone_r_reg[18]

C 18
18 Q
D

RTL_REG

hphone_r_reg[19]

C 19
19 Q
D

RTL_REG

hphone_r_reg[20]

C 20
20 Q
D

RTL_REG

hphone_r_reg[21]

C 21
21 Q
D

RTL_REG

hphone_r_reg[22]

C 22
22 Q
D

RTL_REG

hphone_r_reg[23]

C 23
23 Q
D

RTL_REG