Proceedings- Books 3
Design of Discrete PID Controller to Improve
Performance of Power Factor Correction (PFC) Circuit
Aripriharta, Lecturer State Universty of Malang (UM) &
Member of IAENG, aripriharta@um.ac.id
Abstract – Recently, an adjustable speed drive (ASD) is
widely used on many industries. A power factor is one of
important aspect to be considered, since it can
drawback reactive power to supply side during its
operating condition. This paper presents a discrete PID
algorithm which applied by inner and outer loops
controller circuit. This makes a better control action on
power factor correction (PFC) circuit based on buck
topology. Three phase IGBT inverter loaded by 10 hp
220/380 V 50 Hz squirrel cage induction motor is used
as a PFC load to meet real implementation on
industries. This proposed system is designed and
simulated by PSIM software. From the simulation result,
a control circuit achieve its best performance. A power
factor increase significantly.
Keywords: discrete PID controller, PID algorithm,
power factor, PFC circuit, adjustable speed drive.
1 Introduction
ASD (also called VSD or VFD) is widely used on
many industries. AC adjustable-speed drives (ASD) are
growing in popularity, mainly because ac motors are
simpler than dc motors. Moreover, recent advances in
inverter and microprocessor technology have reduced
controller cost and improved its performance and
reliability [1].
Figure 1. Generic block diagram of ASD
AC ASD can be thought of as electrical control devices
that change the operating speed of a motor. ASD’s are
able to vary the operating speed of the motor by
changing the electrical frequency input to the motor. The
basic steps for this process are shown in the block
diagram of Figure 1, and the circuit is known as a DC
link converter. The first step is to convert AC power into
DC power. The second step is to convert this DC power
back into AC at the desired frequency [ 1],[2].
Setiadi Cahyono Putro, Senior Lecturer State Universty of
Malang (UM), scp0324@yahoo.com
Although they can improve displacement power factor
(DPF), modern ASDs also create harmonics, which
reduce real power factor. (Real power factor includes
harmonics and DPF.) For instance, while a ASD can
improve DPF to close to 1.0, the harmonics generated by
the ASD can cause the real power factor to decline to
between 0.75 and 0.80. These harmonic currents (most
often the fifth and seventh harmonics) tend to exacerbate
resistance losses and can even negate the transformer
capacity benefits of improved DPF [4], [5],[6].
A power factor is one of important aspect to be
considered, since it can drawback reactive power to
supply side during its operating condition. To increase
power factor is to make the input to a power supply
(rectifier) look like a simple resistor. An active power
factor corrector does here by programming the input
current in response to the input voltage [6]. Power factor
(p.f) is defined as the ratio of the real power (P in Watt)
to the apparent power (S in VA), i.e.,
P
p. f = [1]
S
or, it can be written as,
P
p. f = [2]
VI
where P is the input real power, V is the root-mean-
square (rms) input voltage and I is the rms input current.
There are two factors affect the power factor. First, if
the input voltage and current are not in phase, P will be
less than the product of V and I, leading to a low power
factor. The worst case corresponds to a 90o phase shift
between V and I. Second, if the current contains a high
harmonic content, I becomes large, again leading to a
low power factor. Mathematically we can express the
power factor as the product of a displacement factor
(DPF) and a distortion factor, i.e.,
1
p. f = cos ϕ • 2 2
[3]
1 +  2 I  +  3 I  + ....
I I
Displacement  1  1
factor
Distortion factor
125

or in brief,
cos ϕ
p. f = [4]
1 + (THD)2
where φ is the phase difference between the fundamental
input voltage and current, Ih (h=1,2,3, …) is the rms ith
harmonic input current, and THD is the total harmonic
distortion [7],[8].
Theoretically, unity power factor (PF=1), in the case of
a simple one-port network, requires that the phase shift
between the voltage and the current be zero, and that the
current be free from harmonic distortion. In circuit
terms, these requirements call for an input impedance
resembling a linear resistor, i.e., a zero-order linear one-
port.
Although quite a number of switching circuits are
already being used in practical PFC, they are scattered in
the literature as isolated cases of innovative circuit
designs. Moreover, little formal work has been reported
on the basic topological requirements of these circuits
that can shed light on the creation of new PFC
topologies.
PFC is generally used to compensate systems in which
the source current and voltage waveforms are out of
phase and/or distorted. Usually, the goal of the PFC
circuit is harmonic correction. A variety of circuit
topologies and control methods have been developed for
the PFC application. This can be passive or active circuit
[8].
In section 2 we will present our proposed system, a
discrete PID algorithm which applied by inner and outer
loops for the active PFC controller circuit.
2 System Description
As a brief review, first we consider a generic block
diagram of proposed system reveals the addtion of active
PFC circuit with its control circuit on a genering ASD on
Figure 1. It’s clearly shown on Figure 2.
Figure 2. A block diagram of proposed system
Design of Discrete PID Controller .........
126
An ASD is a device that controls the rotational speed
of motor-driven equipment. Variable frequency drives
(VFDs), the most common type of ASDs, efficiently meet
varying process requirements by adjusting the frequency
and voltage of the power supplied to an AC motor to
enable it to operate over a wide speed range. External
sensors monitor flow, liquid levels, or pressure and then
transmit a signal to a controller that adjusts the
frequency and speed to match process requirements.
2.1 Basic Operation Principle
The proposed system is designed to integrate an active
PFC control with a real motor control application. The
base is the 3-phase squirrel cage induction motor with v/f
speed open loop application to represent ASD. This
system integrates two independent parts that keep all
their own features. First is a 3-phase ac motor drive with
v/f speed open loop algorithm; the second is a PFC
algorithm (see Figure 3). A 3 phase insulated gated
bipolar transistor (IGBT) inverter and its control circuit
runs the main control algorithm. It generates a 3-phase
Pulse Width Modulation (PWM) output signal for the
motor according to the user’s input. The objective of
PWM is to shape and control the three-phase output
voltages in magnitude and frequency by utilization of a
constant DC voltage.
The PWM power circuit is commonly used with three
basic types of regulators. It is these regulators that
largely determine the drive capabilities, including
response, speed regulation due to transient load changes,
and low-speed torque capabilities. Pulse-width
modulated (PWM) VFDs are most often used in variable
torque applications in the 1 to 1,000 hp motor size
range.
PWM is a process where three-phase sinusoidal signals
are compared with a repetitive switching frequency
triangular waveform, thus create the desired symmetrical
synchronized PWM) through the 6 PWM signal
generators. The 6 PWM signals are applied to the 6
MOSFETs on the three phase inverter via the MOSFET
drivers. In spite of this, because of the finite turn-on and
turn-off times associated with any type of switch, the
design requires the inclusion of slight time delays when
the MOSFETs are switching [7][8].
A dead band is the time delay between switching off
one MOSFET on a phase of the inverter and switching
on the complementary MOSFET. This ensures that any
time delay in switching off a device does not lead to a
shoot-through short circuit that can damage the circuit
when its partner is switched on. As a consequence of
this, a sinusoidal signal is created [9].
The system also controls the active PFC circuit that
provides the power supply for the motor. The main
 Proceedings- Books 3

advantage of the power factor correction system is the 2.2.2 Design of Discrete PID Inner and Outter
reduction of electrical noise. This will be possible if the
Loop
input current waveform is sine-like.
The proposed system does not directly control the PFC Unlike simple control algorithms, the PID controller is
switch. It modifies the PFC reference voltage and capable of manipulating the process inputs based on the
current, which makes possible an inner and outer loop history and rate of change of the signal. This gives a
for inventing PID algorithm. Thus a simple a 3-point more accurate and stable control method. Figure 3 shows
sine approximation of the input current waveform the PID controller schematics integrated with the main
appears. It is enough to comply with IEC standard and system, where implemeted by computational discrete
simplifies control software complexity. The second PFC block on PSIm software. This algorithm represent the
feature is the stable output voltage. The active PFC generic discrete PID transfers function, i.e,
circuit is a buck voltage converter, so output voltage
cannot be higher than rectified input voltage. u(n) = K p e(n) + K i ∑ e( k ) + K d ( e(n) − e(n − 1))
k =0
2.2 Development of PFC Controller
… [4]
Generally speaking, any of the basic converters
operating in discontinuous mode can be chosen as a PFC where
stage; there are buck, boost, and buck-boost converter T
being the perfect choice as far as power factor is Ki = K p [5]
concerned. In this paper, we try buck topology for our
Ti
PFC stage as shown on Figure 3. It’s true that the and
discontinuous-mode buck converter can achieve very K pTd
high power factor with small duty-cycle values. But, It Kd = [6]
Ti
suffers high peak current stress [4], [8].

2.2.1 System Model Ti, and Td denotes the time constants of the integral, and
derivative terms respectively. The terms of Kp, Ki, and
Digital controllers can offer a number of advantages Kd denotes the gain of the proportional, integral, and
over analog controllers, including flexibility, lower derivative terms respectively.
sensitivity, and programmability without external
components. Figure 3 shows a digitally controlled buck As we can see from Figure 3, an outter loop of
switching converter. It consists of a discrete PID ineer, a descrete PID is obtained from Figure 4 as an
discrete PID outter and and gate drive to create a pulse indenpendent parts for explain its form.
modulated waveform which is applied by a computation
discrete block on PSIM to implements a control law. In
order to achieve dynamic characteristics comparable with
analog PWM controllers, fast implementation of a
discrete-time control law is required.

Figure 4 Discrete PID Outter Loop

Figure 4 respect to the equation bellow
U1 ( z)  T (1 − Z −1 ) 
= Kp 1 + −1
+ T 
 Ti (1 − Z )
d
E1 ( z) T 
[7]

where U1(z) and E1(z) represent z-domain of the fisrt

Figure 3 Front-end PFC stage.
PFC control circuit used on Fig. 2 is implemented by
discrete PID algorithm which applied by inner and outer
loops controller circuit to make a desired control need.
PID schematics. A delay, ZOH block is used to close the
real implementations of simulation circuit.
The middle stage of inner and outter loop is multiplier
that is used to multiply the U1(z) and delay input voltage
of 3-phase rectifier called middle delay commputational
unit . It’s used as a reference for inner loop PID stage.
Figure 5 clearly shows this middle schematics.

127
 Design of Discrete PID Controller .........
128

This realize by a buck converter to provide a necessary

dc gain on DC link capasitor, which is connected to 3-
phase IGBT inverter. A generic PWM control circuit
generated a signal to operate inverter to drives squirrel
cage induction motor, which attached by mechanical
load to meet real implementation on industries. Table 1
shows the parameter of induction motor used in this
paper.
Figure 5 Middle Delay Computational Unit
Table 1. Squirrel cage Induction Motor Parameter
Figure 6 reresents an inner loop of descrete PID is
Parameter Amount
used on Figure 4 also as an indenpendent parts for
explain its form. Voltage 220/380V
Number of Phase 3
Type Squirrel cage
kW 7.5 kW (10 Hp)
Frekwency 50 Hz
Number of pole(s) 6
Efficiency 89 % (full load)
Power Factor 79 %
Speed 940 rpm

Figure 7 show the circuit test of ASD without

implement PFC stage. Figure 8a. and Figure 8b show the
Figure 5 Discrete PID Inner Loop completely system proposed. It’s expanded on its preview
sight.
Figure 4 respect to the equation bellow
U2 (z)  T ( 1 − Z −1 ) 
= Kp 1 + −1
+ T 
 Ti (1 − Z )
d
E2 ( z) T 
[8]

where U2(z) and E2(z) represent z-domain of the fisrt

PID schematics. A delay, ZOH block is also used to close
the real implementations of simulation circuit.

The output descrete computatinal circuit (PID inner)

on Figure 5 capture by PWM circuit to provide a desired
signal for MOSFET operation on buck converter (PFC
stage). This Figure 6 below shows this circuit topology.
Figure 7 ASD test circuit

Figure 6 PWM circuit for MOSFET on PFC stage

In section 3 we use PSIM software to simulate the

proposed system.

3 Simulation Setup
A 3-phase voltage source Y connected (with ground),
a. rectifier and PFC stage
50 Hz system supply the 3-phase diode rectifier to create
a fixed dc voltage at desired value. Then, dc output
voltage from rectifier is consumed by active PFC circuit.
 Proceedings- Books 3

c. DPF, PF and VA
Figure 9 Without PFC

The simulation result for circuit on Figure 8a and

b. ASD stage
Figure 8b is the second scenario of this experiment. This
results of three graph or performance of ASD after
Figure 8 Proposed system test circuit (front-end
addition of PFC stage with the proposed control method,
expanded)
as shown bellow. Figure 10a. show the input current for
4 Result and Analysis each phase Is1, Is2, Is3 respectively. And, Figure 10b.
shows the motor current Isa, Isb, and Isc respectively.
In this paper, the simulation result for circuit on Figure 7 Figure 10c show the DPF, PF and VA in separated
is the first scenario of this experiment. This results of graphs.
three graph or performance of ASD before addition of
PFC stage, as shown on Figure 9 bellow. Figure 9a. show
the input current for each phase Ia, Ib, Ic respectively.
And, Figure 9b. shows the motor current Isa, Isb, and Isc
respectively. Figure 9c show the DPF, PF and VA in
separated graphs.

a. source current

a. input current
b. motor current

c. DPF, PF and VA

Figure 10. with PFC

By comparing the result, we get the conclution about
this work, which is the buck topology of PFC circuit
which is controlled by discrete PID inner and outter loop
can make a power factor increase significantly. A
discrete PID algorithm which applied by inner and outer
b. Motor current loops controller circuit makes a better control action on
power factor correction (PFC) circuit based on buck
topology.

129
 Design of Discrete PID Controller .........
130

5 Conclusions
In conclution, by adding the buck topology of PFC
circuit which controlled with a proposed method has
achieve its best performance. A discrete PID algorithm
which applied by inner and outer loops controller circuit
makes a better control action on power factor correction
(PFC) circuit based on buck topology. From the
simulation result a power factor on this system is
increase significantly.

References
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Correction on Variable Speed Drive Systems,
Dissertation submitted to the Faculty of the
Virginia Polytechnic Institute and State
University in partial fulfillment of the
requirements for the degree of Doctor of
Philosophy in Electrical and Computer
Engineering, February 17, 1999, Blacksburg,
Virginia
[2] Thida Win, Nang Sabai, And Hnin Nandar
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World Academy Of Science, Engineering And
Technology Volume 32 August 2008, Pp. 758-
762
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