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Digital Architecture For An Uwb Radio Reciever2
Digital Architecture For An Uwb Radio Reciever2
GROUP NO.5
Electric circuits (ID1310)
Indian Institute of Technology,Hyderabad
UWB Flavors
Multicarrier. 500 MHz from 3.1 to 10.6 GHz
Time
Frequency
Physically
10log|S112|= -Return Loss < -10 dB
Small
Current Design:
1.0 x 1.9in.
Wave Reception
Constant Group
Delay
High Radiation Efficiency
Target Omnidirectional Radiation Pattern (Non-
directive)
Analog Front-End
FLASH
G ADC
Samples to
90o Φn
Φn Samples to
Back-End
G FLASH
ADC
Control
Back-End
A/D Converter
500+Msps ⇒ FLASH converters or FLASH
interleaved converters.
Coarse
From Acquisition
ADCs Subsystem
Fine
Tracking
Subsystem
Coarse acquisition
Fine tracking
Time
FD
Nc = 31, duty cycle = 2%, Pfa Pcd
∆delay = pulse width ⇒ N 10-3 0.42
Early/Late
Signal generator Filter
Received
signal
Multiplier Integrate & Dump
20 ppm, width = 2ns ⇒ 25µs for static users.
Signals with Same Bit Rate
Target bit rate: 100Mbps
Options:
Pulses of 2ns width separated 10ns from one another.
BPSK.
OFDM with 256 carriers, prefix of 54 ns. Duration of
the symbol: 310 ns. Each carrier modulated using
BPSK. 31 bits per symbol.
Assumptions:
Time and frequency synchronization achieved.
No need for channel equalization
Instantaneous AGC.
Demodulation of UWB Signals
Samples Bits
Pulsed UWB Integrate & Dump Slicer
Bits
Samples
OFDM UWB
Noise Limited Case
Pulsed UWB OFDM UWB
-10 -5 0 5 10 15 -10 -5 0 5 10 15
SNR (dB) SNR (dB)
-10 -5 0 5 10 -10 -5 0 5 10
SIR (dB) SIR (dB)
Conclusions
Digital architecture ⇒ programmability and scalability.