Computer Manual

A
INTEL PENTIUM II/PENTIUM III PROCESSOR (SC242) / INTEL

810e CHIPSET
UNIPROCESSOR CUSTOMER REFERENCE SCHEMATICS
REVISION 1.0
Title
Page
Cover Sheet
Block Diagram
SC242 Connector
Clock Synthesizer
82810e
Display Cache
6, 7, 8
9
System Memory
10, 11
ICH
12, 13
FWH
14
Super I/O
15
16, 17
PCI Connectors
THESE SCHEMATICS ARE PROVIDED "AS IS" WITH NO WARRANTIES

WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS
FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING
OUT OF PROPOSAL, SPECIFICATION OR SAMPLES.
3,4
ULTRA-ATA66 IDE Connectors
18
USB Connectors
19
Parallel Port
20
Serial Port/COM Headers
21
Kybrd / Mse / F. Disk / Gme Connectors
22
Digital Video Out
23
Video Connectors
24
Audio/Modem Riser
25
26, 27
LAN
** Please note these schematics are subject to change.
Voltage Regulators
28
Processor Voltage Regulator (VRM8.4 rev 1.5)

System
29
30, 31
Pullup Resistors and Unused Gates
32
DRAM, Chipset,and Bulk Power Decoupling
33
Information in this document is provided in connection with Intel products. No license,

express or implied, by estoppel or otherwise, to any intellectual property rights is
granted by this document. Except as provided in Intel's Terms and Conditions of Sale
for such products, Intel assumes no liability whatsoever, and Intel disclaims any
express or implied warranty, relating to sale and/or use of Intel products including
liability or warranties relating to fitness for a particular purpose, merchantability, or
infringement of any patent, copyright or other intellectual property right. Intel products
are not intended for use in medical, life saving or life sustaining applications.
Intel may make changes to specifications and product descriptions at any time,
without notice.
The Intel Celeron(tm) processor and Intel 810e chipset may contain design defects or
errors known as errata which may cause the product to deviate from published
specifications. Current characterized errata are available on request.
Copyright (c) Intel Corporation 1999.
* Third-party brands and names are the property of their respective owners.
Title: Intel 810e Chipset Customer Reference Board
REV.
Cover Sheet
intel
A
Platform Components Division

1900 Prairie City Road
Folsom, Ca. 95630
1.0
Last Revision Date:
Sheet:
6/14/99
of
33
Block Diagram
Slot 1 Processor
VRM
Clock
DATA
CTRL
ADDR
Term
DATA
CTRL
ADDR
Display Cache
Memory
2 DIMM
Modules
GMCHE
Digital Video
Out Device
IDE Primary
PCI ADDR/DATA
USB
AMC'97
Audio/Modem
AC'97 Link
LPC Bus
USB Port 1
USB Port 2
PCI CONN 3
PCI CNTRL
ICH
PCI CONN 2
PCI CONN 1
UltraDMA/66
IDE Secondary
PCI CNTRL
PCI ADDR/DATA
LAN
SIO
FirmWare
Hub
Keyboard
Mouse
Floppy
Parallel
Game Port
Serial 1
REV.
1.0
Block Diagram
intel
A

Folsom, Ca. 95630
Last Revision Date:

Sheet:
6/14/99
of
33
J20A
SC242
CONNECTOR
Part 1
6 HD#[63:0]
HD#0
B72
HD#1
A73
HD#2
B71
HD#3
A72
HD#4
B70
HD#5
A71
HD#6
B68
HD#7
B67
HD#8
A69
HD#9
A68
HD#10
A65
HD#11
A64
HD#12
B66
HD#13
A63
HD#14
A67
HD#15
B64
HD#16
A61
HD#17
B63
HD#18
B60
HD#19
B59
HD#20
B62
HD#21
A60
HD#22
B58
HD#23
A59
HD#24
A57
HD#25
B56
HD#26
B55
HD#27
A56
HD#28
B52
HD#29
B54
HD#30
A55
HD#31
A53
HD#32
B51
HD#33
A51
HD#34
B48
HD#35
A52
HD#36
B46
HD#37
A49
HD#38
B50
HD#39
A45
HD#40
B47
HD#41
B42
HD#42
A43
HD#43
A48
HD#44
B44
HD#45
A44
HD#46
A39
HD#47
B43
HD#48
B39
HD#49
A40
HD#50
B35
HD#51
A41
HD#52
B40
HD#53
A36
HD#54
B36
HD#55
A33
HD#56
B34
HD#57
A37
HD#58
B31
HD#59
B38
HD#60
A35
HD#61
A32
HD#62
B30
HD#63
B32
HD#0
HD#1
HD#2
HA#3
HD#3
HA#4
HD#4
HA#5
HD#5
HA#6
HD#6
HA#7
HD#7
HA#8
HD#8
HA#9
HD#9
HA#10
HD#10
HA#11
HD#11
HA#12
HD#12
HA#13
HD#13
HA#14
HD#14
HA#15
HD#15
HA#16
HD#16
HA#17
HD#17
HA#18
HD#18
HA#19
HD#19
HA#20
HD#20
HA#21
HD#21
HD#22
HD#23
HA#22
SC242
HA#23
HA#24
HD#24
HA#25
HD#25
HA#26
HD#26
HA#27
HD#27
HA#28
HD#28
HA#29
HD#29
HA#30
HD#30
HA#31
HD#31
HA#32
HD#32
HA#33
HD#33
HA#34
HD#34
HA#35
HD#35
HD#36
VID0
HD#37
VID1
HD#38
VID2
HD#39
VID3
HD#40
VID4
HD#41
HD#42
RS#0
HD#43
RS#1
HD#44
RS#2
HD#45
HD#46
RSP#
HD#47
HD#48
REQ#0
HD#49
REQ#1
HD#50
REQ#2
HD#51
REQ#3
HD#52
REQ#4
B98
A100
A97
B99
B96
B95
A99
A96
B92
B94
A93
A95
B90
A92
B91
A91
A89
B86
B87
A85
A87
B83
B88
B82
A84
B84
B80
A81
A83
HA#3
HA#4
HA#5
HA#6
HA#7
HA#8
HA#9
HA#10
HA#11
HA#12
HA#13
HA#14
HA#15
HA#16
HA#17
HA#18
HA#19
HA#20
HA#21
HA#22
HA#23
HA#24
HA#25
HA#26
HA#27
HA#28
HA#29
HA#30
HA#31
HA#[31:3] 6
B79
A79
A80
B78
B120
A120
A119
B119
A121
B108
A112
B111
VID0
VID1
VID2
VID3
VID4
RS#0
RS#1
RS#2
VID[4:0]
29
RS#[2:0] 6
B115
B102
B103
A107
A108
B104
HREQ#0
HREQ#1
HREQ#2
HREQ#3
HREQ#4
HREQ#[4:0] 6
HD#53
RP#
HD#54
B114
HD#55
HD#56
THRNDN
HD#57
THRNDP
B15
8.2 K
B14
8.2 K
HD#58
HD#59
HD#60
RESERVED3
HD#61
RESERVED2
HD#62
RESERVED1
HD#63
RESERVED0
B12
A116
A88
A47
REV.
1.0
SC242 CONNECTOR: PART1
intel
A

Folsom, Ca. 95630
Last Revision Date:

Sheet:
2/22/99
of
33
SLOT 1
VCC2_5
VCC3_3
ITP Test Port Option
VCC2_5
VTT1_5
R182A
220
VTT1_5
1
27
28
A27
29
30
B26
A28
B27
A29
A31
B28
B19
A21
A23
B24
A24
A19
5 CPUHCLK
12,32 APICD1
B22
5 APICCLK_CPU
B18
A75
5 CPUHCLK
A12
B74
B101
B121
FLUSH#
DEP#4
DEP#5
BREQ0#
DEP#6
BREQ1#
DEP#7
BSEL0
BP2#
BSEL1
BP3#
BPM0#
BPM1#
BINIT#
TESTHI
THMTRP#
A20M#
PICD0
STPCLK#
PICD1
CPUSLP#
PICCLK
SMI#
LINT0
CLK
LINT1
INIT#
PWRGOOD
FERR#
RESET#
IGNNE#
IERR#
SLOTCC#
BERR#
AERR#
B61
EMI_1
2 B100
EMI_2
0
2 B81
EMI_3
0
2
B1
EMI_4
0
2 B41
EMI_5
0
JP19A is a Test Option Only.

A117
B116
A101
BNR#
A103
BPRI#
A104
HTRDY#
A105
DEFER# 6
HLOCK# 6
B106
B107
DRDY#
A109
HITM#
B110
HIT#
DBSY#
HADS#
A111
A115
B2
FLUSH#
A76
B75
B21
VCC3_3
32
1
R193
10
R245
220
FREQSEL 5,8
A14
R_REFCLK 5,8
A13
TESTHI
32
A5
A20M#
12,32
B6
STPCLK# 12,32
B8
B3
CPUSLP# 12,32
SMI#
12,32
A17
INTR
12,32
B16
B4
NMI
INIT#
12
12,14,32
A7
FERR#
12,32
A8
IGNNE#
12,32
A15
A4
A77
B118
RES0
RES1
RES2
RES3
A16
B20
B112
A113
GND24
A102
GND25
A106
GND26
A110
GND27
A114
GND28
A118
GND29
B76
A98
GND22
GND23
A94
A90
GND20
GND19
GND21
A86
A82
A78
GND17
GND18
A74
A70
GND15
GND14
GND16
A66
A62
A58
GND12
GND13
A54
A50
GND11
A46
GND10
RES4
GND9
18PF
R195
1
R197
1
R198
1
R199
1
R200
1
B117
HADS#
DEP#3
4N937
VCC3_3
DBSY#
DEP#2
GND0
R196
2
C339A
Place site w / in 0.5"

of clock pin (W37)
680
B113
HIT#
DEP#1
A2
Do not stuff C339A
VCC3_2
VCC5
HITM#
DEP#0
1K
VCC3_1
B109
B105
B93
B89
B85
B77
B73
B69
B65
B57
B53
B49
B45
B37
B33
B29
B25
B17
B97
VCCP18
VCCP17
VCCP16
VCCP15
VCCP14
VCCP13
VCCP12
VCCP11
VCCP10
VCCP9
VCCP8
VCCP7
VCCP6
VCCP5
VCCP4
VCCP3
B13
VCCP1
VCCP2
B9
B5
DRDY#
VCC2_5
31 PWRGOOD
6 CPURST#
LOCK#
PRDY#
2
JP19A
A25
DEFER#
PREQ#
SLOT1_B
240
A3
A1
B23
A42
26
A20
A38
24
25
47
ITPREQ#
R192A
TRDY#
GND8
23
R_ITPRDY#
BPRI#
TMS
GND7
22
TCK
A34
20
21
B10
BNR#
GND6
18
19
47 TMS
AP1#
TRST#
GND5
17
R191A
R_TMS
AP0#
TDO
A30
16
B7
A26
15
TCK
GND4
14
B11
R190A
A22
13
A11
TRST#
R_TCK
TDI
A18
12
VTT4
10
VTT3
9
11
A9
TDI
TDO
VTT2
1
8
GND2
ITPCLK
GND1
A10
ITP_PON
1K
VTT1
R_DBRST#
0K
R_TMS
VCC3_3
1
J20B
R189A
1k
A6
R_TCK
31 DBRESET#
ITP_RST
R244
330
1K
ITP30RA
R188A
240
6 CPURST#
R243
VCCP19
150
2
R185A
150
J27A
VCC5
VCCVID
4N642
R184A
1K
VTT1_5
Part 2
4N101
REV.
SC242 Connector: Part 2
intel
A

Folsom, Ca. 95630
1.0
Last Revision Date:

Sheet:
6/14/99
of
33
Clock Synthesizer
VCC3_3
L21A
1
USBV3
22UF
VCC3_3
1
+
C341A
C340A
0.1UF
VCC3_3
L23A
- Place all decoupling caps as close to VCC/GND pins as possible

- PCI_0/ICH pin has to go to the ICH.
(This clock cannot be turned off through SMBus)
- CPU_ITP pin must go to the ITP. It is the only
CPU CLK that can be shut off through the SMBUS interface.
22UF
C344A
C348A
C349A
C350A
C351A
C352A
C342A
C353A
C354A
C343A
0.1UF
.001UF
0.1UF
.001UF
.1UF
.001UF
.001UF
.1UF
.001UF
1
+
C347A
MEMV3
PCIV3
C345A
0.1UF
C346A
.001UF
0.1UF
C355A
22UF
1
+
Notes:
L22A
1
R201A
14.318MHZ
12PF
R212A
7 GMCH_3V66
22
A
3V66_0
223V66_1
R215A
11
PCI_0
12 PCLK_0/ICH
15 PCLK_1
R217A
16 PCLK_2
33
R221A
16 PCLK_3
33
R225A
17 PCLK_4
26 PCLK_5
33
14 PCLK_6
33PCI_1
R219A
38
33
27
21
44
VDD3_3[7]
VDD3_3[6]
VDD3_3[5]
VDD3_3[4]
VDD3_3[3]
VDD3_3[2]
REF
CPU_0
XTAL_OUT
CPU
REF0
12
13
PCI_2
33
PCI_3
R223A
PCI_3
15
PCI_4
16
33
R226A
PCI_5
18
PCI_6
19
33
R228A
13 USBCLK
8 DOTCLK
R229A
CPU_1
CPU_2/ITP
20
3V66_0
3V66_1
SDRAM_0
3V66
SDRAM_1
CK810e
PCI_0/ICH
SDRAM_2
SDRAM_3
SDRAM_4
PCI_1
SDRAM_5
PCI_2
PCI_3
PCI
Memory
33
SDRAM_6
SDRAM_7
PCI_4
PCI_6
DCLK
USB_0
25
USB_1
26
USB_0
USB_1
SCLK
USB
SDATA
SEL1
APICCLK_CPU 4
R204A
33
APICCLK_ICH 12
33
52
CPU_0_1
R206A
CPU_2
33
R209A
50
49
CPUHCLK 4
R207A
GMCHHCLK 6
33
45
DRAM_1
43
DRAM_2
42
DRAM_3
40
DRAM_4
39
DRAM_5
37
DRAM_6
36
DRAM_7
R213A
ITPCLK
22
R216A
22
R220A
22
R224A
34
R211A
MEMCLK0
22
R214A
MEMCLK1
22
R218A
MEMCLK3
22
R222A
MEMCLK5
22
MEMCLK7
MEMCLK[7:0] 10,11
MEMCLK2
A
MEMCLK4
MEMCLK6
R227A
DCLK
DCLK_WR 7
VCC2_5
32
CK_PWRDN# 31
31
30
29
CK_SMBCLK 24
CK_SMBDATA 24
28
L25A
FREQSEL 4,8
VSS3_3[7]
VSS2_5[1]
VSS2_5[0]
51
L_VCC2_5
53
56
48
C360A
C361A
C362A
.001UF
0.1UF
4.7UF
47
VSS3_3[5]
VSS3_3[6]
41
35
VSS3_3[3]
VSS3_3[4]
24
17
VSS3_3[1]
VSS3_3[2]
14
VSS_A
VSS3_3[0]
VDD2_5[1]
Minimize Stub Length from

CLK14 trace to
JP20A.
DRAM_0
VDD_A
VDD2_5[0]
23
46
22
C359A
R203A
22
PWRDWN#
SEL0
.001UF
APIC_1
PCI_7
L_CKVDDA
0.1UF
APIC_0
54
22
22
C358A
55
PCI_5
L24A
APIC_1
33
R210A
13 ICH_3V66
APIC_0
1
+
10
APIC
REFCLK
XTAL_IN
SEL1 _PU
C357A
XTAL_IN
X T AL_OUT
10
R208A
VCC3_3
Y3A
XTAL
R205A
15 SIO_CLK14
13 ICH_CLK14
VDD3_3[0]
12PF
2
10K
4,8 R_REFCLK
VDD3_3[1]
C356A
10
8.2K
U17A
JP20A
JP1
APIC Clk StrapJP20A

16 MHz
in
33 MHz
out
R230A
10K
REV.
1.0
Clock Synthesizer
intel
A

Folsom, Ca. 95630
Last Revision Date:

Sheet:
6/14/99
of
33
82810E, PART 1: HOST INTERFACE

VCC1_8
12,14,15,16,17,18,23,26 PCIRST#
M2
4 CPURST#
AB4
4 HLOCK#
P5
4 DEFER#
R3
HADS#
N3
BNR#
T3
BPRI#
T1
DBSY#
M4
DRDY#
N1
HIT#
P1
4
4
HITM#
HTRDY#
R1
3 HA#[31:3]
HA#4
U1
HA#5
V4
HA#6
V1
HA#7
T4
HA#8
U2
HA#9
U3
HA#10
W1
HA#11
U4
HA#12
W3
HA#13
W4
HA#14
T5
HA#15
W2
HA#16
V2
HA#17
AC2
HA#18
AA2
HA#19
Y3
HA#20
AB3
HA#21
AA1
HA#22
AB2
HA#23
AC3
HA#24
AA3
HA#25
Y2
HA#26
AB5
HA#27
AC4
HA#28
Y1
HA#29
AC5
HA#30
Y4
HA#31
AB1
HREQ#0
R4
HREQ#1
T2
HREQ#2
P4
HREQ#3
R2
HREQ#4
R5
RS#0
N5
RS#1
P2
RS#2
N2
F8
F10
F14
F16
F17
V7
V8
V9
V10
V14
V15
V16
V17
U18
P6
F7
VCC_CORE[13]
VCC_CORE[12]
VCC_CORE[11]
VCC_CORE[10]
VCC_CORE[9]
VCC_CORE[8]
VCC_CORE[7]
VCC_CORE[6]
VCC_CORE[5]
VCC_CORE[4]
VCC_CORE[3]
VCC_CORE[2]
HD4#
HD9#
HLOCK#
HD10#
DEFER#
HD11#
INTEL 82810E
ADS#
BNR#
HD12#
HD13#
BPRI#
HD14#
PART1
DBSY#
HD15#
DRDY#
HD16#
HIT#
HD17#
HOST INTERFACE
HITM#
HD18#
HTRDY#
HD19#
HD20#
HA3#
HD21#
HA4#
HD22#
HA5#
HD23#
HA6#
HD24#
HA7#
HD25#
HA8#
HD26#
HA9#
HD27#
HA10#
HD28#
HA11#
HD29#
HA12#
HD30#
HA13#
HD31#
HA14#
HD32#
HA15#
HD33#
HA16#
HD34#
HA17#
HD35#
HA18#
HD36#
HA19#
HD37#
HA20#
HD38#
HA21#
HD39#
HA22#
HD40#
HA23#
HD41#
HA24#
HD42#
HA25#
HD43#
HA26#
HD44#
HA27#
HD45#
HA28#
HD46#
HA29#
HD47#
HA30#
HD48#
HA31#
HD49#
HD50#
HREQ0#
HD51#
HREQ1#
HD52#
HREQ2#
HD53#
HREQ3#
HD54#
HREQ4#
HD55#
HD56#
RS0#
HD57#
RS1#
HD58#
RS2#
HD59#
VSS[22]
VSS[21]
VSS[23]
N13
N14
M10
VSS[19]
VSS[20]
M11
M12
VSS[17]
VSS[16]
VSS[18]
M13
M14
L10
VSS[14]
VSS[15]
L11
L12
VSS[12]
VSS[11]
VSS[10]
VSS[9]
VSS[13]
L13
L14
K10
K11
K12
VSS[7]
VSS[6]
VSS[5]
VSS[4]
VSS[3]
VSS[8]
K13
K14
E22
C19
VSS[2]
HD60#
Y19
3 RS#[2:0]
U5
HD3#
HD8#
CPURST#
VSS[0]
3 HREQ#[4:0]
HA#3
HD2#
HD7#
RESETB
Y22
N4
HD1#
HD6#
HTCLK
VSS[1]
.001UF
V6
J22
0.1UF
C364A
5 GMCHHCLK
HD0#
HD5#
N22
C363A
GTLREFB
V18
R232A
150
1%
GTLREFA
VCC_CORE[1]
M5
W13
VCC_CORE[0]
GMCHGTLREF
VCC1_8[2]
VCC1_8[0]
U18A
R231A
75
1%
VCC1_8[1]
B20
VTT1_5
HD61#
HD62#
HD63#
Y5
W5
W8
AA6
AB6
Y6
AA5
AA9
V5
AC7
AB7
AC8
AA7
Y8
W7
AC6
W9
AC9
Y7
AA10
AB8
AC10
AB13
AB10
AB9
AB11
Y10
AB16
AB12
Y11
Y9
AC12
W11
AC11
W12
AA11
AA13
Y13
Y12
AC14
AA15
AC15
Y14
AC13
AA14
AB14
Y17
Y15
AC17
AC16
AA18
AB15
W15
AB18
W17
AA17
W18
W16
AC19
Y16
AB19
Y18
AC18
AB17
HD#0
HD#1
HD#2
HD#3
HD#4
HD#5
HD#6
HD#7
HD#8
HD#9
HD#10
HD#11
HD#12
HD#13
HD#14
HD#15
HD#16
HD#17
HD#18
HD#19
HD#20
HD#21
HD#22
HD#23
HD#24
HD#25
HD#26
HD#27
HD#28
HD#29
HD#30
HD#31
HD#32
HD#33
HD#34
HD#35
HD#36
HD#37
HD#38
HD#39
HD#40
HD#41
HD#42
HD#43
HD#44
HD#45
HD#46
HD#47
HD#48
HD#49
HD#50
HD#51
HD#52
HD#53
HD#54
HD#55
HD#56
HD#57
HD#58
HD#59
HD#60
HD#61
HD#62
HD#63
HD#[63:0] 3
Do not Stuff C365A

C365A
Place site w/in 0.5"
of clock ball (V6)
18PF
REV.
82810E, Part 1: Host Interface
intel
A

Folsom, Ca. 95630
1.0
Last Revision Date:

Sheet:
6/14/99
of
33
82810E, PART 2: SYSTEM MEMORY

AND HUB INTERFACE
VCC1_8
VCC3_3
VCC3_3SBY
SM_MAA4
D7
B8
SM_MAA5
A8
SM_MAA6
B7
SM_MAA7
A7
SM_MAA8
D6
10
SM_MAA9
C6
SM_MAA10
D5
SM_MAA11
A5
SM_MAB#4
SM_MAB#5
B6
A6
SM_MAB#6
B4
SM_MAB#7
A4
SM_DQM0
C10
SM_DQM1
A10
SM_DQM2
B1
SM_DQM3
D1
SM_DQM4
B10
SM_DQM5
D9
SM_DQM6
C1
SM_DQM7
10,11 SM_BS[1:0]
10,11 SM_CS#[3:0]
D2
SM_BS0
C5
SM_BS1
E5
SM_CS#0
C4
SM_CS#1
C3
SM_CS#2
B3
SM_CS#3
C2
10,11 SM_RAS#
D8
10,11 SM_CAS#
A11
10,11 SM_WE#
B11
10,11 SM_CKE[1:0]
R238A
SM_CKE0
A3
SM_CKE1
A2
SCLK
5 DCLK_WR
E6
J18
F18
G21
L21
B2
R18
VCC3_3[15]
VCC3_3[14]
VCC3_3[13]
VCC3_3[12]
VCC3_3[11]
K6
F9
F6
VCC3_3[9]
VCC3_3[8]
F15
G3
SMAA3
SMD8
SMAA7
SMD9
SMAA8
INTEL 82810E
SMAA9
SMAA10
PART 2
SMAB4#
SMAB5#
SMAB6#
SYSTEM MEMORY
SMAB7#
SDQM1
AND
SDQM2
SDQM3
HUB INTERFACE
SDQM5
SDQM6
SDQM7
SCS0#
SMD32
SCS1#
SMD33
SCS2#
SMD34
SCS3#
SMD35
SMD36
SRAS#
SMD37
SCAS#
SMD38
SWE#
SMD39
SMD40
SCKE0
SMD41
SCKE1
SMD42
SCLK
SMD43
HUBREF
D20
HLSTB
12 HLSTB#
D18
HL5
C369A
0.1UF
SMD51
HUB I/F
HL6
SMD52
HL7
SMD53
HL8
SMD54
HL9
SMD55
HL10
SMD56
HUBREF
SMD57
HLSTB
SMD58
HLSTB#
SMD59
HCOMP
SMD60
N12
Place C369A as close

as possible to GMCH
A20
SMD50
VSS[24]
R247
301 1%
C376
0.1 uF
A21
SMD49
HL4
VSS[34]
AA12
VSS[35]
AA16
VSS[36]
W6
VSS[37]
W10
VSS[38]
W14
VSS[39]
V3
VSS[40]
R6
VSS[41]
P3
VSS[42]
M1
VSS[43]
L4
VSS[44]
J2
VSS[45]
A19
SMD48
HL3
AA8
HL10
SMD47
HL2
VSS[33]
C20
SMD46
HL1
VSS[32]
HL9
HL0
AA4
A22
SMD45
AC1
HL8
GHCOMP
12
A18
SMD44
HLCLK
VSS[31]
C18
SMD25
SMD31
VSS[30]
HL6
SMD24
SMD30
P10
B18
SMD22
SMD29
SBS1
VSS[29]
HL5
SMD21
SMD28
P11
B19
SMD20
SMD27
SBS0
P12
HL4
SMD18
SMD26
VSS[28]
A23
SMD17
SMD23
SDQM4
VSS[27]
VCC1_8
R246
301 1%
HUBREF
HL3
HL7
Place HUBREF Generation

Circuit in middle of
GMCH and ICH
B22
SMD15
SMD19
SDQM0
VSS[26]
HL2
SMD14
SMD16
P13
B23
SMD11
SMD13
VSS[25]
HL1
SMD10
SMD12
SMAA11
P14
C21
SMD3
SMD7
SMAA6
N10
12 HL[10:0]
22PF
HL0
SMD2
SMD6
SMAA5
N11
D19
5 GMCH_3V66
SMD1
SMD5
SMAA4
0K
C368A
SMD0
SMD4
10
10,11 SM_DQM[7:0]
VCC3_3[7]
SMAA2
RP34A
11 SM_MAB#[7:4]
VCC3_3[6]
L3
C15
C7
D4
SMAA1
VCC3_3[10]
A9
RP33A
SM_MAA3
VCC3_3[5]
E7
SM_MAA2
VCC3_3[4]
SM_MAA1
SMAA0
VCC3_3[3]
C9
VCC3_3[2]
SM_MAA0
U18B
VCC3_3[1]
10,11 SM_MAA[11:0]
VCC3_3[0]
R233A
40
1%
C11
Place Resistor as Close

as possible to GMCH
SMD61
SMD62
SMD63
E17
SM_MD0
C16
SM_MD1
D15
SM_MD2
D17
SM_MD3
C17
SM_MD4
A17
SM_MD5
A16
SM_MD6
B16
SM_MD7
A15
SM_MD8
C14
SM_MD9
B14
SM_MD10
A14
SM_MD11
D13
SM_MD12
C13
SM_MD13
A13
SM_MD14
A12
SM_MD15
E1
SM_MD16
F2
SM_MD17
G4
SM_MD18
G1
SM_MD19
D3
SM_MD20
H2
SM_MD21
H1
SM_MD22
J4
SM_MD23
J1
SM_MD[63:0] 10,11
SM_MD24
K2
SM_MD25
K1
SM_MD26
K3
SM_MD27
L1
SM_MD28
L2
SM_MD29
M3
SM_MD30
K4
SM_MD31
D16
SM_MD32
E15
SM_MD33
D14
SM_MD34
E14
SM_MD35
E13
SM_MD36
E12
SM_MD37
D12
SM_MD38
B15
SM_MD39
B12
SM_MD40
C12
SM_MD41
D11
SM_MD42
D10
SM_MD43
E10
SM_MD44
E9
SM_MD45
E8
SM_MD46
C8
SM_MD47
F3
SM_MD48
F1
SM_MD49
G2
SM_MD50
H3
SM_MD51
E4
SM_MD52
E3
SM_MD53
F4
SM_MD54
J3
SM_MD55
F5
SM_MD56
G5
SM_MD57
H5
SM_MD58
H4
SM_MD59
H6
SM_MD60
J5
SM_MD61
K5
SM_MD62
L5
SM_MD63
C370A
18PF
REV.
82810E, Part 2: System Memory and Hub
intel
A

Folsom, Ca. 95630
Last Revision Date:

Sheet:
1.0
6/14/99
of
33
82810E, PART 3: DISPLAY CACHE
VCC1_8
VCC1_8
AND VIDEO INTERFACE
*OUT = Normal
System
Bus Freq.
IOQ Depth
N/A
JP23A
VCORE
Detect
N/A
RESVD
JP24A
Reads System
Bus Freq.
IN = IOQ Depth of 1
R20
DC_MD8
R22
DC_MD9
R21
DC_MD10
P23
DC_MD11
P22
DC_MD12
N23
DC_MD13
N21
DC_MD14
N20
DC_MD15
M23
DC_MD16
F23
DC_MD17
E20
DC_MD18
E21
DC_MD19
E23
DC_MD20
D22
DC_MD21
D23
*Out = IOQ Depth of 4
DC_MD22
D21
Detects type of
Processor I/O Buffers
DC_MD23
C22
TBD
R240A
9
DC_CLK
R241A
0K
OCLK_FB
DC_MD24
H21
DC_MD25
H22
DC_MD26
H23
DC_MD27
G20
DC_MD28
G22
DC_MD29
G23
DC_MD30
F21
DC_MD31
F22
R_LTCLK
K22
RCLK
J20
22
R242A
J23
OCLK
33
Place R242A within 0.5"
of the GMCH Ball.
C375A
W22
FTD3
W21
FTD4
V23
1
2
33UF
0.1UF
C373A
FTD[11:0] 23
FTD5
U23
FTD6
U22
FTD7
U21
0.01UF
C372A
AB21
AB23
VCCDA
VCCBA
VCCDACA2
AC20
E19
U6
VCCHA
VCCDACA1
W23
FTD2
FTD8
T23
FTD9
T22
FTD10
T21
FTD11
V19
U20
FTBLNK# 23
SL_STALL 23
V21
FTCLK0
23
V22
FTCLK1
23
V20
FTVSYNC 23
U19
FTHSYNC 23
T19
3VFTSCL 23,24
T20
3VFTSDA 23,24
VIDEO INTERFACE
LMD5
LMD6
LMD7
LMD8
LMD9
LMD10
LMD11
LMD12
LMD13
LMD14
LMD15
LMD16
LMD17
LMD18
DISPLAY CACHE
LMD19
DDCDA
DDCCL
LMD20
LMD21
DCLKREF
LMD22
IWASTE
LMD23
IREF
LMD24
W19
3VDDCDA 24
W20
3VDDCCL 24
AA21
DOTCLK
DOTCLK 5
Y23
AA23
IREFPD
C374A
Do not Stuff C374A
LMD25
VSYNC
GRAPHICS INTERFACE
LMD26
HSYNC
LMD27
RED
LMD28
GREEN
LMD29
BLUE
LMD30
AA20
CRT_VSYNC 24
AB20
CRT_HSYNC 24
AC21
VID_RED 24
AC22
VID_GREEN 24
VID_BLUE 24
AC23
LMD31
R239A
174
1%
LTCLK
18PF
Place site w / in 0.5"

of clock ball (AA21).
Place as close as
Possible to GMCH
and via straight to
VSS plane.
LRCLK
LOCLK
AB22
VSSDACA
IN = Tri-state Mode
DC_MD7
LMD4
AA22
VSSDA
JP22A
IN = XOR Tree
*OUT = Normal
R19
VSS[59]
Tri-state
JP21A
Comment
DC_MD6
FTD1
LMD3
VSS[60]
AA19
VSS[61]
XOR
Jumper
K23
VSSHA
Function
DC_MD5
FTD0
Y20
LMD2
VSS[58]
L22
Y21
Use Surface Mount Caps

placed as close as possible to
power pins with short,
wide direct connections
AND
LMD1
T18
DC_MD26
LTVDA
LMD0
P18
JP24A
L23
K21
LTVCL
LMA11
VSS[57]
DC_MD2
DC_MD3
DC_MD4
LMA10
K18
M21
TVHSYNC
DISPLAY CACHE
LMA9
VSS[56]
DC_MD1
LMA8
VSS[55]
M22
CLKOUT1
TVVSYNC
G18
DC_MD0
LMA7
B21
L19
PART3
LMA6
CLKOUT0
B17
DC_MA11
BLANK#
TVCLKIN/SL_STALL
LMA5
VSS[54]
F19
M20
LTVDATA11
LMA4
VSS[53]
9 DC_MD[31:0]
DC_MD28
G19
DC_MA9
DC_MA10
LMA3
VSS[52]
DC_MD30
LTVDATA10
INTEL 82810E
LMA2
E16
H18
LMA1
B13
DC_MA7
LTVDATA9
E11
H20
LTVDATA8
VSS[51]
H19
DC_MA6
LTVDATA7
LMA0
VSS[50]
DC_MA5
INTERFACE
LWE#
VSS[49]
J21
LTVDATA6
B9
N19
DC_MA4
LTVDATA5
LCAS#
VSS[48]
DC_MA3
DC_MA8
DC_MD29
JP23A
P20
VIDEO DIGITAL OUT
LRAS#
B5
JP22A
DC_MD31
DC_MA2
LTVDATA4
A1
JP21A
P19
LTVDATA3
LDQM3
VSS[47]
1
GRS_PU31
DC_MD13
M19
DC_MA1
LTVDATA2
LDQM2
VSS[46]
J19
DC_MA0
LTVDATA1
LDQM1
E2
K20
9 DC_MA[11:0]
GRS_PU 30
F20
LTVDATA0
LDQM0
G6
C23
DC_DQM3
K19
10K
GRS_PU 26
10K
2
DC_DQM2
9 DC_WE#
RP36A
R23
9 DC_RAS#
9 DC_CAS#
R_REFCLK 4,5
GRS_PU 28
DC_DQM1
LCS#
VSSBA
VCC3_3
P21
J6
FREQSEL 4,5
DC_DQM0
E18
L20
DC_CS#
9 DC_DQM[3:0]
T6
GMCH RESET STRAPS
68NH-0.3A
+
C371A
VCCDACA
U18C
RP35A
L26A
22PF
Do Not Populate C375A
intel
A
REV.
82810E, Part 3 : Display Cache and Video

1.0
Last Revision Date:
6/14/99
Sheet:
Folsom, Ca. 95630
of
8
33
4MB Display
Cache
19
DQ11
DQ12
35
DC_CLK
DC_CKE
34
CLK
DQ13
CKE
DQ14
DQ15
DC_MD9
42
DC_MD10
43
DC_MD11
45
DC_MD12
46
DC_MD13
48
DC_MD14
49
DC_MD15
36
DC_DQM1
14
DC_DQM0
DC_MA10
20
DC_MA11
19
VSS_1
44
38
13
DQ2
A3
DQ3
A4
A5
A6
DQ4
A7
A8
A9
A10
A11
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DC_CLK
35
DC_CKE
34
DQ13
CLK
DQ14
CKE
DQ15
DC_CS#
18
DC_RAS#
17
DC_CAS#
16
DC_WE#
15
37
50
NC_2
VDDQ_4
32
VDDQ_3
DC_MA9
VDDQ_2
31
VDDQ_1
30
DC_MA8
33
NC_1
VSS_2
37
40
DC_MA7
WE#
26
33
LDQM
VSSQ_1
15
UDQM
CAS#
VSSQ_2
8 DC_WE#
RAS#
VSSQ_3
16
47
17
8 DC_CAS#
41
8 DC_RAS#
DC_MD8
CS#
10
18
VSSQ_4
DC_CS#
39
29
25
1
DQ10
DC_MD7
28
DC_MA6
VDD_1
38
44
VDDQ_4
13
A11
DQ9
12
DC_MA5
A2
DC_MD16
DC_MD17
DC_MD18
DC_MD19
DC_MD20
DC_MD21
11
DC_MD22
12
DC_MD23
39
DC_MD24
40
DC_MD25
42
DC_MD26
43
DC_MD27
45
DC_MD28
46
DC_MD29
48
DC_MD30
49
DC_MD31
36
DC_DQM3
14
DC_DQM2
CS#
RAS#
UDQM
CAS#
LDQM
DC_MD[31:0] 8
DC_DQM[3:0] 8
WE#
NC_1
NC_2
VSS_1
DC_MA11
A10
DQ8
DC_MD6
27
VSS_2
20
A9
DQ7
DC_MD5
11
24
DC_MA4
50
DC_MA10
A8
DQ6
DC_MD4
23
DC_MA3
DQ1
26
32
A7
DC_MA2
DQ0
A1
VSSQ_1
DC_MA9
A6
DQ5
DC_MD3
A0
SDRAM
50-PIN TSOP
31
DQ4
A5
DC_MD2
22
VSSQ_2
DC_MA8
A4
21
DC_MA1
VSSQ_3
30
DQ3
DC_MA0
47
DC_MA7
DQ2
A3
DC_MD1
41
29
DQ1
A2
DC_MD0
VSSQ_4
28
DC_MA6
A1
10
27
DC_MA5
DC_MA[11:0]
DQ0
DC_MA4
VDDQ_3
24
A0
VDDQ_2
23
DC_MA3
VDDQ_1
DC_MA2
VDD_2
22
SDRAM
50-PIN TSOP
R1A
4.7K
21
DC_MA1
VDD_1
1
VCC3_3
DC_MA0
25
U1A
U2A
8 DC_MA[11:0]
VCC3_3
VDD_2
VCC3_3
REV.
Display Cache
intel
A

Folsom, Ca. 95630
1.0
Last Revision Date:

Sheet:
6/14/99
of
33
SM_CKE1
SM_CKE0
SM_CS#1
SM_CS#0
SM_DQM7
SAO_PU
164
146
145
135
134
109
108
80
62
61
51
50
48
44
31
25
24
81
167
166
165
147
83
82
63
128
115
111
27
129
45
114
30
131
130
NC17
NC16
NC15
NC14
NC13
NC12
NC11
NC10
NC9
NC8
NC7
NC6
NC5
NC4
NC3
NC2
NC1
WP
SA2
SA1
SA0
REGE
SMBCLK
SMBDATA
CKE1
CKE0
RAS#
CAS#
WE#
S3#
S2#
S1#
S0#
DQMB7
DQMB6
VCC6
SM_DQM6
VCC7
DQMB5
DQMB4
DQMB3
DQMB2
DQMB1
DQMB0
BA1
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
VCC8
113
112
47
46
29
28
39
122
132
126
123
38
121
37
120
36
119
35
118
A2
VCC9
SM_DQM5
SM_DQM4
SM_DQM3
SM_DQM2
SM_DQM1
SM_DQM0
SM_BS1
SM_BS0
SM_MAA11
SM_MAA10
SM_MAA9
SM_MAA8
SM_MAA7
SM_MAA6
SM_MAA5
SM_MAA4
SM_MAA3
J1A
A1
A0
18
34
26
117
40
SM_MAA2
41
SM_MAA1
90
33
102
SM_MAA0
110
CLK3
124
163
49
MEMCLK3
59
CLK2
73
CLK1
84
CLK0
133
79
143
125
157
MEMCLK2
168
VCC17
VSS18
VCC16
VSS17
VCC15
VSS16
VCC14
VSS15
VCC13
VSS14
VCC12
VSS13
VCC11
VSS12
VCC10
VSS11
DIMM SOCKET
168 PIN
ECC7
ECC6
ECC5
ECC4
ECC3
ECC2
ECC1
ECC0
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VCC3_3SBY
MEMCLK1
42
MEMCLK0
SM_MD29
SM_MD30
SM_MD31
SM_MD32
SM_MD33
75
76
77
86
87
SM_MD63
137
136
106
105
53
52
22
21
SM_MD61
SM_MD62
161
SM_MD60
160
SM_MD59
158
159
SM_MD58
156
150
155
SM_MD54
149
SM_MD55
SM_MD53
144
SM_MD57
SM_MD52
142
154
SM_MD51
141
SM_MD56
SM_MD50
140
153
SM_MD49
139
151
SM_MD47
SM_MD48
104
SM_MD44
99
SM_MD46
SM_MD43
98
SM_MD45
SM_MD42
97
103
SM_MD41
95
101
SM_MD40
94
100
SM_MD38
SM_MD39
93
SM_MD37
SM_MD28
74
92
SM_MD27
72
SM_MD34
SM_MD26
71
SM_MD36
SM_MD25
70
SM_MD35
SM_MD24
69
91
SM_MD23
67
89
SM_MD22
66
88
SM_MD19
SM_MD21
65
SM_MD18
SM_MD20
57
60
56
58
SM_MD16
SM_MD17
55
SM_MD13
SM_MD15
20
SM_MD12
SM_MD14
19
16
17
SM_MD9
SM_MD11
15
SM_MD8
SM_MD10
11
14
SM_MD7
10
13
SM_MD5
SM_MD6
9
SM_MD3
8
SM_MD4
4
7
SM_MD2
3
5
SM_MD0
SM_MD1
SYSTEM MEMORY
7,11 SM_MD[63:0]
VSS10
VSS9
VSS8
VCC5
VSS7
VSS6
VCC4
VSS5
VCC3
VSS4
VCC2
VSS3
VCC1
VSS2
VSS1
intel
R
162
152
148
138
127
116
107
96
85
78
68
64
54
43
32
23
12
11
7,11 SM_MAA[11:0]
5,11 MEMCLK[7:0]
7,11 SM_DQM[7:0]
7,11 SM_BS[1:0]
7,11 SM_CS#[3:0]
7,11 SM_WE#
7,11 SM_CAS#
7,11 SM_RAS#
11,13,24,27,32 SMBDATA
11,13,24,27,32 SMBCLK
7,11 SM_CKE[1:0]

Folsom, Ca. 95630
System Memory : DIMM0

Last Revision Date:
REV.
Sheet:
10
6/14/99
1.0
of
33
38
123
SM_MAA10
SM_MAA11
39
28
29
46
47
112
113
130
131
SM_BS1
SM_DQM0
SM_DQM1
SM_DQM2
SM_DQM3
SM_DQM4
SM_DQM5
SM_DQM6
SM_DQM7
5,10 MEMCLK[7:0]
129
SM_CS#3
63
SM_CKE1
intel
R
164
146
145
135
134
109
108
80
62
61
51
50
48
44
31
25
24
81
167
166
165
147
83
82
128
SM_CKE0
115
111
27
45
114
SM_CS#2
NC17
NC16
NC15
NC14
NC13
NC12
NC11
NC10
NC9
NC8
NC7
NC6
NC5
NC4
NC3
NC2
NC1
WP
SA2
SA1
SA0
REGE
SMBCLK
SMBDATA
CKE1
CKE0
RAS#
CAS#
WE#
S3#
S2#
S1#
S0#
VCC6
DQMB7
VCC7
DQMB6
VCC8
DQMB5
DQMB4
DQMB3
DQMB2
DQMB1
DQMB0
BA1
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
VCC9
30
122
SM_BS0
132
126
121
120
SM_MAB#7
SM_MAA9
36
SM_MAB#6
37
119
SM_MAB#5
SM_MAA8
35
SM_MAB#4
118
SM_MAA3
J2A
A1
34
117
18
SM_MAA2
26
SM_MAA1
40
A0
41
33
90
SM_MAA0
102
CLK3
110
163
124
MEMCLK7
49
CLK2
59
CLK1
73
CLK0
84
79
133
125
143
MEMCLK6
157
MEMCLK5
168
42
VCC17
VSS18
VCC16
VSS17
VCC15
VSS16
VCC14
VSS15
VCC13
VSS14
VCC12
VSS13
VCC11
VSS12
VCC10
VSS11
DIMM SOCKET
168 PIN
ECC7
ECC6
ECC5
ECC4
ECC3
ECC2
ECC1
ECC0
DQ63
DQ62
DQ61
DQ60
DQ59
DQ58
DQ57
DQ56
DQ55
DQ54
DQ53
DQ52
DQ51
DQ50
DQ49
DQ48
DQ47
DQ46
DQ45
DQ44
DQ43
DQ42
DQ41
DQ40
DQ39
DQ38
DQ37
DQ36
DQ35
DQ34
DQ33
DQ32
DQ31
DQ30
DQ29
DQ28
DQ27
DQ26
DQ25
DQ24
DQ23
DQ22
DQ21
DQ20
DQ19
DQ18
DQ17
DQ16
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
VCC3_3SBY
MEMCLK4
137
136
106
105
53
52
22
21
161
160
159
158
156
155
154
153
151
150
149
144
142
141
140
139
104
103
101
100
99
98
97
95
94
93
92
91
89
88
87
86
77
76
75
74
72
71
70
69
67
66
65
60
58
57
56
55
20
19
17
16
15
14
13
11
10
SM_MD0
SM_MD1
SM_MD2
SM_MD3
SM_MD4
SM_MD5
SM_MD6
SM_MD7
SM_MD8
SM_MD9
SM_MD10
SM_MD11
SM_MD12
SM_MD13
SM_MD14
SM_MD15
SM_MD16
SM_MD17
SM_MD18
SM_MD19
SM_MD20
SM_MD21
SM_MD22
SM_MD23
SM_MD24
SM_MD25
SM_MD26
SM_MD27
SM_MD28
SM_MD29
SM_MD30
SM_MD31
SM_MD32
SM_MD33
SM_MD34
SM_MD35
SM_MD36
SM_MD37
SM_MD38
SM_MD39
SM_MD40
SM_MD41
SM_MD42
SM_MD43
SM_MD44
SM_MD45
SM_MD46
SM_MD47
SM_MD48
SM_MD49
SM_MD50
SM_MD51
SM_MD52
SM_MD53
SM_MD54
SM_MD55
SM_MD56
SM_MD57
SM_MD58
SM_MD59
SM_MD60
SM_MD61
SM_MD62
SM_MD63
SYSTEM MEMORY
7,10 SM_MD[63:0]
VSS10
VSS9
VSS8
VSS7
VCC5
VSS6
VCC4
VSS5
VCC3
VSS4
VCC2
VSS3
VCC1
VSS2
VSS1
162
152
148
138
127
116
107
96
85
78
68
64
54
43
32
23
12
R2A
VCC3_3SBY
SAO_PU
SAO_PU 10
2.2K
7,10 SM_MAA[11:0]
7 SM_MAB#[7:4]
7,10 SM_DQM[7:0]
7,10 SM_BS[1:0]
7,10 SM_CS#[3:0]
7,10 SM_CAS#
7,10 SM_RAS#
7,10 SM_WE#
10,13,24,27,32 SMBDATA
10,13,24,27,32 SMBCLK
7,10 SM_CKE[1:0]

Folsom, Ca. 95630
System Memory : DIMM1

Last Revision Date:
REV.
Sheet:
11
6/14/99
1.0
of
33
AD6
E1
AD7
E2
AD8
D1
AD9
D3
AD10
E4
AD11
C2
AD12
C1
AD13
B1
AD14
D4
AD15
C3
AD16
A4
AD17
B4
AD18
C5
AD19
C6
AD20
B5
AD21
E7
AD22
A6
AD23
B6
AD24
D7
AD25
B8
AD26
A7
AD27
16,17,26 C_BE#[3:0]
A8
AD28
B7
AD29
C9
AD30
D8
AD31
C7
C_BE#0
D2
C_BE#1
B2
C_BE#2
A3
C_BE#3
D6
H16
L15
G15
K14
H14
G13
J16
VCC1_8_7
VCC1_8_6
VCC1_8_5
VCC1_8_3
VCC1_8_1
VCC1_8_2
E13
N13
N5
D16
E5
E6
A5
C8
M14
T16
R13
U10
T7
P6
G5
E3
C11
VCC3_3_9
VCC3_3_8
VCC3_3_7
VCC3_3_6
VCC3_3_5
VCC3_3_4
VCC3_3_3
VCC3_3_17
F5
VCC3_3_16
F4
AD5
VCC3_3_15
F3
AD4
VCC3_3_14
AD3
VCC3_3_12
F2
VCC3_3_13
G4
AD2
VCC3_3_11
G2
AD1
VCC3_3_10
AD0
VCC3_3_2
VCC3_3_1
U3A
16,17,26 AD[31:0]
VCC1_8
VCC3_3
VCC1_8_4
ICH, Part 1
AD0
A20M#
AD1
CPUSLP#
AD2
FERR#
AD3
IGNNE#
AD4
INIT#
AD5
INTR
CPU
AD6
NMI
AD7
SMI#
AD8
STPCLK#
AD9
RCIN#
AD10
AD11
AD12
A20GATE
INTEL 82801AA (ICH)
HL0
AD13
HL1
AD14
HL2
AD15
HL3
PART 1
AD16
HL4
HL5
AD17
HUB I/F
AD18
AD19
AD20
AD21
HL6
HL7
HL8
PCI
HL9
HL10
AD22
AD23
HLSTB
AD24
HLSTB#
AD25
HCOMP
AD26
HUBREF
AD28
PIRQ#A
AD29
PIRQ#B
AD30
PIRQ#C
AD31
PIRQ#D
INTERRUPTS
C_BE#0
C_BE#1
IRQ14
IRQ15
C_BE#2
APICCLK
C_BE#3
APICD1
REQ#B/GPIO1
RESV[1]
PC/PCI
RESV[2]
FERR#
B17
IGNNE#
E15
INIT#
4,14,32
INTR
NMI
4,32
4
E14
B16
F14
4,32
4,32
4,32
A17
SMI#
4,32
STPCLK# 4,32
A15
RCIN#
B15
A20GATE 15,32
D17
HL0
E17
HL1
F17
HL2
G16
HL3
J15
HL4
K16
HL5
K17
HL[10:0] 7
VCC1_8
HL6
L17
HL7
H15
HL8
J17
HL9
J14
HL10
R3A
40
1%
G17
H17
M17
15,32
HLSTB
HLSTB#
Place R3A
as close as
possible to ICH.
IHCOMP_PU
J13
HUBREF 7
D10
PIRQ#A
16,17,26,32
A10
PIRQ#B
16,17,32
B10
PIRQ#C
16,17,32
C10
PIRQ#D
16,17,32
P11
IRQ14
18,32
N14
C17
IRQ15
18,32
APICCLK_ICH 5
APICD1 4,32
E16
APICD0
R4
SERIRQ
C16
C1A
Place C1A as close
as possible to ICH.
0.1UF
32
15,17,32
VSS13
VSS12
VSS11
A14
PREQ#0
16,32
B13
PREQ#1
16,32
B12
PREQ#2
17,32
D12
PREQ#3
26,32
A13
PGNT#0
C13
A12
C12
A11
16,32
17,32
26,32
RESV1PU
F16
RESV2PD
VCC3_3
R4A
RESV0PU
B11
16,32
PGNT#1
PGNT#2
PGNT#3
R5A
8.2K
8.2K
R6A
0K
For Test/Debug
Don't Stuff R6A
K15
G14
K10
VSS10
VSS9
GNT#B/GPIO17
J10
R5
RESV[0]
REQ#A/GPIO0
GNT#A/GPIO16
H10
P4
GNT#3
PME#
VSS8
P5
SERR#
VSS7
32 REQ#B/GPIO1
32 GNT#B/GPIO17
N6
GNT#0
GNT#2
K9
17,32 PCPCI_REQ#A
17 PCPCI_GNT#A
REQ#3
GNT#1
PAR
VSS6
K1
A1
PLOCK#
J9
16,17,26 PCI_PME#
PCI
PCIRST#
H9
A9
STOP#
VSS5
B9
16,17,26 PAR
16,17,26,32 SERR#
REQ#2
VSS4
16,17,32 PLOCK#
J5
REQ#1
K8
16,17,26,32 STOP#
6,14,15,16,17,18,23,26 PCIRST#
IRDY#
TRDY#
J8
A2
D5
VSS3
C4
REQ#0
VSS2
16,17,26,32 IRDY#
16,17,26,32 TRDY#
DEVSEL#
H8
D9
SERIRQ
PCICLK
VSS1
16,17,26,32 DEVSEL#
CPUSLP# 4,32
F15
FRAME#
G3
B3
R2
5 PCLK_0/ICH
16,17,26,32 FRAME#
A20M#
E12
AD27
APICD0
C14
F13
REV.
1.0
ICH, Part 1
intel
A

Folsom, Ca. 95630
Last Revision Date:

Sheet:
12
6/14/99
of
33
ICH
VCC3_3
VCC3_3SBY
ICH5VREF
A
VRTC
R8
1-2
Normal
2-3
Clear CMOS
JP1A
R11A
VBATC_DLY
C5A
A
2.2UF
R13A
JP24_PD
R12A
1K
VBAT
21 ICH_RI#
L3
27,31 RSMRST#
F1
27 SUS_STAT#
L4
J1
10,11,24,27,32 SMBCLK
J2
32 SMBALERT#
M1
J4
C6A
U6
R14A
32.768KHZ
Socketed
3vdc Lithium
equivalent to
Rayovac BR2325
C8A
18pF
C7A
18pF
U2
5 ICH_3V66
A16
VBIAS
H2
RTCX1
H3
RTCX2
H4
RTCRST#
R15A
10M
5 USBCLK
Speaker
No Reboot on 2nd watchdog timeout
Reboot on 2nd watchdog timeout
H1
25 AC_RST#
T1
25 AC_SYNC
T3
25 AC_BITCLK
25 AC_SDOUT
R3
25,32 AC_SDIN0
U1
25,32 AC_SDIN1
P3
30 ICH_SPKR
U3
15,32 LPC_SMI#
D11
T2
15,32 LPC_PME#
E11
17,32 GPIO7
E9
32 GPIO12
N4
32 GPIO13
L2
17,32 GPIO21
B14
32 GPIO22
D13
30 GPIO23_FPLED
D15
30 GPIO26_FPLED
K4
27 GPIO27
M5
27 GPIO28
L5
14,15 LAD0/FWH0
R6
14,15 LAD1/FWH1
U5
14,15 LAD2/FWH2
T5
14,15 LAD3/FWH3
T4
14,15 LFRAME#/FWH4
U4
15 LDRQ#0
T6
32 LDRQ#1
N3
THRM#
R1
IN
Force CPU freq. strap to safe mode (1111)
OUT
Use CPU freq. strap setting in ICH register.
19 USBP1N
P2
19 USBP0P
P1
19 USBP0N
N2
M4
VCC3_3
JP2A
19
M3
OC#0
C15
PDCS#1
PWROK
SDCS#1
PWRBTN#
PDCS#3
RI#
SDCS#3
RSMRST#
SUSSTAT#/GPIO25
PDA0
PDA1
SMBDATA
PDA2
SYSTEM
SMBCLK
SMBALERT#/GPIO11
SDA0
SDA1
SDA2
INTRUDER#/GPIO10
PDDREQ
CLK14
CLK48
SDDREQ
INTEL 82801AA (ICH)
CLK66
PDDACK#
SDDACK#
VBIAS
PDIOR#
RTCX1
SDIOR#
PART 2
RTCX2
RTCRST#
PDIOW#
SDIOW#
PIORDY
AC_RST#
SIORDY
AC_SYNC
AC_BITCLK
PDD0
AC97
AC_SDOUT
PDD1
AC_SDIN0
AC_SDIN1/GPIO9
IDE
SPKR
PDD2
PDD3
PDD4
PDD5
GPIO5
PDD6
GPIO6
PDD7
GPIO7
PDD8
GPIO12
PDD9
GPIO13
GPIO
GPIO21
GPIO22
PDD10
PDD11
PDD12
GPIO23
PDD13
GPIO26
PDD14
GPIO27
PDD15
GPIO28
SDD0
LAD0/FWH0
SDD1
LAD1/FWH1
SDD2
LAD2/FWH2
LPC
LAD3/FWH3
LFRAME#/FWH4
SDD3
SDD4
SDD5
LDRQ#0
SDD6
LDRQ#1/GPIO8
SDD7
SDD8
USBP1P
SDD9
USBP1N
USBP0P
USB
USBP0N
SDD10
SDD11
SDD12
OC#1
SDD13
OC#0
SDD14
SDD15
N12
PDCS#1 18
L14
SDCS#1 18
U13
PDCS#3 18
L16
SDCS#3 18
R12
PDA0
T12
PDA1
P12
PDA2
M16
SDA0
M15
SDA1
L13
SDA2
PDA[2:0] 18
SDA[2:0] 18
U11
PDREQ
18
P17
SDREQ
18
U12
PDDACK# 18
M13
SDDACK# 18
R11
PDIOR#
18
N16
SDIOR#
18
T11
PDIOW# 18
N15
SDIOW# 18
N11
PIORDY 18
N17
SIORDY
R10
PDD0
N9
PDD1
R9
PDD2
U9
PDD3
R8
PDD4
U8
PDD5
R7
PDD6
U7
PDD7
P7
PDD8
N7
PDD9
T8
PDD10
P8
PDD11
T9
PDD12
P9
PDD13
T10
PDD14
P10
18
PDD[15:0] 18
PDD15
P15
SDD0
R16
SDD1
T17
SDD2
U16
SDD3
U15
SDD4
R14
SDD5
P13
SDD6
T13
SDD7
U14
SDD8
T14
SDD9
P14
SDD10
T15
SDD11
U17
SDD12
R15
SDD13
R17
SDD14
P16
SDD15
SDD[15:0] 18
C9A
R16A
1K
18PF
JP14_PU
R17A
10K
BAT17
0.1UF
5VREF
L1
SLP_S5
ICH_SPKR
JP13_PD
R7A
1K
CR1A
C3A
1.0UF
SLP_S3/GPIO24
AC_SDOUT
19 USBP1P
N1
G1
M2
5 ICH_CLK14
Y1A
JP3A Strap
30 PWRBTN#
32 INTRUDER#
10M
OUT
J3
R_VBIAS
0.047UF
IN
27,28,31 PWROK
10,11,24,27,32 SMBDATA
1K
JP2A Strap
K3
RTCRST#
8.2K
BAT17
D14
K2
VBATC
CR3A
32 THERM#
28,31 SLP_S3#
JP1A Config.
VCCSUS1
C4A
1.0UF
C2A
U3B
VCCSUS2
10K
1K
SLP_S5#
BAT17
R10A
10K
R9
VCCRTC
CR2A
A
VCC3_3SBY
X1
VCC5
VCC3SBY
PART 2
Minimize Stub Length

to Jumpers
JP3A
REV.
ICH, Part 2
AC_SDOUT
intel
A

Folsom, Ca. 95630
1.0
Last Revision Date:
Sheet:
13
6/14/99
of
33
FirmWare Hub (FWH) Socket

NOTE: This is a Socketed Implementation
VCC3_3
VCC3_3
C10A
C11A
C12A
C13A
0.1UF
0.1UF
0.1UF
0.1UF
Distribute close to each power pin.
VCC3_3
X2A
1
2
3
C15A
0.1UF
5
6
7
8
9
5 PCLK_6
10
R18A
R_VPP
11
0K
12
6,12,15,16,17,18,23,26 PCIRST#
13
14
15
16
VCC3_3
VCC3_3
18 S66DETECT
17
18 P66DETECT
18
19
20
IC_PD
FGPI4_PD
FGPI3_PD
FGPI2_PD
WPROT
R19A
JP4A CONFIG
IN
Unlocked
Default
OUT Locked
JP4A
GNDA
IC
VCCA
NC3
FWH4
NC4
INIT#
NC5
RFU36
NC6
RFU35
FGPI4
RFU34
NC8
RFU33
CLK
RFU32
VCC10
VCC31
VPP
GND30
RST#
GND29
NC13
FWH3
NC14
FWH2
FGPI3
FWH1
FGPI2
FWH0
FGPI1
ID0
FGPI0
ID1
WP#
ID2
TBL#
ID3
39
38
LFRAME#/FWH4 13,15
37
INIT#
4,12,32
36
35
34
33
32
31
30
29
A
28
LAD3/FWH3 13,15
27
LAD2/FWH2 13,15
26
LAD1/FWH1 13,15
25
24
23
22
21
LAD0/FWH0 13,15
FWH_ID0
FWH_ID1
FWH_ID2
FWH_ID3
RP2A
8
R20A
4.7K
0K
RP1A
8.2K
TBLK_LCK
4.7K
0.1UF
NC1
40
C14A
40PIN_TSOP_SKT
RP2A for
Test/Debug
Notes:
VPP and WP# are tied to 3.3v
in this configuration Write Protection is register based
with the exception of the Boot Block.
REV.
1.0
FIRMWARE HUB (FWH)
intel
A

Folsom, Ca. 95630
Last Revision Date:

Sheet:
14
2/22/99
of
33
23
13,14 LAD2/FWH2
22
13,14 LAD1/FWH1
21
13,14 LAD0/FWH0
20
26
27
13,32 LPC_PME#
17
12,17,32 SERIRQ
30
PCLK_1
29
22
KDAT
56
22
KCLK
57
MDAT
MCLK
58
12,32 RCIN#
63
12,32 A20GATE
64
22
22
59
30
IRRX
61
30
IRTX
62
21
RXD#0
84
21
TXD0
85
21
DSR#0
86
21
RTS#0
87
21
CTS#0
88
21
DTR#0
89
21
RI#0
90
21
DCD#0
91
21 RXD#1
95
21
21
TXD1
DSR#1
96
21
RTS#1
98
21
CTS#1
99
21
DTR#1
100
21
RI#1
92
21
97
DCD#1
94
22 DRVDEN#1
22 DRVDEN#0
LAD0
65
53
93
VCC3
VCC2
PD6
LPC I/F
LDRQ#
PD5
LRESET#
PD4
PARALLEL PORT I/F
LPCPD#
PD3
PD2
PME#
SERIRQ
PD1
SIO
PCI_CLK
KDAT
PD0
SLCT#
LPC47B27X
KCLK
MDAT
PE
BUSY
ACK#
KYBD/MSE I/F
MCLK
ERROR#
KBDRST
ALF#
STROBE#
A20GATE
IRRX2/GP34
FAN2/GP32
INFRARED I/F
IRTX2/GP35
FAN1/GP33
FDC_PP/DDRC/GP43
RXD1
DIR#
STEP#
22 WDATA#
10
22 WGATE#
11
22 HDSEL#
12
22 INDEX#
13
22
14
TRK#0
22 WRTPRT#
15
22 RDATA#
16
22 DSKCHG#
4
6
5 SIO_CLK14
19
74
PDR6
73
PDR5
72
PDR4
71
PDR3
70
PDR2
69
PDR1
68
PDR0
PDR[7:0] 20
77
SLCT#
20
78
PE
BUSY
20
20
79
80
81
ACK#
20
ERROR# 20
82
ALF#
83
STROBE# 20
20
54
PWM2
30
55
PWM1
30
SIO_GP43
28
Test/Debug Header
Unused GPIOs
A
J3A
RI1#
DCD1#
RXD2_IRRX
TXD2_IRTX
DSR2#
SERIAL PORT 2
RTS2#
GP60/LED1
CTS2#
GP61/LED2
DTR2#
GP27/IO_SMI#
RI2#
GP30/FAN_TACH2
DCD2#
DRVDEN1
GP25/MIDI_IN
DRVDEN0
GP26/MIDI_OUT
SIO_GP60
48
49
SIO_GP61
50
LPC_SMI# 13,32
51
TACH2
30
52
TACH1
30
46
MIDI_IN
22
47
MIDI_OUT 22
32
J1BUTTON1 22
33
J1BUTTON2 22
34
J2BUTTON1 22
35
J2BUTTON2 22
36
JOY1X
22
37
JOY1Y
22
38
JOY2X
22
39
JOY2Y
22
KEYLOCK# 30
SIO_GP21
MTR0#
DS0#
GP10/J1B1
DIR#
GP11/J1B2
STEP#
GP12/J2B1
WDATA#
GP13/J2B2
FDC I/F
WGATE#
GP14/J1X
HDSEL#
GP15/J1Y
INDEX#
GP16/J2X
TRK0#
GP17/J2Y
WRTPRT#
GP20/P17
RDATA#
GP21/P16
DSKCHG#
GP22/P12
CLOCKS
CLKI32
GP24/SYSOPT
CLOCKI
AVSS
DS#0
22
22
22
PDR7
DTR1#
40
SLCTIN# 20
75
SERIAL PORT 1
CTS1#
GND4
MTR#0
PAR_INIT# 20
67
DSR1#
RTS1#
GP31/FAN_TACH1
22
66
TXD1
76
470PF
PD7
GND3
C23A
LAD1
GND2
C22A
470PF
SLCTIN#
LAD2
GND1
Place 1 0.1UF cap near each power pin
25
LAD3
60
0.1UF
0.1UF
13 LDRQ#0
6,12,14,16,17,18,23,26 PCIRST#
INIT#
LFRAME#
31
VREF pin
24
13,14 LAD3/FWH3
C21A
C20A
0.1UF
C19A
0.1UF
C18A
C17A
0.1UF
2.2UF
1
+
C16A
Place near
13,14 LFRAME#/FWH4
VCC5
SUSSTAT_P
VCC3_3
VCC1
Decoupling
18
VREF
U4A
VTR
44
R21A
4.7K
VCC3_3
VCC5
VCC3_3
Super I/O
41
42
SIO_GP22
43
45
SYSOPT
Pulldown on SYSOPT for IO

address of 0x02E
R22A
4.7K
REV.
Super I/O
intel
A

Folsom, Ca. 95630
1.0
Last Revision Date:
Sheet:
15
6/14/99
of
33
PCI Connector 0
(DEV Ah)
PCI Connector 1
(DEV Bh)
VCC3_3SBY
VCC3_3
VCC5
VCC12VCC5
VCC3_3SBY
VCC3_3
VCC12-
VCC5
VCC5
J5A
VCC3_3
VCC12
PTCK
P CI3_CON
B1
A1
B2
A2
B3
A3
PTMS
17,32
B4
A4
PTDI
17,32
B5
A5
B6
A6
PIRQ#A
12,17,26,32
12,17,32 PIRQ#B
B7
A7
PIRQ#C
12,17,32
12,17,32 PIRQ#D
17 PRSNT#11
B8
A8
B9
A9
B10
A10
B11
A11
B12
A12
B13
A13
B14
A14
B15
A15
B16
A16
B17
A17
B18
A18
B19
A19
AD31
B20
A20
AD29
B21
A21
B22
A22
AD28
AD27
B23
A23
AD26
AD25
B24
A24
B25
A25
AD24
B26
A26
R_AD16
B27
A27
B28
A28
AD22
AD21
B29
A29
AD20
AD19
B30
A30
B31
A31
AD18
B32
A32
AD16
B33
A33
B34
A34
B35
A35
B36
A36
B37
A37
B38
A38
B39
A39
B40
A40
SDONEP1 32
B41
A41
SBOP1
32
B42
A42
B43
A43
PAR
12,17,26
B44
A44
B45
A45
B46
A46
AD13
AD12
B47
A47
AD11
AD10
B48
A48
B49
A49
17
PTCK
17 PRSNT#12
PCLK_2
12,32 PREQ#0
12,17,26 AD[31:0]
12,17,26 C_BE#[3:0]
C_BE#3
AD23
AD17
C_BE#2
12,17,26,32 IRDY#
12,17,26,32 DEVSEL#
12,17,32 PLOCK#
17,26 PERR#
12,17,26,32 SERR#
C_BE#1
AD14
PTRST#
17
PCIRST# 6,12,14,15,17,18,23,26
PGNT#0
AD5
B55
A55
AD4
AD3
B56
A56
B57
A57
A61
A62
A11
B12
A12
B13
A13
B14
A14
B15
A15
B16
A16
B17
A17
B18
A18
B19
A19
AD31
B20
A20
AD29
B21
A21
B22
A22
AD28
AD27
B23
A23
AD26
AD25
B24
A24
B25
A25
AD24
B26
A26
R_AD17
B27
A27
C_BE#3
AD30
B28
A28
AD22
B29
A29
AD20
B30
A30
B31
A31
AD18
B32
A32
AD16
B33
A33
B34
A34
B35
A35
B36
A36
B37
A37
IRDY#
FRAME# 12,17,26,32
DEVSEL#
B38
A38
TRDY#
PLOCK#
B39
A39
PERR#
B40
A40
B41
A41
B42
A42
B43
A43
B44
A44
B45
A45
12,17,26,32
C_BE#1
12,32
AD[31:0]
R23A
AD17
100
AD19
AD17
12,17,26,32
PGNT#1
PCI_PME#
AD21
R24A
12,17,26
PCIRST#
FRAME#
TRDY#
STOP#
SDONEP2 32
SBOP2
32
PAR
AD15
B46
A46
AD13
AD12
B47
A47
AD11
AD10
B48
A48
B49
A49
AD9
key
AD6
A60
A10
B11
C_BE#[3:0]
AD9
A54
B62
B10
AD[31:0]
AD15
A53
B61
A9
AD14
B54
B60
PIRQ#D
B9
12,32 PREQ#1
key
32 PU1_ACK64#
PIRQ#B
SERR#
A52
A59
PTDI
A5
A8
AD[31:0]
STOP#
B53
A58
A4
B5
A7
C_BE#2
B52
B59
PTMS
B4
A6
100
AD7
B58
A3
B8
AD23
AD8
AD1
A2
B3
B7
PCI_PME# 12,17,26
AD16
B2
B6
PCLK_3
12,32
PTRST#
A1
PIRQ#C
17 PRSNT#21
VCC12
PCI3_CON
B1
PIRQ#A
17 PRSNT#22
AD30
J4A
VCC3_3
C_BE#0
12,17,26
B52
A52
AD7
B53
A53
B54
A54
AD6
AD5
B55
A55
AD4
AD3
B56
A56
B57
A57
AD2
B58
A58
AD0
B59
A59
B60
A60
B61
A61
B62
A62
AD1
AD2
32 PU2_ACK64#
AD0
C_BE#0
AD8
PU2_REQ64# 32
PU1_REQ64# 32
REV.
1.0
PCI Connectors 1 and 2
intel
A

Folsom, Ca. 95630
Last Revision Date:

Sheet:
16
6/14/99
of
33
PCI Connector 2
(DEV 6h)
Layout Note: Should be in Slot 0 Position (Outside Edge of Board Furthest from CPU)
VCC3_3
VCC5
VCC12VCC12
PTMS
16,32
B4
A4
PTDI
16,32
B5
A5
B6
A6
PIRQ#C
12,16,32
12,16,32 PIRQ#D
B7
A7
PIRQ#A
12,16,26,32
12,16,32 PIRQ#B
B8
A8
B9
A9
R_GPO21
B10
A10
For Debug Only
B11
A11
B12
A12
B13
A13
B14
A14
B15
A15
B16
A16
B17
A17
B18
A18
B19
A19
AD31
B20
A20
AD29
B21
A21
B22
A22
AD27
B23
A23
AD25
B24
A24
B25
A25
B26
A26
B27
A27
B28
A28
AD22
AD21
B29
A29
AD20
AD19
B30
A30
B31
A31
AD18
B32
A32
AD16
B33
A33
B34
A34
B35
A35
B36
A36
B37
A37
B38
A38
B39
A39
B40
A40
SDONEP3 32
B41
A41
SBOP3
32
B42
A42
B43
A43
PAR
12,16,26
B44
A44
B45
A45
B46
A46
AD13
AD11
For Debug Only
PCLK_4
12,32 PREQ#2
12,16,26 AD[31:0]
12,16,26 C_BE#[3:0]
C_BE#3
AD23
AD17
C_BE#2
12,16,26,32 IRDY#
12,16,26,32 DEVSEL#
12,16,32 PLOCK#
16,26 PERR#
12,16,26,32 SERR#
C_BE#1
AD14
AD12
B47
A47
AD10
B48
A48
B49
A49
VCC3_3SBY
16 PRSNT#21
16 PRSNT#12
R30A
VAUX3
16 PRSNT#11
PCIRST# 6,12,14,15,16,18,23,26
0K
R31A
PGNT#2
PCPCI_REQ#A 12,32
12,32
0K
PCI_PME# 12,16,26
AD30
Do Not Stuff R31A
0.1UF
0K
PCPCI_GNT#A 12
For Debug Only
C29A
R_SERIRQ
12,15,32 SERIRQ
0K
16 PRSNT#22
0.1UF
R29A
PRSNT#32
PRSNT#31
R28A
R_GNT#A
C28A
0K
0.1UF
PRSNT#32
C27A
R27A
13,32 GPIO21
5.6K
0.1UF
PRSNT#31
5.6K
R26A
PTCK
C26A
A2
B3
A3
PTCK
0.1UF
B2
16
16
R25A
PTRST#
PTRST#
C24A
A1
0.1UF
J6A
P CI3_CON
B1
C25A
VCC5
VCC3_3
For Debug Only
AD[31:0]
AD28
AD26
AD24
R_AD22
R32A
AD22
100
FRAME# 12,16,26,32
TRDY#
12,16,26,32
STOP#
12,16,26,32
JP5A
1
PERR#_PU 32
16,26 PERR#
GPIO7
13,32
AD15
JP5A-ICH Compatibility
1-2
ICH0
2-3
ICH
DEFAULT
AD9
key
AD8
B52
A52
AD7
B53
A53
B54
A54
AD6
AD5
B55
A55
AD4
AD3
B56
A56
B57
A57
AD2
B58
A58
AD0
B59
A59
B60
A60
B61
A61
B62
A62
AD1
32 PU3_ACK64#
C_BE#0
12,16,26
PU3_REQ64# 32
REV.
1.0
PCI Connector 2
intel
A

Folsom, Ca. 95630
Last Revision Date:

Sheet:
17
6/14/99
of
33
ULTRA-ATA66 IDE
CONNECTORS
VCC5
VCC5
R33A
1K
PRIMARY
IDE CONN.
SECONDARY
IDE CONN.
R34A
1K
13 SDD[15:0]
13 PDD[15:0]
J8A
J7A
1
PDD7
PDD8
PCIRST_BUF#
R36A
33
R_RSTS#
SDD7
SDD6
SDD10
SDD11
PDD6
PDD9
PDD5
PDD10
SDD5
SDD4
SDD9
PDD4
10
PDD11
10
PDD3
11
12
PDD12
SDD3
11
12
SDD12
PDD2
13
14
PDD13
SDD2
13
14
SDD13
PDD1
15
16
PDD14
SDD1
15
16
SDD14
PDD0
17
18
PDD15
SDD0
17
18
SDD15
19
20
13 PDREQ
21
22
13 PDIOW#
23
24
13 PDIOR#
25
26
13 PIORDY
27
28
29
30
13 PDDACK#
12,32 IRQ14
31
32
PDA1
33
34
PDA0
35
36
13 PDCS#1
37
38
30 IDEACTP#
39
40
For Host side 80-conductor Cable Detection:

Populate R37A and R40A, Depopulate C31A
For Drive side 80-conductor Cable Detection:
Populate C31A, Depopulate R37A and R40A
PRI_PD1
19
20
13 SDREQ
21
22
13 SDIOW#
23
24
13 SDIOR#
25
26
13 SIORDY
27
28
29
30
13 SDDACK#
R_P66DET
P66DETECT 14
0K
PDCS#3 13
34
SDA0
35
36
37
38
39
40
13 SDCS#1
30 IDEACTS#
R_S66DET
R38A
S66DETECT 14
0K
SDCS#3 13
C30A
R43A
470
5.6K
0.047UF
15K
R39A
0.047UF
R41A
R46A
C31A
13 SDA[2:0]
R40A
470
10K
15K
VCC3_3
14
VCC3_3
6,12,14,15,16,17,23,26 PCIRST#
R47A
8.2K
VCC
A O
GND
U5A
PCIRST_BUF#
SN74LVC07A
R44A
5.6K
32
33
For Host side 80-conductor Cable Detection:

Populate R38A and R39A, Depopulate C30A
For Drive side 80-conductor Cable Detection:
Populate C30A, Depopulate R38A and R39A
PRI_SD1
SDA2
R45A
13 PDA[2:0]
31
SDA1
12,32 IRQ15
R37A
PDA2
A
SDD8
R42A
33
R_RSTP#
10K
PCIRST_BUF#
R35A
REV.
1.0
ULTRAATA/66 IDE CONNECTORS
intel
A

Folsom, Ca. 95630
Last Revision Date:

Sheet:
18
6/14/99
of
33
USB Connectors
VCC3_3
VCC5
R48A
25 AC97_USB-
POLYSWITCH RUSB250
0K
F1A
R49A
2.5A
25 AC97_USB+
L1A
USBV5
C33A
0.1UF
1
2
R51A
470K
68UF
C32A
1
+
R52A
Place R53A, R55A, C35A, and C36A

within 1" of ICH
0K
Do Not Stuff
13
R54A
R_USBP0N
13 USBP0N
OC#0
15
C34A
0K
R55A
R56A
R_USBP0P
13 USBP0P
R57A
560K
USBD0N
USBD0P
0K
15
USBG0
R58A
C35A
C36A
47PF
47PF
15K
R59A
15K
C37A
L2A
470PF
J9A
USB-CON2
.001UF
USBV0
R53A
25 AC97_OC#
Do Not Stuff 0K
R50A
A
330K
1
2
3
4
C38A
6
7
8
15
R61A
13 USBP1P
15
DATA0+
GND
9
12
GND0
47PF
R63A
15K
11
GND1
GND
10
47PF
C41A
C40A
GND
DATA1+
Place CAPs as close as

possible to connector for
EMI.
USBG1
R62A
15K
DATA1-
C45A
47PF
VCC1
C46A
L4A
470PF
1
C44A
C43A
USBD1P
47PF
USBD1N
13 USBP1N
47PF
USBV1
R60A
47PF
Place R60A, R61A, C44A, and C45A

within 1" of ICH0
C42A
0.1UF
68UF
C39A
GND
DATA0-
2 - USB Stacked
L3A
1
A
VCC0
REV.
USB Connectors
intel
A

Folsom, Ca. 95630
1.0
Last Revision Date:

Sheet:
19
6/14/99
of
33
Parallel Port Header
VCC5
CR4A
A
PARV5
5
4
2.2K
2.2K
RP6A
2.2K
RP5A
2.2K
1
RP4A
RP3A
2.2K
R64A
1N4148
15 ERROR#
1
R_SLCTIN#
R_PARINIT#
15
ALF#
15 STROBE#
R_ALF#
R_STROBE#
15 PDR[7:0]
33
RP8A
PDR0
R_PDR0
PDR1
R_PDR1
PDR2
R_PDR2
PDR3
R_PDR3
PDR4
PDR5
33
RP9A
J10A
4
10
11
12
R_PDR5
13
14
15
16
17
18
19
20
21
22
23
24
25
26
PDR6
R_PDR6
PDR7
R_PDR7
ACK#
C54A
180PF
C55A
180PF
C63A
180PF
180PF
C53A
180PF
C62A
180PF
C61A
180PF
C52A
180PF
180PF
C59A
C51A
C50A
180PF
180PF
180PF
C58A
C60A
C49A
180PF
180PF
180PF
C57A
SLCT#
C48A
PE
15
180PF
15
C47A
BUSY
180PF
15
R_PDR4
33
15
C56A
RP7A
15 SLCTIN#
15 PAR_INIT#
NOTE: J10A is pinned out for IDC (Flow

Through) ribbon cable connector.
REV.
Parallel Port Header
intel
A

Folsom, Ca. 95630
1.0
Last Revision Date:

Sheet:
20
6/14/99
of
33
Serial Port/COM Headers

VCC12VCC12
VCC5
COM1 HEADER
U6A
12
11
RA3
DA2
DY2
RY4
RA4
GND
VCC-12
TXD#0_C
CTS#0_C
RTS#0_C
10
RI#0_C
J11A
10
C64A
VCC3_3SBY
C68A
R65A
10K
C71A
RI#0
RY3
DTR#0_C
COM1 and COM2 are 2x5 pin

Headers for a cabled port.
Place Close to Header

100PF
RTS#0
15
DY1
DSR#0_C
C67A
15
13
DA1
RXD#0_C
100PF
14
DY0
DCD#0_C
C70A
CTS#0
DA0
100PF
15
RA2
C66A
15
RA1
100PF
TXD0
16
RA0
RY2
C69A
15
17
VCC12
RY1
100PF
DSR#0
DTR#0
VCC
RY0
C65A
15
15
18
100PF
DCD#0
RXD#0
100PF
19
15
15
GD75232
100PF
20
do not stuff CR5A and Q1A.
CR5A
R66A
G
RI#_CR_C
ICHRI#_C
R67A
47K
NOTE: J11A and J12A are pinned out

for IDC (Flow Through) ribbon cable
connector.
47K
C72A
Serial Modem is not supported
Q1A
NOTE: If Wake from S3 on
2N70 02LT1
13 ICH_RI#
1.0UF
BAT54C
2nd COM Header Option
VCC12VCC12
If not populated at all, remove BAT54C

and short RI#0_C to RI#CR
VCC5
COM2 HEADER
U7A
RI#1
12
11
RA3
DA2
DY2
RY4
RA4
GND
VCC-12
TXD#1_C
CTS#1_C
RTS#1_C
10
RI#1_C
10
C80A
15
RY3
J12A
Place Close to Header

100PF
13
C76A
RTS#1
DY1
DTR#1_C
100PF
CTS#1
15
DY0
DSR#1_C
C79A
15
14
DA0
DA1
RXD#1_C
100PF
15
RA2
C75A
TXD1
RY2
DCD#1_C
100PF
15
16
C78A
17
RA1
100PF
DSR#1
DTR#1
RA0
RY1
C74A
15
15
RY0
100PF
18
C77A
19
RXD#1
100PF
DCD#1
VCC12
C73A
15
15
GD75232
VCC
100PF
20
REV.
1.0
Serial Port/ COM Headers
intel
A

Folsom, Ca. 95630
Last Revision Date:

Sheet:
21
6/14/99
of
33
KEYBOARD/MOUSE PORTS
FLOPPY DISK HEADER
VCC5
L5A
F2A
1
PS2V5_F
1.25A
VCC5
RP10A
PS2V5
RP11A
4.7K
STACKED PS2 CONNECTOR
4
J13A
1
KDAT
L_KDAT
1
2
3
L7A
15
KCLK
L_KCLK
R68A
1K
PS/2 Kybd
15
1K
L6A
J14A
2
10
16
12
11
15
14
13
14
16
15
13
DIR#
STEP#
18
17
20
19
15 WDATA#
22
21
15 WGATE#
24
23
15 TRK#0
15 WRTPRT#
26
25
28
27
15 RDATA#
30
29
15 HDSEL#
32
31
15 DSKCHG#
34
33
15 DRVDEN#0
L8A
15
15 DRVDEN#1
MDAT
L_MDAT
15 INDEX#
PS/2 Mse
8
9
L9A
15
10
MCLK
L_MCLK
11
15
15
0.1UF
C81A
15
15
L10A
PS2_PD
C84A
C85A
470PF
470PF
470PF
470PF C83A
C82A
12
PS2GND
17
DS#0
L11A
MTR#0
GAME PORT HEADER

RP12A
R_JOY1X
15
JOY1Y
15
JOY2Y
15
R_JOY2X
JOY2X
15
11
13
15
10
12
14
16
0.01UF
3
4
0.01UF
1
2
VCC5
0.01UF
2.2K
0.01UF
NOTE: J15A is pinned out for IDC (Flow

Through) ribbon cable connector.
C88A
JOY1X
R_JOY2Y
C89A
C87A
R_JOY1Y
C86A
VCC5
J15A
VCC5
RP13A
R70A
4.7K
1K
R69A
4.7K
J1BUTTON1 15
J1BUTTON2 15
J2BUTTON2 15
C93A
C92A
C91A
C90A
47PF
47PF
47PF
R_MIDIIN
47PF
47
470PF
47
C95A
15 MIDI_IN
J2BUTTON1 15
470PF
R72A
R_MIDIOUT
C94A
R71A
15 MIDI_OUT
REV.
1.0
KEYBOARD/MOUSE PORTS
intel
A

Folsom, Ca. 95630
Last Revision Date:

Sheet:
6/14/99
22 of
33
Digital Video Out

VCC3_3
VCC3_3
L12A
FPP1V3
C102A
1
+
C101A
10UF
100PF
2
100PF
C99A
FPDV3
100PF C100A
10UF
C98A
100PF
100PF
VCC3_3
C96A
1
1
C97A
L13A
L14A
FPAV3
1K
R74A
400
1%
37
38
39
40
41
42
43
44
45
46
47
8 FTD[11:0]
FTD11
50
FTD10
51
FTD9
52
FTD8
53
FTD7
54
FTD6
55
FTD5
58
FTD4
59
FTD3
60
FTD2
61
FTD1
62
FTD0
63
EXTRS_PU
33
12
VCC0
VCC1
49
18
VCC2
PVCC0
PVCC1
29
23
AVCC0
D23
VREF
36
U8A
AVCC1
0.01UF
1K
Place C106A
near U8A pin 3
100pF
C107A
R76A
C106A
1
+
FTVREF
D22
TXC-
D21
TXC+
D18
TX0-
D17
TX0+
Flat Panel
Transmitter
D15
D14
D13
TX1TX1+
D10
TX2-
D9
TX2+
EXT_RS
D7
D5
DKEN
D4
TEST
D3
BSEL/SCL
D2
DSEL/SDA
D1
ISEL/RST
D0
MSEN
IDCLK+
CTL1/A1/DK1
CTL2/A2/DK2
HS
27
TX1-
24
28
TX1+
24
A
30
TX2-
24
31
TX2+
24
19
35
PCIRST# 6,12,14,15,16,17,18,26
34 TEST_PD
15
3VFTSCL 8,24
14
3VFTSDA 8,24
13
11
SL_STALL 8
10
9
3VHTPLG 24
R77A
A1_PD
8
7
A2_PD
A3_PD
1K
R78A
1K
R80A
R79A
4.7K
1K
16
GND2
GND1
48
PGND
GND0
CTL3/A3/DK3
VS
64
EDGE/CHG
IDCLKDE
17
8 FTVSYNC
24
D6
AGND0
8 FTHSYNC
24
TX0+
D8
AGND1
TX0-
25
D11
20
57
24
D12
AGND2
FTCLK1
24
DFP
D16/PFEN
26
FTCLK0
8 FTBLNK#
24
TXC+
D19
32
8
8
TXC-
22
D20
PD
56
21
FPDV3
C105A
C103A
100PF
R73A
100PF
1
+
C104A
10UF
2
VCC1_8
Do Not Stuff
REV.
Digital Video Out
intel
A

Folsom, Ca. 95630
1.0
Last Revision Date:

Sheet:
23
6/14/99
of
33
Video Connectors
VCC5
VGA Connector
VCC1_8
CR6A
20 Pin Flat Panel Connector
F3A
15
TX0+
23
TXC-
16
TX0-
17
23
R84A
18
19
R248
10
20
30k
R83A
75
1%
VCC1_8
B L M 11B750S
C116A
14
8,23 3VFTSCL
17
5 CK_SMBDATA
18
5 CK_SMBCLK
21
22
1
13
1B5
2A1
2B1
2A2
2B2
2A3
2B3
2A4
2B4
2A5
BEA#
2B5
GND
5VVSYNC
10
5VHTPLG
15
5VFTSDA
16
5VFTSCL
R92A
R93A
0K
3.3PF
C115A
3.3PF
C118A
Do Not Stuff C117A and C118A
BAT54S
C122A
C121A
5VHSYNC
C120A
C119A
5VDDCCL
3.3PF
2
5VDDCDA
23
3.3PF
CR11A
0K
C117A
VCC5
24
19 QSSDA
20 QSSCL
R90A
5VVSYNC
1A5
R89A
4.7K
10PF
8,23 3VFTSDA
1B4
3
BAT54S
10PF
11
1B3
15
A
10PF
23 3VHTPLG
1A3
1A4
10
15
10PF
1B2
L18A
1
8 VID_BLUE
R91A
75
1%
SMBDATA 10,11,13,27,32
SMBCLK 10,11,13,27,32
0K
VCC1_8
CR12A
B L M 11B750S
2
1
2
C124A
8 CRT_VSYNC
1A2
14
3.3PF
8 CRT_HSYNC
L_VSYNC
Do Not Stuff C114A and C115A

A
C123A
0K
3.3PF
8 3VDDCCL
1B1
MON2PU
5VDDCCL
0.1UF
2.2K
VCC
FUSE_5
13
3.3PF
CR9A
2
VCC5
CR10A
QST3384
C113A
C112A
C114A
VCC5
RP14A
L_HSYNC
R88A
5VHSYNC
5V to 3.3V Translation / Isolation
2
8
L_BLUE
5VDDCDA
5VFTSCL
11
12
10
0K
1A1
L_GREEN
B L M11B750S
3.3PF
R85A
75
1%
P o p u l ate if DFP Device

i s also populated.
1
1
L17A
1
8 VID_GREEN
11
7
5VFTSDA
QS4_3V
MONOPU
BAT54S
10UF
CON_FTSCL
CON_FTSDA
De-Bounce
Circuit
C110A
2.2K
0K
R87A
8 3VDDCDA
J17A
L_RED
R86A
U9A
L16A
2
5VHTPLG
R81A
1K
CR8A
0.01UF C111A
2
1
CON_HTPLG
23
Place R66A,R67A,&
R69A Close to VGA
Connector
Protection Circuit
for 20V Tolerance
3.3PF
14
TXC+
C109A
13
1N5821
C108A
CR7A
3.3PF
23
23
C
23
TX2-
TX2+
12
TX1-
CRT5V_F
11
TX1+
23
8 VID_RED
23
R82A
1K
L15A
BAT54S
J16A
2.5A
BLM11B750S is rated at
70Ohms at 100MHz
VCC5
VCC5
12
BAT54S
BEB#
R94A
2.2K
R95A
2.2K
Do Not Populate
REV.
1.0
Video Connectors
intel
A

Folsom, Ca. 95630
Last Revision Date:

Sheet:
24
6/14/99
of
33
AUDIO/MODEM RISER
VCC12
VCC5
VCC5
VCC12-
VCC3_3
VCC3_3SBY
J18A
B1
B2
30 AC97SPKR
B3
B4
B5
B6
B7
B8
B9
B10
B11
AUDIO_MUTE#
B12
B13
B14
B15
B16
13 AC_SDOUT
B17
13 AC_RST#
B18
B19
B20
B21
B22
B23
MONO_PHONE
MONO_OUT/PC_BEEP
RESV[5]
RESV[1]
RESV[6]
RESV[2]
RESV[7]
PRIMARY_DN#
GND[7]
-12V
+5VDUAL/5VSBY
USB_OC
GND[1]
GND[8]
+12V
USB+
GND[2]
+5VD
KEY
AUDIO_PWRDWN
GND[0]
KEY
AC'97_RISER
AMR_CONNECTOR
USB-
KEY
RESV[3]
S/P_DIF_IN
RESV[4]
GND[10]
+3.3VD
+3VDUAL/3VSBY
GND[4]
GND[11]
AC97_SDATA_OUT
AC97_SYNC
GND[12]
AC97_RESET#
AC97_SDATA_IN3
AC97_SDATA_IN1
GND[5]
GND[13]
AC97_SDATA_IN2
AC97_SDATA_IN0
GND[6]
GND[14]
AC97_MSTRCLK
A2
A3
A4
A5
A6
A7
A8
AC97_OC# 19
A9
A10
AC97_USB+ 19
A11
AC97_USB- 19
KEY
GND[9]
GND[3]
A1
AC97_BITCLK
A12
A13
A14
A15
A16
A17
AC_SYNC 13
A18
A19
AC_SDIN1 13,32
A20
A21
AC_SDIN0 13,32
A22
A23
AC_BITCLK 13
REV.
1.0
AUDIO/MODEM RISER
intel
A

Folsom, Ca. 95630
Last Revision Date:
6/14/99
Sheet:
25
of
33
VCC5
VCC3_3SBY
D2
AD20
D3
AD21
C1
AD22
B1
AD23
B2
AD24
B4
Place C131A/C132A
AD25
A5
Close to Ball A10
AD26
B5
AD27
B6
AD28
C6
AD29
C7
AD30
A8
AD31
B8
C_BE#0
M4
L9
L5
L4
K11
K10
K9
K8
K7
K6
K5
K4
J11
J10
J9
L10
VCC[25]
VCC[24]
VCC[23]
VCC[22]
VCC[21]
VCC[20]
VCC[19]
VCC[18]
VCC[17]
VCC[16]
VCC[15]
VCC[14]
VCC[13]
VCC[12]
J8
J7
J6
J5
H8
H7
H6
H5
G6
G5
P2
N6
K3
E1
A7
A3
A11
P12
N8
K13
E12
LILED
AD3
ACTLED
AD4
SPEEDLED
AD5
TDP
AD6
TDN
AD7
RDP
AD8
RDN
AD9
SMBALRT#
AD10
CSTSCHG
AD11
PME#
AD12
FLA0/PCIMODE#
AD13
FLA1/AUXPWR
AD14
FLA2
AD15
FLA3
AD16
FLA4
AD17
FLA5
AD18
FLA6
AD19
FLA7
82559
AD20
AD21
FLA8/IOCHRDY
FLA9/MRST
FLA10/MRING#
AD22
AD23
FLA11/MINT
AD24
FLA12/MCNTSM#
AD25
FLA13/EEDI
AD26
FLA14/EEDO
AD27
FLA15/EESK
AD28
FLA16
AD29
FLD0
AD30
FLD1
AD31
FLD2
12,16,17 C_BE#[3:0]
FLD3
C_BE#1
L3
C_BE#2
F3
C_BE#3
C4
C/BE0#
FLD4
C/BE1#
FLD5
C/BE2#
FLD6
C/BE3#
FLD7
EECS
F2
12,16,17,32 FRAME#
F1
12,16,17,32 IRDY#
12,16,17,32 TRDY#
G3
12,16,17,32 DEVSEL#
H3
12,16,17,32 STOP#
H1
12,16,17 PAR
J1
12,16,17,32 PIRQ#A
H2
16,17 PERR#
J2
A2
12,16,17,32 SERR#
R102A
12,16,17 AD20
R_LANIDS
A4
100
12,32 PREQ#3
C3
J3
12,32 PGNT#3
6,12,14,15,16,17,18,23 PCIRST#
C2
PCLK_5
G1
27 LAN_ISOLATE#
B9
27 LAN_RST#
A9
27 L_SMBCLK
A10
27 L_SMBD
C9
FRAME#
FLCS#
FLOE#
IRDY#
TRDY#
FLWE#
DEVSEL#
CLKRUN#
TEST
STOP#
TEXEC
PAR
TCK
INTA#
PERR#
TI
TO
SERR#
IDSEL
RBIAS10
REQ#
RBIAS100
GNT#
VREF
RST#
NC11
CLK
NC10
NC9
ISOLATE#
NC8
ALTRST#
NC7
NC6
SMBCLK
NC5
SMBD
NC4
NC3
G2
VIO
NC2
VIO
B11
LILED
27
ACTLED
27
SPEEDLED 27
TDP
27
C13
C14
E13
E14
TDN
27
RDP
27
RDN
27
B10
C5
A6
PCI_PME# 12,16,17
J13
J12 LANAPWR
R97A
3K
K14
L14
L13
L12
M14
M13
N14
VCC3_3SBY
P13
N13
U11A
M12
M11
93C46
EEDI
EEDO
EESK
P10
N10
M10
P9
3
4
2
1
EEDI
EEDO
NC2
EESK
NC1
EECS
F14
F13
7
6
F12
G12
H14
R98A
H13
FLD5_PD
H12
FLD6_PD
J14
R99A
619
Do Not Stuff
619
EECS
P7
N9
M8
M9
C8
LANCLKRUN
A13 LAN_TEST
R100A
62K
R101A
4.7K
D13
D14
D12
B12
B14 RBIAS10
B13 RBIAS100
C12
R103A
549
R104A
619
D10
G4
A14
J4
L7
P1
D9
L8
P14
H4
A1
VSS[31]
VSS[30]
VSS[29]
C11
L11
L6
H11
VSS[28]
H10
VSS[27]
H9
VSS[26]
G11
VSS[25]
G10
VSS[24]
G9
VSS[23]
G8
VSS[22]
G7
VSS[21]
F11
VSS[20]
F10
VSS[19]
F9
VSS[18]
F8
VSS[17]
F7
VSS[16]
F6
VSS[15]
F5
VSS[14]
F4
VSS[13]
E11
VSS[12]
E10
VSS[11]
E9
VSS[10]
E8
VSS[9]
E7
VSS[8]
E6
VSS[7]
E5
VSS[6]
E4
VSS[5]
D11
VSS[4]
D8
VSS[2]
VSS[3]
D7
D6
VSS[1]
D5
VSS[0]
D4
VSSPP[5]
N1
VSSPP[4]
M6
VSSPP[2]
VSSPP[3]
K2
E2
VSSPP[0]
VSSPP[1]
B7
B3
VSSPT
C10
VSSPL[2]
VSSPL[1]
VSSPL[3]
N12
VSSPL[0]
0.1UF
G14
C135A
C134A
22PF
22PF
X2
P8
P11
X1
K12
L AN_XTAL2
C133A
25MHZ
N11
Y2A
NC1
L AN_XTAL1
A12
E3
D1
VCC[11]
K1
VCC[10]
AD16
VCC[9]
L2
VCC[8]
L1
AD15
VCC[7]
AD14
VCC[6]
M3
VCC[5]
M2
AD13
VCC[4]
M1
AD12
VCC[3]
AD11
VCC[2]
N2
VCC[1]
N3
AD10
VCC[0]
AD9
VCCPP[5]
P3
VCCPP[4]
N4
AD8
VCCPP[3]
P4
AD7
VCCPP[1]
AD6
VCCPP[0]
M5
VCCPT
AD5
AD2
VCCPL[3]
N5
AD1
VCCPL[2]
AD4
AD0
VCCPL[1]
P5
AD19
4.7UF
C132A
1
+
2
4.7UF
C131A
1
+
AD3
AD18
VCC3_3SBY
P6
AD17
0.1UF
0.1UF
C130A
C129A
0.1UF
C128A
VCC3_3SBY
M7
AD2
VCC
C126A
0.1UF
0.1UF
0.1UF
C125A
C127A
Pins Close to 82559.
N7
AD1
VCC3_3SBY
GND
VCC3_3SBY
AD0
VCC3_3SBY
VCC3_3SBY
LAN Decoupling
Distribute around Power
U10A
VCCPL[0]
12,16,17 AD[31:0]
G13
VCC3_3SBY
R96A
4.7K
5%
VCCPP[2]
LAN
REV.
LAN
intel
A

Folsom, Ca. 95630
1.0
Last Revision Date:
Sheet:
26
6/14/99
of
33
LAN
VCC3_3SBY
VCC3_3SBY
R105A
330
R107A
330
R106A
330
R108A
5
6
JP12_PU
JP8A
RJ-45
330
16
LILED
13
SPEEDLED
14
LILED
26 ACTLED
26 SPEEDLED
RDC
8
TDC
11
RXC_PD
TXC
R115A
75
TXC_PD
RJ45_PD
RJ78_PD
C137A
R114A
75
JP7A
ACTLED
RJ-8
RD_PD
0.1UF
C136A
0.1UF
Do Not Stuff
LI_CR
RJ-7
4
TD_PD
LC2
RJ-5
15
26
LA2
RJ-4
RDC
R113A
50
TDC
R112A
50
RD-
SHLD2
Place Termination near 82559
R111A
50
LC1
RD+
R110A
50
LA1
TD-
JP6A
R109A
RJMAG
18
RDN
RXC
RDP
26
TD+
12
SHLD1
26
10
17
TDP
TDN
JP7_PU
ACT_CR
J19A
26
26
JP11_PU
330
R117A
75
R116A
75
C138A
C139A
0.1UF
0.1UF
VCC3_3SBY
A
Do Not Stuff
R118A
4.7K
RJMAG_CONN
JP9A
C140A
Default Config:
Do Not Stuff
For EST Testing
470PF-1500V
Note: Chassis Ground,

use plane for this signal
10,11,13,24,32 SMBCLK
13 GPIO27
R119A
JP8_SMBC
L_SMBCLK 26
0K
Select JP9A/JP10A
ICH0 1-2 Default
Note: Chassis Ground,
use plane for this signal
ICH 2-3
VCC3_3SBY
R120A
4.7K
JP10A
10,11,13,24,32 SMBDATA
13 GPIO28
R121A
2
R122A
13 SUS_STAT#
JP9_SMBD
L_SMBD 26
0K
0K
LAN_ISOLATE# 26
R123A
13,28,31 PWROK
0K
LAN DISABLE - JP11A
Do Not Stuff R123A
NORMAL
DISABLE
1-2
2-3
Default
JP11A
13,31 RSMRST#
1
2
LAN_RST# 26
REV.
1.0
LAN
Note: This circuit is for debug purpose only.
intel
A

Folsom, Ca. 95630
Last Revision Date:

Sheet:
27
6/14/99
of
33
Voltage Regulators
V3SB
VCC3_3
VCC3_3SBY
1N5822
C144A
1200uF
C143A
NDS356AP
1
2
47UF
47UF
CR13A
C142A
C141A
This generates 3.3V Standby Power which is

on in S0,S1,S3,S4,&S5. It passes 3.3V from
the ATX supply in S0/S1, and 3.3VSB (generated
by VR4 below) in S3/S4/S5.
VCC 3.3V Standby VOLTAGE SWITCH
1200uF
VTT 1.5V VOLTAGE REGULATOR

Q2A
Do Not Populate
VCC12
VCC3_3
NDS356AP
VTT1_5
VR1A
LT1587-1_5
VOUT
3
R124A
4.7K
PLANE_CTL0
V_GQ6
0K
74LS132
SN74LVC07A
C
3
1
2
R126A
MMBT3904LT1
14
PCTL_IN
Q5A
U13A
C146A
1
C147A
1
2
100UF
C145A
5
1.0UF
SI4410DY
13,27,31 PWROK
VCC
14
2
GND
U12A
PLANE_CTL1
R125A
10K
VCC3_3SBY
Q4A
VCC5SBY
13,31 SLP_S3#
ADJ
G
Q3A
VCC5SBY
VIN
100UF
Q6A
SN74LVC07A has 5V input and output tolerance.

A
VCC 3.3VSB Regulator
SI4410DY
VCC 2.5 VOLTAGE REGULATOR
VCC 1.8 VOLTAGE REGULATOR

VCC1_8
VCC2_5
VCC5SBY
VCC3_3
V3SB
VCC5
VR2A
VR4A
VR3A
LT1587ADJ
LT1587ADJ
ADJ
VR5_ADJ
R130A
240
1%
VIN
C148A
1
R128A
240
1%
22UF
Place C153A at the

Regulator
0.1UF
R129A
130
1%
C154A
VR1_ADJ
100UF
1.0UF
ADJ
VOUT
C151A
1
C150A
C149A
1
2
100UF
100UF
C152A
1
2
Place C152A at
the Regulator
VIN
22UF
OUT
IN
C153A
1
GND
VOUT
R127A
301
1%
LT1117-3_3
REV.
Voltage Regulators
intel
A

Folsom, Ca. 95630
1.0
Last Revision Date:

Sheet:
28
6/14/99
of
33
Processor Voltage
Regulator
(VRM 8.4 rev 1.5)
VCC3_3
8
D1
S1
6
D3
D4
D2
S2
S3
SI4410DY
G1
8
D1
S1
D2
S2
D3
C164A
1.0UF
VCCVID
D1
S1
D2
D3
S2
2
S3
5
D4
SI4410DY
G1
D1
S1
D2
S2
0.8UH-20A
Q10A
R140A
8.2K
JP12A
Q9A
JP16A
C163A
1.0UF
L_VCCVID
VFB_PD
SS_PD
JP15A
D4
R138A
20
G2
11
VRCOMP_PD
JP14A
4
R_VCCVID
Place CAPs
Close to FETs
L20A
SI4410DY
VFB
G1
G2
FAULT#_PU
20
D3
IFB
VID4
12
D4
VID3
G1
G1
Q8A
13
The LTC1753 incorporates internal pull-ups on VID[4:0].

If your VR IC does not incorporate these, they must
go on the motherboard.
VID2
LTC1753
C168A
C165A
2700UF
C174A
1
+
2
C173A
1
2
2700UF
2700UF
1
+
2
C172A
C171A
1
+
2700UF
1
+
2
Do Not Stuff C169A
2700UF
C169A
0.1UF
C170A
220PF
0.1UF
0.01UF
C167A
150PF
VID Override Jumpers
R_VRCOMP
JP13A
C166A
FAULT#
IMAX
S3
14
PWRGD
VID1
SENSE
15
20K
0
VID0
R_VID3
8
1
16
Q7A
SI4410DY
PV12
17
GND
VID4
18
R_VID1
R_VID2
IMAX
VID3
R_VID0
VCC
SGND
SS
VID2
VID1
OUTEN
COMP
VID0
19
OUTEN
10
RP15A
VID[4:0]
PVCC
VR5A
3
R137A
2.7K
0.01UF
S3
C162A
G1
C161A
1.0UF
1200UF +
1
2
1200UF
1200UF +
C160A
1
2
VRM_PWRGD 31
C155A
C159A
1
2
1200UF
C158A
C157A
1
+
2
10UF
C156A
0.1UF
10K
R134A
5.6K
5.1
L19A
1.0UH-6.8A
R133A
220
R135A
5VIN
R136A
VCC5
VCC12
VCC5
Refer to VR supplier for layout guildlines.
REV.
Processor Voltage Regulator (VRM8.4 rev 1.5)
intel
A

Folsom, Ca. 95630
Last Revision Date:

Sheet:
29
1.0
6/14/99
of
33
VCC3_3
SYSTEM
VCC5
No stuff.
For test only
15
0K
16V
1
+
2
R143A
13 PWRBTN#
C177A
1.0UF
10UF
0.1UF
R141A
100K
C176A
No stuff.
For test only
R142A
1M
ICH has internal pullup and debounce on PWRBTN#
C175A
VCC3_3SBY
IRRX
J21A
1
2
15
IRTX
R144A
SW1
VCC3_3
VCC3_3
R_IRTX
82
R145A
INFRARED
4
5
4.7K
KEY
6
7
VCC5
VCC3_3
VCC5
PBTN_IN
POWER SW.
R146A
14
SN74LVC07A
A O
GND
18 IDEACTP#
12
13
IDE_ACTIVE
KEY
14
H.D. LED
15
VCC5
6
A O
16
18
R150A
SN74LVC07A
KEY
17
U5C
POWER LED
KEY
19
PWRLED
20
220
GND
18 IDEACTS#
11
470
FP_PD
R149A
10K
14
U5B
VCC
R148A
10K
VCC
R147A
10K
10
KEY
21
15 KEYLOCK#
KEYLOCK
22
23
24
SPKR_IN
JP17A
C
Q11A
1
2
13 ICH_SPKR
R153A
3
SPKR
SPKR_Q1G
1
2
E
RP16A
FNT_PNL_CONN
SP1A
68
C178A
C179A
C180A
470PF
470PF
1+
SPKR_NEG
0.1UF
POS
NEG
Speaker Circuit
FAN Headers
4.7K
VCC5
2.2K
SPEAKER
26
R_SPKRIN
68
R152A
2N3904
VCC3_3
KEY
25
R151A
25 AC97SPKR
VCC3_3SBY
VCC3_3SBY
VCC12
VCC12
330
TACH2
VCC12
CR15A
13 GPIO23_FPLED
For Debug Only
330
R155A
U13B
VCC3_3SBY
U13C
GP26LED 6
SN74LVC07A
14
5
GP23LED
GPIO26_FPLED 13
7
SN74LVC07A
CR14A
VCC12
Hot-Swapping Memory.
14
4.7K
On-Board LED indicates the

Standby Well is on to prevent
R157A
R156A
V3SBLED
J23A
15 TACH1
VCC3_3SBY
0.1UF
J22A
330
C181A
C182A
0.1UF
15
R154A
VCC3_3SBY
C184A
C183A
0.1UF
J24A
J25A
0.1UF
3
15 PWM1
15
PWM2
REV.
SYSTEM
intel
A

Folsom, Ca. 95630
1.0
Last Revision Date:
Sheet:
30
6/14/99
of
33
SYSTEM
Power Connector and Reset Control
ITP RESET CIRCUIT - FOR DEBUG ONLY
VCC3_3SBY
VCC3_3SBY
Power Good Circuit
R158A
240
4 DBRESET#
SN74LVC08A
VCC5SBY
16
17
18
19
20
PS_0N
5V4
ATX
GND5
GND15
GND16
5V6
GND17
GND7
PW_OK
-5V
5V19
5VSB
5V20
12V
SN74LVC06A has
5V input tolerance
74LVC14A is 5V input
tolerant
2
3
A O
VCC5SBY
4
5
DBRPOK
U12B
74LS132
6
7
ATX_PWOK
8
9
10
Do not stuff
R162A
R163A
0K
0K
DBRPOK_DLY
4
5
C185A
1.0UF
A
B
SN74LVC06A
PWRGOOD 4
VCC3_3SBY
PWROK#
VCC3_3SBY
U16C
R164A
4.7K
VCC
Do not stuff
R161A
330
SN74LVC06A
GND3
GND13
U16A
14
15
3_3V2
R159A
0K
14
14
3_3V1
-12V
VCC
5VPSON
3_3V11
74LVC14A
GND
13
4
SN74LVC06A is 5V output
tolerance
A O
GND
13,28 SLP_S3#
12
ST23
14
11
74LVC14A
J26A
VCC
U16B
R160A
4.7K
VCC2_5
VCC3_3SBY
14
VCC3_3SBY
U15B
3 DBRST
2
7
U15A
14
14
APOK_ST
VCC
VCC12
VCC3_3
VCC12-
VCC5-
GND
VCC5
14
U14A
VCC5SBY
A O
29 VRM_PWRGD
PWROK
R165A
1M
SN74LVC06A
Reset Button
13,27,28
GND
220 Ohm Pull-up to 3.3V is on VRM Sheet
Do Not Stuff
For Debug Only
SW2
1
R166A
RST_PD
C186A
0.01UF
22
JP18A
1
C187A
10UF
Resume Reset Circuitry
Place JP23A near front panal header (J20)
Schmitt Trigger Logic

using a 22msec delay
VCC3_3SBY
VCC3_3SBY
VCC3_3SBY
CLOCK POWERDOWN CONTROL

U15C
R167A
VCC3_3SBY
R168A
CK_PWRDN# 5
V3RSMRST
5
7
14
4
ST69
RSMRST# 13,27
74LVC14A
U14B
6
5
7
DBRPOK
U15D
6
22K
8.2K
14
74LVC14A
14
SLP_S3#
CK_PWRD
SN74LVC08A
R170A
R169A
1M
C188A
1.0UF
0K
Do Not Stuff
For Debug Only
Do not stuff R170A - For debug only.

If R170A is populated, R167A must
be de-populated.
REV.
System Power Connector and Reset Control
intel
A

Folsom, Ca. 95630
1.0
Last Revision Date:

Sheet:
31
6/14/99
of
33
PULL-UP RESISTORS AND UNUSED

GATES
PCI BUS
ICH
CPU
VCC5
RP17A
2
17 PERR#_PU
VCC5
12,16,17,26 SERR#
12,16,17 PLOCK#
RP18A
12,16,17,26 STOP#
12,16,17,26 DEVSEL#
12,16,17,26 TRDY#
12,16,17,26 IRDY#
2.7K
16 SDONEP1
16 SDONEP2
16
16
SBOP1
SBOP2
RP19A
13 SMBALERT#
13 LDRQ#1
13 GPIO12
13 GPIO13
5.6K
12,16,17,26 FRAME#
10
VCC5
9 PULLUP/DOWN
RESISTOR PAK
RP23A
12,16,17 PIRQ#D
12,16,17 PIRQ#C
12,16,17 PIRQ#B
12,16,17,26 PIRQ#A
17 SBOP3
VCC5
16,17 PTDI
16,17 PTMS
12,26 PREQ#3
6
7
12,16 PREQ#1
12,16 PREQ#0
10,11,13,24,27 SMBCLK
13 INTRUDER#
RP25A
16 PU1_ACK64#
16 PU1_REQ64#
16 PU2_ACK64#
16 PU2_REQ64#
RP27A
12,26 PGNT#3
4,12 STPCLK#
4,12 SMI#
4.7K
RP24A
8
7
6
4,12,14 INIT#
4,12 IGNNE#
4,12 A20M#
12 GNT#B/GPIO17
12,15,17 SERIRQ
12,17 PCPCI_REQ#A
13 THERM#
12,15 RCIN#
12,15 A20GATE
RP26A
8
12 REQ#B/GPIO1
150
8.2K
R173A
R174
RP28A
17 PU3_ACK64#
R175A
2.7K
17 PU3_REQ64#
2.7K
8.2K
4,12 FERR#
150
1
4,12 NMI
8.2K
4,12 INTR
13,15 LPC_SMI#
13,17 GPIO7
UNUSED GATES
VCC3_3SBY
VCC3_3SBY
14
14
14
U16D
U15E
U14C
13 GPIO22
13,15 LPC_PME#
13,17 GPIO21
10
10
13
7
U15F
12
12
13
VCC5
11
1
12,18 IRQ14
9
10
A
B
4 FLUSH#
150
4
TESTHI
100K
8
R180A
74LS132
13,25 AC_SDIN0
10K
12
SN74LVC06A
U13F
12
10K
14
SN74LVC07A
13
VCC2_5
R178A
R181A
10
14
For Future Compatibility Upgrade
13,25 AC_SDIN1
13
A
B
VCC
12
11
R179A
14
U16F
U12C
U13E
2
4
12,18 IRQ15
14
8
VCC
GND
U13D
RP31A
8.2K
Y
GND
GND
SN74LVC06A
14
14
U12D
11
74LS132
7
SN74LVC07A
REV.
SN74LVC07A
A O
GND
12
GND
A O
SN74LVC08A
VCC5SBY
U16E
10
VCC
14
VCC
13
13
74LVC14A
SN74LVC07A
U5F
8.2K
U14D
14
VCC
7
VCC
14
10
SN74LVC07A
7
14
SN74LVC06A
GND
A O
A O
74LVC14A
VCC3_3SBY
11
2
4
SN74LVC07A
11
SN74LVC08A
14
VCC
A O
GND
VCC
14
8
U5E
RP30A
VCC3_3SBY
11
9
GND
A O
2
150
8.2K
VCC3_3
2
150
RP29A
U5D
1
2
2.7K
VCC3_3
4,12 CPUSLP#
VCC3_3
9 PULLUP/DOWN
RESISTOR PAK
12,16 PGNT#1
12,17 PGNT#2
150
150
VCC5
10
12,16 PGNT#0
4,12 APICD1
RP21A
10,11,13,24,27 SMBDATA
5.6K
2.7K
150
R172A
RP22A
12,17 PREQ#2
R171A
12 APICD0
4.7K
RP20A
17 SDONEP3
VCC2_5
VCC3_3SBY
PULL-UP RESISTORS AND UNUSED GATES
intel
A

Folsom, Ca. 95630
1.0
Last Revision Date:

Sheet:
32
6/14/99
of
33
DRAM, CHIPSET, and BULK POWER DECOUPLING
VCC3_3
Distribute near the

VCC3_3SBY power pins of
the ICH.
VCC3_3SBY
VCC1_8
C244A
C245A
C246A
C247A
C248A
C249A
C250A
C251A
C252A
C253A
C254A
C255A
C256A
C257A
C258A
C259A
C260A
C261A
C262A
C263A
C264A
C265A
C266A
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.01UF
0.1UF
0.1UF
0.1UF
1
+
Distribute near the

1.8V power pins of
the ICH.
ICH 3.3V Plane Decoupling:

Place 1 .1uF/.01uF pair in each corner,
and 2 on opposite sides close to component
if they fit.
0.1UF
10UF
C243A
0.1UF
C242A
0.1UF
C269A
C241A
0.1UF
C268A
C240A
0.1UF
10UF
C239A
0.1UF
C238A
10UF
C237A
Distribute near the power pins

of both SDRAM components.
VCC3_3
VCC1_8
ICH
Decoupling
C270A
Display Cache Decoupling
C267A
2.2UF
GMCH Decoupling
0.1UF
GMCH Core Plane Decoupling:

Place 1 .1uF/.01uF pair in each corner,
and 2 on opposite sides close to component
if they fit.
VCC1_8
Bulk Power Decoupling
C298A
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C297A
0.1UF
C296A
C295A
C294A
C282A
C281A
22UF
0.1UF
0.1UF
0.1UF
C293A
0.1UF
0.1UF
C279A
0.1UF
C289A
C283A
0.1UF
C288A
1
+
C286A
0.1UF
0.1UF
C285A
VCC12-
0.1UF
0.1UF
C292A
C284A
C291A
VCC12
VCC5-
0.1UF
0.1UF
3 VOLT Decoupling
VCC3_3
C311A
C312A
C313A
C314A
C315A
C316A
C317A
C318A
C319A
C320A
C321A
C322A
C323A
C324A
C325A
C326A
C327A
C328A
C329A
C330A
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
C331A
C338A
0.1UF
C337A
0.1UF
VCC3_3SBY
DIMM1 Decoupling:
Distribute near DIMM1 Power Pins.
C336A
0.1UF
C304A
0.1UF
C310A
0.1UF
C303A
C335A
C309A
0.1UF
C302A
0.1UF
C308A
0.1UF
C301A
C334A
C307A
0.1UF
C300A
0.1UF
C306A
0.1UF
C332A
1
C305A
and 3 near Display Cache Quadrant
22UF
Place 3 near System Memory Quadrant
22UF C333A
VCC3_3
C299A
GMCH 3.3V IO Decoupling:
VCC5
C290A
Distribute near DIMM0 Power Pins.
VCC3_3SBY
22UF
DIMM0 Decoupling:
1
+
VCC3_3
C280A
System Memory Decoupling
0.01UF
22UF
C278A
0.01UF
C277A
0.01UF
22UF
C276A
0.01UF
C275A
0.01UF
C274A
0.01UF
C287A
C273A
1
+
C272A
0.01UF
22UF
C271A
0.01UF
REV.
DRAM, CHIPSET, and BULK POWER DECOUPLING
intel
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Folsom, Ca. 95630
Last Revision Date:

Sheet:
1.0
6/14/99
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INTEL PENTIUM II/PENTIUM III PROCESSOR (SC242) / INTEL

THESE SCHEMATICS ARE PROVIDED "AS IS" WITH NO WARRANTIES

ULTRA-ATA66 IDE Connectors

Serial Port/COM Headers

Kybrd / Mse / F. Disk / Gme Connectors

Digital Video Out

** Please note these schematics are subject to change.

Processor Voltage Regulator (VRM8.4 rev 1.5)

Pullup Resistors and Unused Gates

DRAM, Chipset,and Bulk Power Decoupling

Information in this document is provided in connection with Intel products. No license,

Title: Intel 810e Chipset Customer Reference Board

Platform Components Division

Title: Intel 810e Chipset Customer Reference Board

Platform Components Division

Last Revision Date:

Title: Intel 810e Chipset Customer Reference Board

SC242 CONNECTOR: PART1

Platform Components Division

Last Revision Date:

ITP Test Port Option

JP19A is a Test Option Only.

Place site w / in 0.5"

Do not stuff C339A

Title: Intel 810e Chipset Customer Reference Board

SC242 Connector: Part 2

Platform Components Division

Last Revision Date:

- Place all decoupling caps as close to VCC/GND pins as possible

Minimize Stub Length from

APIC Clk StrapJP20A

Title: Intel 810e Chipset Customer Reference Board

Platform Components Division

Last Revision Date:

82810E, PART 1: HOST INTERFACE

Do not Stuff C365A

82810E, Part 1: Host Interface

Platform Components Division

Last Revision Date:

82810E, PART 2: SYSTEM MEMORY

Place C369A as close

Place HUBREF Generation

Place Resistor as Close

82810E, Part 2: System Memory and Hub

Platform Components Division

Last Revision Date:

82810E, PART 3: DISPLAY CACHE

AND VIDEO INTERFACE

*Out = IOQ Depth of 4

Place site w / in 0.5"

Use Surface Mount Caps

VIDEO DIGITAL OUT

GMCH RESET STRAPS

Title: Intel 810e Chipset Customer Reference Board

82810E, Part 3 : Display Cache and Video

Title: Intel 810e Chipset Customer Reference Board

Platform Components Division

Last Revision Date:

Title: Intel 810e Chipset Customer Reference Board

System Memory : DIMM0

Title: Intel 810e Chipset Customer Reference Board

Platform Components Division