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An Impact Ionization MOSFET With Reduced Breakdown Voltage Based on Back-

Gate Misalignment

Article  in  IEEE Transactions on Electron Devices · December 2018

DOI: 10.1109/TED.2018.2887168

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IEEE TRANSACTIONS ON ELECTRON DEVICES
An Impact Ionization MOSFET With Reduced
Breakdown Voltage Based on
Back-Gate Misalignment
Gaurav Musalgaonkar , Student Member, IEEE , Shubham Sahay , Student Member, IEEE ,
Raghvendra Sahai Saxena , and Mamidala Jagadesh Kumar , Senior Member, IEEE
Abstract — In this paper, we propose a misaligned double-
gate p-i-n impact ionization MOS (MIMOS) with a deliber-
ate misalignment between the top and bottom gates. The
presence of a misaligned bottom gate leads to band-to-
band-tunneling of electrons at the source-intrinsic region
interface and increases the number of carriers for impact
ionization. The electric field redistribution provides a longer
transport path for the carriers. Therefore, carriers gain
higher kinetic energy, and the impact ionization rate is
enhanced in the MIMOS. This results in a significantly lower
avalanche breakdown voltage compared to conventional
single-gate IMOS structure. Using calibrated 2-D simula-
tions, we demonstrate that MIMOS exhibits a steep sub-
threshold slope ( ∼6 mV/dec) at a significantly low-supply
voltage of (VDS = 0.59 V), which is ∼48% lower than that of
the corresponding single-gate IMOS (VDS = 1.15 V).
Index Terms — Avalanche breakdown, impact ionization,
low power, MOSFET, misaligned gate, steep subthreshold
slope.
I. I NTRODUCTION
T HE modern-day integrated circuits require MOSFETs
which can simultaneously offer a low-power dissipation
and a high speed. The low-power operation of the MOSFETs
is limited by the inability to scale the subthreshold swing (SS)
below 60 mV/dec [1]. However, several device architectures
with different turn on mechanisms such as band-to-band tun-
neling (BTBT) or impact ionization were proposed to reduce
the SS below the conventional limit of 60 mV/dec.
Although the tunneling field-effect transistor (TFET) based
on the carrier injection via BTBT [2]–[8] provides subthresh-
old slope lower than the theoretical limit, the low drive current
Manuscript received September 28, 2018; revised November 13, 2018;
accepted December 13, 2018. The review of this paper was arranged by
Editor R. M. Todi. (Corresponding author: Gaurav Musalgaonkar.)
G. Musalgaonkar is with the Solid-State Physics Laboratory,
DRDO, New Delhi 110054, India, and also with the Depart-
ment of Electrical Engineering, IIT Delhi, New Delhi 110016, India
(e-mail: gaurav.musalgaonkar7@gmail.com).
S. Sahay is with the California NanoSystems Institute, University of
California at Santa Barbara, Santa Barbara, CA 93106, USA (e-mail:
shubham.sahay.ece10@iitbhu.ac.in).
R. S. Saxena is with the Solid-State Physics Laboratory, DRDO, New
Delhi 110054, India (e-mail: rs_saxena@yahoo.com).
M. J. Kumar is with the Department of Electrical Engineering, IIT Delhi,
New Delhi 110016, India (e-mail: mamidala@ee.iitd.ac.in).
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TED.2018.2887168
0018-9383 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
1
in the ON-state is still a bottleneck. Moreover, ambipolar
conduction makes it unsuitable for various digital circuit oper-
ations [5]. Although various solutions have been proposed to
improve the drive current [9]–[14] and to reduce the ambipolar
conduction [15], [16] in TFET, a high ON-state current compa-
rable to MOSFET with a sub-60-mV/dec SS is yet to be real-
ized experimentally [4], [5], [17], [18]. The feedback FET [19]
and negative capacitance field-effect transistor [20], [21]
also show very steep SS compared to the conventional
MOSFET.
The impact ionization MOSFET (IMOS), which relies on
the impact ionization phenomena in reverse biased p-i-n struc-
ture, is considered as one of the most promising candidates
to realize low SS devices [22], [28]. However, the con-
ventional p-i-n IMOS requires a large operating voltage for
generating and sustaining charge carriers through an impact
ionization mechanism. Therefore, several solutions were pro-
posed to reduce the operating voltage of the conventional
p-i-n IMOS such as depletion IMOS [28], enhanced electric
(E2) IMOS [27], and bipolar IMOS [29], [30]. The use of
heterostructure of two different bandgap materials enhances
the electric field at the interface and leads to an increased
impact ionization in the E2-IMOS. The bipolar IMOS uses
the internal current gain mechanism of the parasitic bipo-
lar junction transistor to lower the breakdown voltage. The
impact ionization occurs in the bulk in the depletion mode
IMOS where the impact ionization coefficients are higher as
compared to the surface. Therefore, a lower drain voltage
is required for avalanche breakdown. However, despite these
innovations, the voltage required for impact ionization in
silicon-based IMOS is too high to be considered for low-
power (sub-1.0 V) applications according to the ITRS roadmap
for the sub-7-nm technology nodes [31]. Germanium, on the
other hand, can offer a lower breakdown voltage for IMOS
devices owing to its lower bandgap, lower critical fields
for avalanche breakdown, and nearly symmetrical impact-
ionization coefficient (αn , α p ) for both electrons and holes.
Recently, FETs without any metallurgical junction known
as junctionless FETs (JLFETS) were proposed [32]–[36].
The JLFETs exhibit a lower avalanche breakdown voltage
as compared to the conventional MOSFETs owing to the
bulk conduction and occurrence of peak electric field within
the drain region [32]. Several device architectures such as
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
2 IEEE TRANSACTIONS ON ELECTRON DEVICES
Fig. 1. (a) Conventional IMOS. (b) Proposed MIMOS structure.
back-gate engineering including independent gate operation,
misalignment [34], [36], and raised source/drain architec-
ture [37] were proposed in JLFETs to achieve a subbandgap
(<Eg /q) breakdown voltage. However, the increased sensitivity
of JLFETs toward process variations, the large source/drain
series resistance, and random dopant fluctuation (RDF) owing
to the heavily doped (∼1019 cm−3 ) channel region limit their
application. Since IMOS devices utilize an intrinsic channel
and heavily doped source/drain regions, they are more immune
to RDF and offer a low source/drain series resistance.
To lower the breakdown voltage of IMOS, a mechanism
is required to enhance the impact ionization process. This
may be achieved by increasing the number of charge carri-
ers or collisions. In this paper, we have proposed a double-
gate p-i-n IMOS with a deliberate misalignment between the
top and bottom gates to achieve sub-1.0-V breakdown voltage
for low-power applications. The misaligned gates lead to an
electric field redistribution in the channel region and elongate
the path of motion of the charge carriers during the impact
ionization process. Therefore, the carriers gain more energy
at lower operating voltages, and the impact ionization rate is
increased. Also, the bottom gate leads to a BTBT of carriers
at the source-channel interface. The BTBT generated carriers
further enhance the collisions resulting in a higher impact
ionization rate leading to a sub-1.0-V breakdown voltage in
the proposed MIMOS.
II. S TRUCTURE AND S IMULATION M ETHODOLOGY
The cross-sectional view of the conventional IMOS and the
proposed misaligned double-gate p-i-n impact ionization MOS
(MIMOS) is shown in Fig. 1. The only difference between
the MIMOS and conventional IMOS is that the bottom gate
is placed near the source edge in the MIMOS as compared to
the drain edge in the case of DGIMOS as shown in Fig. 1(b).
Double gate silicon on insulator MOSFETs with a misaligned
back gate, which can be shifted in steps of 15 nm using
electrical vernier, have been experimentally demonstrated
in [38]. Utilizing a similar process flow, the proposed MIMOS
may be experimentally realized. The parameters used for
device simulation are listed in Table I. The simulations were
performed using ATLAS device simulator ver: 5.22.1 [39].
We have followed the same approach in our simulations as
suggested by Mayer et al. [24]. The concentration- and field-
dependent mobility for considering the scattering mechanisms
were used. Selberherr model was used to account for impact
ionization. Shockley–Read–Hall model, bandgap narrowing
model, and Fermi–Dirac carrier statistics were also considered.
The BTBT model was included to take into account the
TABLE I
D EVICE PARAMETERS
Fig. 2. Calibrated simulation setup by reproducing the reported results
of (a) germanium IMOS [22] and (b) silicon IMOS [44].
BTBT leakage in the OFF-state of IMOS devices. The impact
ionization coefficients used for analyzing Ge-IMOS transistor
were obtained from [40] and [41].
It may be noted that the main aim of this paper is to
evaluate the impact of the top and bottom gates misalignment
on the breakdown voltage of IMOS. Therefore, the impact
ionization parameters for germanium IMOS were calibrated by
reproducing the simulation results reported in [22] as shown in
Fig. 2(a). The simulation results of [22] are in good agreement
with the experimental results of [42]. It may be noted that a
similar approach was adopted in [33] and [43] for analyzing
impact ionization in germanium JLFETs. Furthermore, using
the same set of models for silicon, our simulation setup is able
to accurately reproduce the breakdown characteristics of the
silicon IMOS of [44] as shown in Fig. 2(b).
III. R ESULTS AND D ISCUSSION
Fig. 3 shows the comparison of the output characteristics
of the conventional and proposed Ge-MIMOS structure at
VGS = 0 V. It can be observed that in the conventional IMOS,
breakdown occurs at VDS ∼ 1.15 V. However, in the MIMOS
avalanche breakdown occurs at only VDS ∼ 0.59 V. Fig. 4
shows the energy band diagram just before the breakdown
for conventional IMOS and MIMOS along the cut line A–A
(1 nm below the top gate), B–B (1 nm above the bottom
gate), and C–C (in the center of the germanium film) as
shown in Fig. 1. For the conventional IMOS, VDS = 0.9
V, VGD = 0.2 V and for the proposed MIMOS structure,
VDS = 0.4 V, VGD = 0.15 V are applied. For the conventional
IMOS, the energy bands appear almost same throughout the
semiconductor film thickness (TSc ) indicating uniform BTBT
and impact ionization rate at the source-channel interface
owing to uniform electric field in the intrinsic region. However,
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MUSALGAONKAR et al.: IMPACT IONIZATION MOSFET WITH REDUCED BREAKDOWN VOLTAGE
Fig. 3. Output characteristics of the conventional IMOS and proposed
MIMOS.
Fig. 4. Energy band profiles of (a) conventional IMOS and (b) proposed
MIMOS just before the avalanche breakdown. For conventional IMOS
VDS = 0.9 V and VGD = 0.2 V and for MIMOS VDS = 0.4 V and
VGD = 0.15 V
Fig. 5. Lateral electric field of (a) conventional IMOS and (b) proposed
MIMOS at the onset of avalanche breakdown.
in the MIMOS, a sharp band bending is observed at the source-
channel interface just before breakdown voltage along the
cutline B–B’. This band bending aligns the valence band of
the source with the conduction band of the intrinsic region
(L I ). Carriers are injected into the channel region via BTBT
from the source region due to this band alignment. The BTBT
increases the number of carriers available for impact ionization
in the intrinsic region. This enhances the impact ionization
rate in the MIMOS. Fig. 5 shows the electric field profile for
both the conventional and MIMOS structure at the onset of
avalanche breakdown.
As can be observed in Fig. 5(a), in the conventional IMOS,
most of the electric fields drop across the intrinsic region (L I ).
The electric field peaks at the gate edge and source-channel
junction and is minimum under the gate region (L G ). As a
3
Fig. 6. 2-D contour plot (at the onset of breakdown) of electron and hole
current density, respectively. (a) and (b) Conventional IMOS. (c) and (d)
Proposed MIMOS.
result, avalanche breakdown is most likely to be initiated in the
intrinsic region. Once the avalanche breakdown occurs, gener-
ated electrons (holes) drift toward the drain (source) terminal,
respectively, as shown in Fig. 6. Therefore, the motion of
the charge carriers before gaining the required kinetic energy
and initiating avalanche multiplication is limited to L I region
where the electric field is very high. On the other hand, in the
proposed MIMOS, at the middle of the germanium film, in the
region common to the top and bottom gates, the electric field
is minimum and increases on either side as shown in Fig. 5(b).
This electric field redistribution enables the carriers to
traverse along a longer inclined path as shown in Fig. 6(c)
in contrast to the horizontal conduction path in conventional
IMOS. Therefore, the carriers move a longer distance in
MIMOS gaining more kinetic energy and momentum before
impact ionization leading to an increased impact ionization
rate.
Also, in the MIMOS, the inversion layer is formed under
both gates. Therefore, the entire channel potential drops across
the intrinsic regions (L I 1 and L I 2 ) away from the gates.
This increases the lateral electric field in the intrinsic regions
(L I 1 and L I 2 ). At the source-channel interface near the bot-
tom gate, the large electric field induces sharp band bending
and facilitates BTBT of carriers from source to intrinsic region
increasing the impact ionization rate further. All these factors
result in a higher impact ionization in MIMOS leading to a
lower breakdown voltage.
Although the placement of the bottom gate near to the
source side can significantly reduce the breakdown voltage
of an IMOS device, as shown in Fig. 3, the OFF-state current
increases considerably for the MIMOS. It may be noted that
the OFF-state current is defined as the drain current at the
zero-gate voltage (VGS ) for a fixed value (near the breakdown
voltage) of the drain-to-source voltage (VDS ) and the ON-
state current is defined as the drain current when VGS =
VDS = VDD .
The OFF-state current of the conventional IMOS comprises
of p-i-n diode reverse leakage current and tunneling current.
As can be observed from Fig. 7(a), a higher BTBT rate near the
source-channel interface adjacent to the bottom gate, which is
responsible for reduced breakdown voltage also increases the
OFF -state current. Therefore, there is a tradeoff between the
OFF -state current and the breakdown voltage in MIMOS.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
4 IEEE TRANSACTIONS ON ELECTRON DEVICES
Fig. 7. 2-D contour plot (just before the breakdown) of (a) BTBT rate of
proposed MIMOS, (b) bottom gate shifted by 5 nm toward the drain side;
Impact generation rate for (c) conventional IMOS and (d) MIMOS.
Fig. 8. (a) Output characteristics and (b) transfer curve for conventional
IMOS and for proposed MIMOS with changing bottom gate location.
(c) Energy band profiles along B–B for partial misaligned and proposed
MIMOS at zero gate voltage. (d) Conventional and complete aligned.
To reduce the BTBT induced OFF-state current, the bottom
gate may be shifted away from the source-channel interface
toward the drain as shown in Fig. 7(b). As can be seen from
Fig. 8(b), partial MIMOS in which bottom gate is shifted
by 5 nm away from the source-channel interface exhibits
a reduction in OFF-state current by nearly four times of
magnitude (IOFF = 8 × 10−11 ) compared to the case when
the bottom gate is completely aligned to the source interface
(IOFF = 2.1×10−10) due to lower BTBT as shown in Fig. 7(b).
As we further shift the position of the bottom gate toward the
drain side, the OFF-state current decreases further. However,
the avalanche breakdown voltage (VBD ) is increased.
Fig. 8(a) shows the output characteristic showing increase in
the avalanche breakdown voltage as the bottom gate is shifted
away from the source-channel interface. This observation
clearly indicates that BTBT enhances the carriers for impact
generation and leads to higher impact ionization rate at the
source-channel interface as shown in Fig. 7(d). Therefore,
it may be concluded that BTBT-assisted impact ionization
lowers the breakdown voltage in the MIMOS.
As shown in Fig. 8(a), for a completely aligned structure
(with both top and bottom gates near to drain side which
resembles double-gate IMOS), the breakdown voltage is large
(VBD = 0.96 V). However, the breakdown voltage is still
lower than the conventional single-gate IMOS. Furthermore,
the rise in the drain current for completely aligned IMOS is
very steep compared to conventional IMOS. This is due to the
enhanced electric field in the intrinsic region (L I ) compared
to conventional single-gate IMOS. Fig. 8(b) compares the
transfer characteristics of the proposed MIMOS with different
bottom gate configurations and conventional IMOS. As shown
in Fig. 8(b), MIMOS exhibits an ON-state to OFF-state current
ratio (ION /IOFF ) of ∼106 with a minimum subthreshold slope
of 6 mV/dec at an ultralow supply voltage (VDS = 0.4 V).
Also, the back-gate misalignment does not affect the ON-
state performance of the MIMOS. This is attributed to the
drift-diffusion transport mechanism for the impact ionization
generated carriers in the ON-state current of IMOS devices
[22]–[24]. It can also be seen from Fig. 8(b) that the OFF-state
current in the MIMOS is slightly higher compared to the
other structures. This is because in MIMOS with complete
misaligned back gate, there exists a significant overlap of the
valence band of the source region and the conduction band
of the channel region even in the OFF-state (VGS = 0 V) as
shown in Fig. 8(c). This results in a higher BTBT at the
source-channel interface near the bottom gate and increases the
OFF -state current as discussed previously. However, for con-
ventionally, completely aligned, and partially aligned IMOS
structures, Shockley Read Hall (SRH) recombination remains
the dominant OFF-state leakage mechanism, and the OFF-
state current remains nearly the same. Although there is a
band alignment in the conventional IMOS and the completely
aligned IMOS which may facilitate tunneling, the tunneling
distance is significantly large as shown in Fig. 8(d). There-
fore, SRH recombination remains the dominant mechanism
dominating the OFF-state current. The performance of different
IMOS devices under consideration is compared in Table II.
Although the misaligned back gate in MIMOS may be
experimentally realized using electrical vernier [38], a certain
degree of unintentional misalignment may be present in the
fabricated structure. It is, therefore, essential to evaluate the
sensitivity of the MIMOS performance to those misalignments.
The output characteristics of the MIMOS with the bot-
tom gate overlapping the source and shifted away from the
source-channel interface (underlap) have been compared in
Fig. 9(a) and (c), respectively, to analyze the impact of align-
ment of the bottom gate with the source-channel interface.
The breakdown voltage increases when the bottom gate either
overlaps the source region or is shifted away from the source-
channel interface. The source region overlapping the bottom
gate gets depleted due to the bottom gate electrode, and the
effective tunneling width increases as shown in Fig. 9(b). Also,
shifting the bottom gate away from the source-channel inter-
face (underlap) reduces the band banding at the source-channel
interface. This results in an increased tunneling distance as
shown in Fig. 9(d) reducing the overall BTBT generation rate
which assists the impact ionization phenomenon. As a result,
the breakdown voltage increases. Therefore, the bottom gate
must be aligned at the source-channel interface for achieving
optimum performance. Fig. 10(a) indicates that the breakdown
voltage does not change when the bottom gate length is
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
MUSALGAONKAR et al.: IMPACT IONIZATION MOSFET WITH REDUCED BREAKDOWN VOLTAGE
TABLE II
D EVICE PARAMETERS AT VARIOUS G EOMETRIES
Fig. 9. (a) Output curve of proposed MIMOS with bottom gate shifted
toward the source. (b) Energy band profiles along B–B just before the
avalanche breakdown. (c) Output curve of proposed MIMOS with bottom
gate shifted toward the drain. (d) Energy band profiles along B–B just
before the avalanche breakdown.
Fig. 10. (a) Output curve of the proposed MIMOS with complete
bottom gate between the source and drain. (b) Lateral electric field of
the proposed MIMOS and complete bottom gate IMOS at the onset of
avalanche breakdown.
increased toward the drain side keeping one edge fixed at the
source-channel interface. This is because the electric field at
the source-channel interface above the bottom gate remains
nearly the same even when the bottom gate length is increased
as shown in Fig. 10(b). There is only a slight reduction in the
peak electric field at the source-bottom gate interface when
the bottom gate extends below the entire active device layer,
5
Fig. 11. (a) Proposed MIMOS with both bottom and top gate lengths
fixed at 25 nm. (b) Bottom gate length variation keeping top gate length
fixed at 25 nm. (c) Top gate length variation keeping bottom gate
length fixed at 25 nm.
Fig. 12. Output characteristics of the proposed MIMOS for the different
top gate to bottom gate lengths. (a) Top gate is fixed at 25 nm and bottom
gate length is varied. (b) Bottom gate is fixed at 25 nm and top gate length
is varied.
i.e., from source end to drain end. Also, this reduction in the
electric field is compensated by an increased electric field in
the ungated region L I 1 . This compensation ensures that the
breakdown voltage does not change significantly.
The impact of gate length scaling on the breakdown voltage
of MIMOS is analyzed by scaling the top gate and the
bottom gate length as shown in Fig. 11. Fig. 12(a) shows
the output characteristic of the MIMOS for different bottom
gate lengths (L G2 ) while keeping the top gate length (L G1 )
fixed at 25 nm. The electric field in the intrinsic region (L I 1 )
and at the source-channel interface increases when the length
of the bottom gate is reduced below the top gate length.
A higher electric field at the source-channel interface results
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
6 IEEE TRANSACTIONS ON ELECTRON DEVICES
Fig. 13. Output characteristics for the conventional IMOS and for the
proposed MIMOS as a function of temperature. (a) Conventional IMOS.
(b) Proposed MIMOS.
in a higher BTBT generation rate leading to an increased
OFF -state current. It may also be noted that the breakdown
voltage decreases somewhat with a reduction in the bottom
gate length, attains a minimum at L G2 = 20 nm, and then
begins to increase for L G2 < 20 nm. The reduction in the
breakdown voltage till L G2 = 20 nm can be understood by
the higher electric field at the source-channel interface and in
the intrinsic region (L I 1 ) away from the bottom gate which
leads to a larger BTBT resulting in a higher impact generation
rate. However, when L G2 reduces below 20 nm, the effective
intrinsic region length (L I 1 ) where the generation of charge
carriers takes place decreases. As a result, the impact generated
carriers are not able to traverse sufficient distance and acquire
enough kinetic energy to knock off electrons from the atoms.
This leads to an increased breakdown voltage. On the other
hand, as shown in Fig. 12(b), the breakdown voltage does not
change significantly when the top gate is scaled. As the top
gate is scaled from 25 to 10 nm [Fig. 11(c)], a slight reduction
in the breakdown voltage is observed owing to an increased
electric field in the intrinsic region with length L I 2 . However,
for L G1 = 5 nm, the breakdown voltage increases somewhat
owing to the reduction in the intrinsic region where the impact
generated carriers traverse and gain kinetic energy.
The impact of the temperature variation on the breakdown
voltage of the conventional as well as the proposed MIMOS
has been analyzed in Fig. 13. As can be observed from
Fig. 13(a) and (b), the breakdown voltage decreases with a
reduction in the operating temperature. This is consistent with
the results reported in [43] and attributed to the increased
entropy of the impact generated carriers. At high temperature,
the impact generated carriers follow a random path and lose
some energy due to random collisions. Therefore, a larger
voltage is required to accelerate the carriers so that they gain
sufficient kinetic energy to knock off electrons from the atoms.
In our simulation setup, the temperature dependence of impact
ionization is accounted for by the parameters A N , B N and
A P , B p in the impact ionization coefficient for electron and
holes [38] as shown in the following equations. The impact
ionization coefficients are modeled as
 −B  Mn
n
αn = A N e ξ
 −B p  M p
αp = A pe ξ
where αn and α p are the electron and hole impact ionization
coefficient, ξ is the electric field in the direction of current
flow, and Mn , M p are the dimensionless empirical smoothing
parameter used to fit the experimental data. The temperature
dependence of impact ionization is accounted for by the
parameters A N , B N and A p , B p which govern the impact
ionization coefficient for electrons and holes, respectively. Fur-
thermore, the parameters A N , A P, B N, B p can be expressed as
   
T M An
A N = A N1,2 1 + A · NT −1 (3)
300
   
T M Ap
A p = A P1,2 1 + A · PT −1 (4)
300
   
T M Bn
B N = B N1,2 1 + B · NT −1 (5)
300
   
T M Bp
B p = B P1,2 1 + B · PT −1 (6)
300
where T is the lattice temperature, A N1,2 and A P1,2 are
the maximum number of electrons and holes, respectively,
that may be generated per unit distance at high electric
fields due to impact ionization, B N1,2 and B P1,2 are the
electric field-dependent ionization parameters, and M An ,
M Ap , M Bn , and MBP are the dimensionless empirical
smoothing parameter used to fit the experimental data. Based
on the above-mentioned model, the ionization coefficients
may be extracted to fit the experimental measurements [41].
From (1)–(6), the ionization coefficient ratio K = (αn /α p ),
decreases with an increase in temperature [45]. This results in
a higher breakdown voltage. Furthermore, Fig. 13 also shows
the variation of the OFF-state current in conventional and
proposed MIMOS with temperature. The OFF-state current
increases in the conventional IMOS with temperature owing to
the strong dependence of the SRH mechanism which dictates
the OFF-state current [45]. However, BTBT phenomena
are the dominant mechanism for the OFF-state current in
MIMOS. Since the BTBT mechanism has a weak dependence
on the temperature [46], the OFF-state current in the MIMOS
does not change considerably with an increase in the
temperature.
RDFs in IMOS may result in variation of device para-
meters such as threshold voltage, breakdown voltage, and
drive current capabilities [47]. However, techniques based on
electrostatic doping of the source/drain regions via charge
plasma or polarity gate may be used as an alternative to avoid
the RDF of the conventionally doped IMOS [30], [13], [48].
The analysis of RDF in MIMOS is an important future work
IV. C ONCLUSION
In this paper, a double-gate IMOS based on deliberate
misalignment (MIMOS) between the top and bottom gates is
presented. It has been shown that the misalignment between
the top and bottom gates can increase the carriers due to
(1) BTBT and lead to an inclined longer motion path for the
carriers prior to avalanche multiplication. These factors lead
(2) to a significant reduction in the voltage required for avalanche
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
MUSALGAONKAR et al.: IMPACT IONIZATION MOSFET WITH REDUCED BREAKDOWN VOLTAGE
multiplication induced breakdown. Using TCAD simulation
for Ge-MIMOS, a breakdown voltage of 0.59 V has been
demonstrated. Although we have analyzed the performance
improvement for germanium devices targeting subunity break-
down voltages, in this paper, the breakdown voltage is reduced
by 1.4 V when this architecture is employed in the silicon
IMOS. Therefore, the proposed MIMOS could be a lucrative
alternative to the conventional IMOS. Our results may provide
the incentive for its experimental realization.
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 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.
8 IEEE TRANSACTIONS ON ELECTRON DEVICES

[41] T. Mikawa, S. Kagawa, T. Kaneda, Y. Toyama, and O. Mikami, “Crystal Shubham Sahay (S’16) received the Ph.D.
orientation dependence of ionization rates in germanium,” Appl. Phys. degree in electrical engineering from IIT Delhi,
Lett., vol. 37, no. 4, pp. 387–389, Jul. 1980, doi: 10.1063/1.91932. New Delhi, India, in 2018.
[42] K. Gopalakrishnan, R. Woo, C. Jungemann, P. B. Griffin, and He is currently a Post-Doctoral Associate with
J. D. Plummer, “Impact ionization MOS (I-MOS)-part II: Experimental the University of California at Santa Barbara,
results,” IEEE Trans. Electron Devices, vol. 52, no. 1, pp. 77–84, Santa Barbara, CA, USA. His current research
Jan. 2005, doi: 10.1109/TED.2004.841345. interests include semiconductor device design
[43] M. Gupta and A. Kranti, “Variation of threshold voltage with temper- and modeling.
ature in impact ionization-induced steep switching Si and Ge junc-
tionless MOSFETs,” IEEE Trans. Electron Devices, vol. 64, no. 5,
pp. 2061–2066, May 2017, doi: 10.1109/ted.2017.2679218.
[44] E.-H. Toh, G. H. Wang, L. Chan, G. S. Samudra, and Y.-C. Yeo,
“Device physics and performance optimization of impact-ionization
metal–oxide–semiconductor transistors formed using a double-spacer
fabrication process,” Jpn. J. Appl. Phys., vol. 47, no. 4s, pp. 3077–3080,
Apr. 2008, doi: 10.1143/jjap.47.3077.
[45] D. J. Massey, J. P. R. David, and G. J. Rees, “Temperature dependence
of impact ionization in submicrometer silicon devices,” IEEE Trans. Raghvendra Sahai Saxena received the Ph.D.
Electron Devices, vol. 53, no. 9, pp. 2328–2334, Sep. 2006, doi: 10.1109/ degree from IIT Delhi, New Delhi, India, in 2012.
ted.2006.881010. Since 1998, he has been a Scientist with the
[46] R. Narang, M. Saxena, R. S. Gupta, and M. Gupta, “Impact of tempera- Solid-State Physics Laboratory (SSPL), DRDO,
ture variations on the device and circuit performance of tunnel FET: New Delhi. His current research interests include
A simulation study,” IEEE Trans. Nanotechnol., vol. 12, no. 6, nanoscale very large scale integration devices
pp. 951–957, Nov. 2013, doi: 10.1109/tnano.2013.2276401. and circuits.
[47] Y. Li, C.-H. Hwang, and T.-Y. Li, “Random-dopant-induced variability Dr. Saxena is an Editor of the IETE Technical
in Nano-CMOS devices and digital circuits,” IEEE Trans. Electron Review and the SSPL Technical Bulletin-Crystal.
Devices, vol. 56, no. 8, pp. 1588–1597, Aug. 2009, doi: 10.1109/ He is an American Society for Quality Certified
ted.2009.2022692. Reliability Engineer.
[48] S. Singh and P. N. Kondekar, “A novel dynamically configurable
electrostatically doped silicon nanowire impact ionization MOS,” Super-
lattices Microstruct., vol. 88, pp. 695–703, Dec. 2015, doi: 10.1016/
j.spmi.2015.10.033.

Gaurav Musalgaonkar (S’18) is currently pur- Mamidala Jagadesh Kumar (SM’98) is a Pro-
suing the Ph.D. degree with the Department fessor (on lien) with IIT Delhi, New Delhi, India.
of Electrical Engineering, IIT Delhi, New Delhi, He is currently the Vice-Chancellor of Jawahar-
India. lal Nehru University, New Delhi.
His current research interests include nano- Mr. Kumar was an Editor of the IEEE Trans-
electronics, semiconductor device modeling, and actions on Electron Devices. He is currently the
CMOS image sensors. Editor-in-Chief of the IETE Technical Review and
an Editor of the IEEE Journal of the Electron
Devices Society.

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